update=Вс 27 янв 2019 15:05:22
version=1
last_client=kicad
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60
[eeschema]
version=1
LibDir=
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=Chiller_control.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.5
TrackWidth2=0.25
TrackWidth3=0.5
TrackWidth4=1
TrackWidth5=2
ViaDiameter1=1.2
ViaDrill1=0.6
ViaDiameter2=1.2
ViaDrill2=0.6
ViaDiameter3=1.5
ViaDrill3=0.8
ViaDiameter4=2.5
ViaDrill4=1
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.2
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Netclasses]
[pcbnew/Netclasses/1]
Name=power
Clearance=0.3
TrackWidth=1
ViaDiameter=2.5
ViaDrill=0.8
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/2]
Name=wide
Clearance=0.5
TrackWidth=2
ViaDiameter=2.5
ViaDrill=0.8
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25