encoders works fine

F1:F103/BISS_C_encoders/openocd.cfg

@@ -1,94 +1,4 @@
 set FLASH_SIZE 0x10000
 
 source [find interface/stlink.cfg]
-
-
-# script for stm32f1x family
-
-#
-# stm32 devices support both JTAG and SWD transports.
-#
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
-   set _CHIPNAME $CHIPNAME
-} else {
-   set _CHIPNAME stm32f1x
-}
-
-set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-# By default use 4kB (as found on some STM32F100s)
-if { [info exists WORKAREASIZE] } {
-   set _WORKAREASIZE $WORKAREASIZE
-} else {
-   set _WORKAREASIZE 0x1000
-}
-
-# Allow overriding the Flash bank size
-if { [info exists FLASH_SIZE] } {
-    set _FLASH_SIZE $FLASH_SIZE
-} else {
-    # autodetect size
-    set _FLASH_SIZE 0
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   if { [using_jtag] } {
-      # See STM Document RM0008 Section 26.6.3
-      set _CPUTAPID 0x2ba01477
-   } {
-      # this is the SW-DP tap id not the jtag tap id
-      set _CPUTAPID 0x2ba01477
-   }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-if {[using_jtag]} {
-   jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# flash size will be probed
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-reset_config srst_nogate
-
-if {![using_hla]} {
-    # if srst is not fitted use SYSRESETREQ to
-    # perform a soft reset
-    cortex_m reset_config sysresetreq
-}
-
-$_TARGETNAME configure -event examine-end {
-	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
-	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
-	mmw 0xE0042004 0x00000307 0
-}
-
-$_TARGETNAME configure -event trace-config {
-	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
-	# change this value accordingly to configure trace pins
-	# assignment
-	mmw 0xE0042004 0x00000020 0
-}
+source [find target/stm32f1x.cfg]