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Add kicad schematic and PCB

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Edward Emelianov
2024-12-19 11:40:50 +03:00
parent f9d9735a5e
commit f26970392e
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F1:F103/Hall_linear/kicad/gerbers/Hall-drl.rpt Normal file
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Drill report for Hall.kicad_pcb
Created on 2024-12-19T11:27:46+0300
Copper Layer Stackup:
=============================================================
L1 : F.Cu front
L2 : B.Cu back
Drill file 'Hall.drl' contains
plated through holes:
=============================================================
T1 0.400mm 0.0157" (1 hole)
T2 0.600mm 0.0236" (27 holes)
T3 0.600mm 0.0236" (4 holes) (with 4 slots)
T4 0.650mm 0.0256" (6 holes)
T5 0.800mm 0.0315" (3 holes)
T6 1.000mm 0.0394" (3 holes)
T7 1.100mm 0.0433" (3 holes)
Total plated holes count 47
Not plated through holes are merged with plated holes
unplated through holes:
=============================================================
T8 0.650mm 0.0256" (2 holes)
T9 3.200mm 0.1260" (3 holes)
Total unplated holes count 5