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add simple work with fonts (too small for this screen), still have some bugs with sprites in lower right corner

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This commit is contained in:
Edward Emelianov
2023-05-11 00:36:10 +03:00
parent eda7d9127a
commit d88de360d0
16 changed files with 4917 additions and 64 deletions
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94
F3:F303/NitrogenFlooding/spi.c
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@@ -30,18 +30,35 @@ spiStatus spi_status = SPI_NOTREADY;
volatile uint32_t wctr;
#define WAITX(x) do{wctr = 0; while((x) && (++wctr < 360000)) IWDG->KR = IWDG_REFRESH; if(wctr==360000){ DBG("timeout"); return 0;}}while(0)
// SPI DMA Rx buffer (set by spi_write_dma call)
static uint8_t *rxbufptr = NULL;
static uint32_t rxbuflen = 0;
// init SPI2 to work with and without DMA
// ILI9341: SCL 0->1; CS=0; command - DC=0, data - DC=1; 1 dummy clock pulse before 24/32 bit data read
// Channel 4 - SPI2 Rx
// Channel 5 - SPI2 Tx
void spi_setup(){
SPI2->CR1 = 0; // clear EN
//RCC->APB1RSTR = RCC_APB1RSTR_SPI2RST; // reset SPI
RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
RCC->AHBENR |= RCC_AHBENR_DMA1EN;
// Baudrate = 0b011 - fpclk/16 = 2MHz; software slave management (without hardware NSS pin)
SPI2->CR1 = /*SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE |*/ SPI_CR1_MSTR | SPI_CR1_BR_0 | SPI_CR1_BR_1 | SPI_CR1_SSM | SPI_CR1_SSI;
SPI2->CR1 = SPI_CR1_MSTR | SPI_CR1_BR_0 | SPI_CR1_BR_1 | SPI_CR1_SSM | SPI_CR1_SSI;
// 8bit; RXNE generates after 8bit of data in FIFO
SPI2->CR2 = SPI_CR2_FRXTH | SPI_CR2_DS_2|SPI_CR2_DS_1|SPI_CR2_DS_0 /*| SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN*/;
SPI2->CR2 = SPI_CR2_FRXTH | SPI_CR2_DS_2|SPI_CR2_DS_1|SPI_CR2_DS_0 | SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN;
// setup SPI2 DMA
// Tx
DMA1_Channel5->CPAR = (uint32_t)&(SPI2->DR); // hardware
DMA1_Channel5->CCR = DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TEIE; // memory increment, mem->hw, error interrupt
// Rx
DMA1_Channel4->CPAR = (uint32_t)&(SPI2->DR);
DMA1_Channel4->CCR = DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_TEIE; // mem inc, hw->mem, Rx complete and error interrupt
NVIC_EnableIRQ(DMA1_Channel4_IRQn); // enable Rx interrupt
NVIC_EnableIRQ(DMA1_Channel5_IRQn); // enable Tx interrupt
spi_status = SPI_READY;
SPI2->CR1 |= SPI_CR1_SPE;
DBG("SPI works");
}
int spi_waitbsy(){
@@ -63,21 +80,41 @@ int spi_write(const uint8_t *data, uint32_t n){
for(uint32_t x = 0; x < n; ++x){
WAITX(!(SPI2->SR & SPI_SR_TXE));
SPIDR = data[x];
//WAITX(!(SPI2->SR & SPI_SR_RXNE));
//data[x] = SPI2->DR; // clear RXNE after last things
}
return 1;
}
/**
* @brief spi_send_dma - send data over SPI2 through DMA
* @brief spi_send_dma - send data over SPI2 through DMA (used both for writing and reading)
* @param data - data to read
* @param rxbuf - pointer to receiving buffer (at least n bytes), can be also `data` (if `data` isn't const)
* @param n - length of data
* @return 0 if failed
* !!! `data` buffer can be changed only after SPI_READY flag!
*/
int spi_write_dma(const uint8_t _U_ *data, uint32_t _U_ n){
int spi_write_dma(const uint8_t *data, uint8_t *rxbuf, uint32_t n){
if(spi_status != SPI_READY) return 0;
return 0;
rxbufptr = rxbuf;
rxbuflen = n;
if(!spi_waitbsy()) return 0;
// clear SPI Rx FIFO
(void) SPI2->DR;
while(SPI2->SR & SPI_SR_RXNE) (void) SPI2->DR;
//DMA1_Channel4->CCR &= ~DMA_CCR_EN; // turn off to reconfigure
//DMA1_Channel5->CCR &= ~DMA_CCR_EN;
DMA1_Channel5->CMAR = (uint32_t) data;
DMA1_Channel5->CNDTR = n;
// check if user want to receive data
if(rxbuf){
DMA1_Channel4->CCR |= DMA_CCR_TCIE;
DMA1_Channel5->CCR &= ~DMA_CCR_TCIE; // turn off Tx ready interrupt
DMA1_Channel4->CMAR = (uint32_t) rxbuf;
DMA1_Channel4->CNDTR = n;
DMA1_Channel4->CCR |= DMA_CCR_EN; // turn on reception
}else DMA1_Channel5->CCR |= DMA_CCR_TCIE; // interrupt by Tx ready - user don't want reception
spi_status = SPI_BUSY;
DMA1_Channel5->CCR |= DMA_CCR_EN; // turn on transmission
return 1;
}
/**
@@ -86,31 +123,52 @@ int spi_write_dma(const uint8_t _U_ *data, uint32_t _U_ n){
* @param n - length of data
* @return n
*/
int spi_read(uint8_t _U_ *data, uint32_t _U_ n){
int spi_read(uint8_t *data, uint32_t n){
if(spi_status != SPI_READY){
DBG("not ready");
return 0;
}
//SPI2->CR1 &= ~SPI_CR1_BIDIOE; // Rx
if(!spi_waitbsy()) return 0;
// clear SPI Rx FIFO
(void) SPI2->DR;
while(SPI2->SR & SPI_SR_RXNE) (void) SPI2->DR;
for(uint32_t x = 0; x < n; ++x){
WAITX(!(SPI2->SR & SPI_SR_TXE));
SPIDR = 0;
WAITX(!(SPI2->SR & SPI_SR_RXNE));
data[x] = SPI2->DR;
data[x] = SPIDR;
USB_sendstr("rd got "); USB_sendstr(uhex2str(data[x]));
newline();
}
//SPI2->CR1 |= SPI_CR1_BIDIOE; // turn off clocking
return 1;
}
/**
* @brief spi_read_dma - read SPI2 data through DMA
* @param data - data to read
* @param n - length of data
* @return n
* @brief spi_read_dma - got buffer read by DMA
* @param n (o) - length of rxbuffer
* @return amount of bytes read
*/
int spi_read_dma(uint8_t _U_ *data, uint32_t _U_ n){
if(spi_status != SPI_READY) return 0;
return 0;
uint8_t *spi_read_dma(uint32_t *n){
if(spi_status != SPI_READY || rxbuflen == 0) return NULL;
if(n) *n = rxbuflen - DMA1_Channel4->CNDTR; // in case of error buffer would be underfull
rxbuflen = 0; // prevent consequent readings
return rxbufptr;
}
// Rx ready interrupt
void dma1_channel4_isr(){
spi_status = SPI_READY; // ready independent on errors or Rx ready
DMA1->IFCR = DMA_IFCR_CTCIF4 | DMA_IFCR_CTEIF4;
// turn off DMA
DMA1_Channel4->CCR &= ~DMA_CCR_EN;
DMA1_Channel5->CCR &= ~DMA_CCR_EN;
}
// Tx ready interrupt
void dma1_channel5_isr(){
spi_status = SPI_READY; // ready independent on errors or Tx ready
DMA1->IFCR = DMA_IFCR_CTCIF5 | DMA_IFCR_CTEIF5;
// turn off DMA
DMA1_Channel4->CCR &= ~DMA_CCR_EN;
DMA1_Channel5->CCR &= ~DMA_CCR_EN;
}