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seems like I2C start works right, need some fixes for large data amount

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This commit is contained in:
Edward Emelianov 2025-09-14 02:18:36 +03:00
parent 93e0b16f79
commit d790a1610d
7 changed files with 317 additions and 67 deletions
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85
F3:F303/I2C_scan/i2c.c
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@ -64,15 +64,21 @@ void i2c_setup(I2C_SPEED speed){
GPIOB->PUPDR = (GPIOB->PUPDR & !(GPIO_PUPDR_PUPDR6 | GPIO_PUPDR_PUPDR7)) | GPIOB->PUPDR = (GPIOB->PUPDR & !(GPIO_PUPDR_PUPDR6 | GPIO_PUPDR_PUPDR7)) |
GPIO_PUPDR6_PU | GPIO_PUPDR7_PU; // pullup (what if there's no external pullup?) GPIO_PUPDR6_PU | GPIO_PUPDR7_PU; // pullup (what if there's no external pullup?)
GPIOB->OTYPER |= GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7; // both open-drain outputs GPIOB->OTYPER |= GPIO_OTYPER_OT_6 | GPIO_OTYPER_OT_7; // both open-drain outputs
// I2C (default timing from PCLK - 64MHz) // I2C (default timing from sys clock - 72MHz)
RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // clocking RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // clocking
if(speed == LOW_SPEED){ // 10kHz if(speed == HIGH_SPEED){
// PRESC=F, SCLDEL=4, SDADEL=2, SCLH=0xC3, SCLL=0xC7 // activate "fast mode plus"
I2C1->TIMINGR = (0xF<<28) | (4<<20) | (2<<16) | (0xC3<<8) | (0xC7); SYSCFG->CFGR1 |= SYSCFG_CFGR1_I2C1_FMP | SYSCFG_CFGR1_I2C_PB6_FMP | SYSCFG_CFGR1_I2C_PB7_FMP;
}else if(speed == HIGH_SPEED){ // 100kHz }else{
I2C1->TIMINGR = (0xF<<28) | (4<<20) | (2<<16) | (0xF<<8) | (0x13); SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_I2C1_FMP | SYSCFG_CFGR1_I2C_PB6_FMP | SYSCFG_CFGR1_I2C_PB7_FMP);
}else{ // VERYLOW_SPEED - the lowest speed by STM register: ~7.7kHz }
I2C1->TIMINGR = (0xF<<28) | (4<<20) | (2<<16) | (0xff<<8) | (0xff); if(speed == LOW_SPEED){ // 100kHz
I2C1->TIMINGR = (0xf<<28) | (0x04<<20) | (0x03<<16) | (0x12<<8) | (0x15);
// PRESC SCLDEL SDADEL SCLH SCLL
}else if(speed == HIGH_SPEED){ // 400kHz
I2C1->TIMINGR = (0x06<<28) | (0x04<<20) | (0x03<<16) | (0x06<<8) | (0x08);
}else{ // VERYLOW_SPEED - 10kHz
I2C1->TIMINGR = (0xf<<28) | (0x04<<20) | (0x03<<16) | (0xc3<<8) | (0xc7);
} }
I2C1->CR1 = I2CCR1; I2C1->CR1 = I2CCR1;
RCC->AHBENR |= RCC_AHBENR_DMA1EN; RCC->AHBENR |= RCC_AHBENR_DMA1EN;
@ -97,31 +103,37 @@ static void i2cDMAsetup(int tx, uint8_t len){
} }
} }
static uint8_t i2c_start(uint8_t busychk){ static uint8_t i2c_chk(uint8_t busychk){
I2C1->CR2 = 0;
if(busychk){ if(busychk){
cntr = Tms; cntr = Tms;
while(I2C1->ISR & I2C_ISR_BUSY){ while(I2C1->ISR & I2C_ISR_BUSY){
IWDG->KR = IWDG_REFRESH; IWDG->KR = IWDG_REFRESH;
if(Tms - cntr > I2C_TIMEOUT){ if(Tms - cntr > I2C_TIMEOUT){
USND("Line busy\n"); USND("i2c_chk: Line busy\n");
return 0; // check busy return 0; // check busy
}} }}
} }/*
cntr = Tms; cntr = Tms;
while(I2C1->CR2 & I2C_CR2_START){ while(I2C1->CR2 & I2C_CR2_START){
IWDG->KR = IWDG_REFRESH; IWDG->KR = IWDG_REFRESH;
if(Tms - cntr > I2C_TIMEOUT){ if(Tms - cntr > I2C_TIMEOUT){
USND("No start\n"); USND("i2c_chk: No start\n");
return 0; // check start return 0; // check start
}} }}*/
return 1; return 1;
} }
// start writing // start writing
static uint8_t i2c_startw(uint8_t addr, uint8_t nbytes, uint8_t stop){ static uint8_t i2c_startw(uint8_t addr, uint8_t nbytes, uint8_t stop){
if(!i2c_start(1)) return 0; if(!i2c_chk(1)) return 0;
I2C1->CR2 = nbytes << 16 | addr; I2C1->CR2 = nbytes << 16 | addr;
if(stop) I2C1->CR2 |= I2C_CR2_AUTOEND; // autoend if(stop){
I2C1->CR2 |= I2C_CR2_AUTOEND; // autoend
}else{
//I2C1->CR2 &= ~I2C_CR2_AUTOEND;
//I2C1->CR2 |= I2C_CR2_RELOAD;
}
// now start transfer // now start transfer
I2C1->CR2 |= I2C_CR2_START; I2C1->CR2 |= I2C_CR2_START;
return 1; return 1;
@ -143,21 +155,31 @@ static uint8_t write_i2cs(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t s
IWDG->KR = IWDG_REFRESH; IWDG->KR = IWDG_REFRESH;
if(I2C1->ISR & I2C_ISR_NACKF){ if(I2C1->ISR & I2C_ISR_NACKF){
I2C1->ICR |= I2C_ICR_NACKCF; I2C1->ICR |= I2C_ICR_NACKCF;
//USND("NAK\n"); USND("write_i2cs: NAK\n");
return 0; return 0;
} }
if(Tms - cntr > I2C_TIMEOUT){ if(Tms - cntr > I2C_TIMEOUT){
//USND("Timeout\n"); USND("write_i2cs: Timeout\n");
return 0; return 0;
} }
} }
I2C1->TXDR = data[i]; // send data I2C1->TXDR = data[i]; // send data
USND("write_i2cs: "); USND(uhex2str(data[i])); newline();
} }
cntr = Tms; cntr = Tms;
// wait for data gone if(stop){
while(I2C1->ISR & I2C_ISR_BUSY){ while(I2C1->ISR & I2C_ISR_BUSY){
IWDG->KR = IWDG_REFRESH; IWDG->KR = IWDG_REFRESH;
if(Tms - cntr > I2C_TIMEOUT){break;} if(Tms - cntr > I2C_TIMEOUT){USND("write_i2cs: Busy timeout\n"); break;}
}
}else{ // repeated start
while(!(I2C1->ISR & I2C_ISR_TC)){
IWDG->KR = IWDG_REFRESH;
if(Tms - cntr > I2C_TIMEOUT){
USND("write_i2cs: TC timeout\n");
return 0;
}
}
} }
return 1; return 1;
} }
@ -181,10 +203,11 @@ uint8_t write_i2c_dma(uint8_t addr, uint8_t *data, uint8_t nbytes){
// start reading // start reading
static uint8_t i2c_startr(uint8_t addr, uint8_t nbytes, uint8_t busychk){ static uint8_t i2c_startr(uint8_t addr, uint8_t nbytes, uint8_t busychk){
if(!i2c_start(busychk)) return 0; if(!i2c_chk(busychk)) return 0;
// read N bytes // read N bytes
I2C1->CR2 = (nbytes<<16) | addr | 1 | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN; I2C1->CR2 = (nbytes<<16) | addr /*| I2C_CR2_AUTOEND*/ | I2C_CR2_RD_WRN;
I2C1->CR2 |= I2C_CR2_START; I2C1->CR2 |= I2C_CR2_START;
I2C1->CR2 |= I2C_CR2_AUTOEND;
return 1; return 1;
} }
@ -203,18 +226,27 @@ static uint8_t read_i2cb(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t bu
IWDG->KR = IWDG_REFRESH; IWDG->KR = IWDG_REFRESH;
if(I2C1->ISR & I2C_ISR_NACKF){ if(I2C1->ISR & I2C_ISR_NACKF){
I2C1->ICR |= I2C_ICR_NACKCF; I2C1->ICR |= I2C_ICR_NACKCF;
//USND("NAK\n"); USND("read_i2_nostart: NAK\n");
return 0; return 0;
} }
if(Tms - cntr > I2C_TIMEOUT){ if(Tms - cntr > I2C_TIMEOUT){
//USND("Timeout\n"); USND("read_i2_nostart: Timeout\n");
return 0; return 0;
} }
} }
*data++ = I2C1->RXDR; *data++ = I2C1->RXDR;
}/*
cntr = Tms;
while(!(I2C1->ISR & I2C_ISR_TC)){
IWDG->KR = IWDG_REFRESH;
if(Tms - cntr > I2C_TIMEOUT){
USND("read_i2cs: TC timeout\n");
return 0;
}
} }
I2C1->CR2 = I2C_CR2_STOP;*/
return 1; return 1;
} }
uint8_t read_i2c(uint8_t addr, uint8_t *data, uint8_t nbytes){ uint8_t read_i2c(uint8_t addr, uint8_t *data, uint8_t nbytes){
if(isI2Cbusy()) return 0; if(isI2Cbusy()) return 0;
@ -243,6 +275,7 @@ uint8_t read_i2c_reg(uint8_t addr, uint8_t reg, uint8_t *data, uint8_t nbytes){
// read 16bit register reg // read 16bit register reg
uint8_t read_i2c_reg16(uint8_t addr, uint16_t reg16, uint8_t *data, uint8_t nbytes){ uint8_t read_i2c_reg16(uint8_t addr, uint16_t reg16, uint8_t *data, uint8_t nbytes){
if(isI2Cbusy()) return 0; if(isI2Cbusy()) return 0;
reg16 = __REV16(reg16);
if(!write_i2cs(addr, (uint8_t*)&reg16, 2, 0)) return 0; if(!write_i2cs(addr, (uint8_t*)&reg16, 2, 0)) return 0;
return read_i2cb(addr, data, nbytes, 0); return read_i2cb(addr, data, nbytes, 0);
} }

BIN
F3:F303/I2C_scan/i2cscan.bin
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105
F3:F303/I2C_scan/i2cscan.creator.user
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174
F3:F303/I2C_scan/i2cscan.creator.user.cf63021 Normal file
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@ -0,0 +1,174 @@
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14
F3:F303/I2C_scan/proto.c
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@ -46,19 +46,19 @@ const char *helpstring =
static uint8_t i2cinited = 0; static uint8_t i2cinited = 0;
TRUE_INLINE const char *setupI2C(const char *buf){ TRUE_INLINE const char *setupI2C(const char *buf){
buf = omit_spaces(buf); buf = omit_spaces(buf);
if(*buf < '0' || *buf > '2') return "Wrong speed"; if(*buf < '0' || *buf > '2') return "Wrong speed\n";
i2c_setup(*buf - '0'); i2c_setup(*buf - '0');
i2cinited = 1; i2cinited = 1;
return "OK"; return "OK\n";
} }
static uint8_t I2Caddress = 0; static uint8_t I2Caddress = 0;
TRUE_INLINE const char *saI2C(const char *buf){ TRUE_INLINE const char *saI2C(const char *buf){
uint32_t addr; uint32_t addr;
if(!getnum(buf, &addr) || addr > 0x7f) return "Wrong address"; if(!getnum(buf, &addr) || addr > 0x7f) return "Wrong address\n";
I2Caddress = (uint8_t) addr << 1; I2Caddress = (uint8_t) addr << 1;
USND("I2Caddr="); USND(uhex2str(addr)); newline(); USND("I2Caddr="); USND(uhex2str(addr)); newline();
return "OK"; return "OK\n";
} }
static void rdI2C(const char *buf, int is16){ static void rdI2C(const char *buf, int is16){
uint32_t N = 0; uint32_t N = 0;
@ -111,7 +111,7 @@ static void rdI2C(const char *buf, int is16){
} }
} }
} }
if(N == 0){ USND("OK"); return; } if(N == 0){ USND("OK\n"); return; }
if(!noreg){USND("Register "); USND(uhex2str(reg)); USND(":\n");} if(!noreg){USND("Register "); USND(uhex2str(reg)); USND(":\n");}
hexdump(USB_sendstr, locBuffer, N); hexdump(USB_sendstr, locBuffer, N);
} }
@ -132,8 +132,8 @@ static const char *wrI2C(const char *buf, int isdma){
uint16_t N = readNnumbers(buf); uint16_t N = readNnumbers(buf);
int result = isdma ? write_i2c_dma(I2Caddress, locBuffer, N) : int result = isdma ? write_i2c_dma(I2Caddress, locBuffer, N) :
write_i2c(I2Caddress, locBuffer, N); write_i2c(I2Caddress, locBuffer, N);
if(!result) return "Error writing I2C"; if(!result) return "Error writing I2C\n";
return "OK"; return "OK\n";
} }
const char *parse_cmd(const char *buf){ const char *parse_cmd(const char *buf){

4
F3:F303/I2C_scan/version.inc
View File

@ -1,2 +1,2 @@
#define BUILD_NUMBER "17" #define BUILD_NUMBER "64"
#define BUILD_DATE "2023-01-22" #define BUILD_DATE "2025-09-13"

2
F3:F303/inc/Fx/stm32f3.h
View File

@ -123,6 +123,8 @@ TRUE_INLINE int StartHSE(){ // system bus 72MHz from PLL
WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY)); WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
// Select PLL as system clock source // Select PLL as system clock source
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
// select system clock as I2C source
RCC->CFGR3 |= RCC_CFGR3_I2C1SW_SYSCLK | RCC_CFGR3_I2C1SW_SYSCLK;
// Wait till PLL is used as system clock source // Wait till PLL is used as system clock source
WAITWHILE((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL); WAITWHILE((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
SysFreq = 72000000; SysFreq = 72000000;