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https://github.com/eddyem/stm32samples.git
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Add canUART for STM32F103
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140
F1:F103/canUART/usart.c
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140
F1:F103/canUART/usart.c
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/*
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* This file is part of the canuart project.
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* Copyright 2022 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "stm32f1.h"
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#include "usart.h"
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extern volatile uint32_t Tms;
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static volatile int idatalen[2] = {0,0}; // received data line length (including '\n')
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static volatile int odatalen[2] = {0,0};
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volatile int usart_txrdy = 1; // transmission done
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static volatile int usart_linerdy = 0 // received data ready
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,dlen = 0 // length of data (including '\n') in current buffer
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,usart_bufovr = 0 // input buffer overfull
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;
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int rbufno = 0, tbufno = 0; // current rbuf/tbuf numbers
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static char rbuf[2][UARTBUFSZI], tbuf[2][UARTBUFSZO]; // receive & transmit buffers
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static char *recvdata = NULL;
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/**
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* return length of received data (without trailing zero)
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*/
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int usart_getline(char **line){
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if(usart_bufovr){
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usart_bufovr = 0;
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usart_linerdy = 0;
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return -1;
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}
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if(!usart_linerdy) return 0;
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*line = recvdata;
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usart_linerdy = 0;
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int x = dlen;
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dlen = 0;
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return x;
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}
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// transmit current tbuf and swap buffers
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void usart_transmit(){
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register int l = odatalen[tbufno];
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if(!l) return;
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uint32_t tmout = 16000000;
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while(!usart_txrdy){if(--tmout == 0) return;}; // wait for previos buffer transmission
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usart_txrdy = 0;
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odatalen[tbufno] = 0;
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DMA1_Channel4->CCR &= ~DMA_CCR_EN;
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DMA1_Channel4->CMAR = (uint32_t) tbuf[tbufno]; // mem
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DMA1_Channel4->CNDTR = l;
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DMA1_Channel4->CCR |= DMA_CCR_EN;
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tbufno = !tbufno;
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}
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void usart_putchar(const char ch){
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if(odatalen[tbufno] == UARTBUFSZO) usart_transmit();
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tbuf[tbufno][odatalen[tbufno]++] = ch;
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}
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void usart_send(const char *str){
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while(*str){
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if(odatalen[tbufno] == UARTBUFSZO) usart_transmit();
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tbuf[tbufno][odatalen[tbufno]++] = *str++;
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}
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}
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/*
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* USART speed: baudrate = Fck/(USARTDIV)
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* USARTDIV stored in USART->BRR
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*
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* for 72MHz USARTDIV=72000/f(kboud); so for 115200 USARTDIV=72000/115.2=625 -> BRR=0x271
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* 9600: BRR = 7500 (0x1D4C)
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*/
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void usart_setup(){
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uint32_t tmout = 16000000;
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// PA9 - Tx, PA10 - Rx
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_USART1EN | RCC_APB2ENR_AFIOEN;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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GPIOA->CRH = CRH(9, CNF_AFPP|MODE_NORMAL) | CRH(10, CNF_FLINPUT|MODE_INPUT);
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// USART1 Tx DMA - Channel4 (Rx - channel 5)
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DMA1_Channel4->CPAR = (uint32_t) &USART1->DR; // periph
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DMA1_Channel4->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq
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// Tx CNDTR set @ each transmission due to data size
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NVIC_SetPriority(DMA1_Channel4_IRQn, 3);
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NVIC_EnableIRQ(DMA1_Channel4_IRQn);
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NVIC_SetPriority(USART1_IRQn, 0);
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// setup usart1
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USART1->BRR = 72000000 / 115200;
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USART1->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; // 1start,8data,nstop; enable Rx,Tx,USART
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while(!(USART1->SR & USART_SR_TC)){if(--tmout == 0) break;} // polling idle frame Transmission
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USART1->SR = 0; // clear flags
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USART1->CR1 |= USART_CR1_RXNEIE; // allow Rx IRQ
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USART1->CR3 = USART_CR3_DMAT; // enable DMA Tx
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NVIC_EnableIRQ(USART1_IRQn);
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}
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void usart1_isr(){
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if(USART1->SR & USART_SR_RXNE){ // RX not emty - receive next char
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uint8_t rb = USART1->DR;
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if(idatalen[rbufno] < UARTBUFSZI){ // put next char into buf
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rbuf[rbufno][idatalen[rbufno]++] = rb;
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if(rb == '\n'){ // got newline - line ready
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usart_linerdy = 1;
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dlen = idatalen[rbufno];
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recvdata = rbuf[rbufno];
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// prepare other buffer
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rbufno = !rbufno;
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idatalen[rbufno] = 0;
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}
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}else{ // buffer overrun
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usart_bufovr = 1;
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idatalen[rbufno] = 0;
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}
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}
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}
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void dma1_channel4_isr(){
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if(DMA1->ISR & DMA_ISR_TCIF4){ // Tx
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DMA1->IFCR = DMA_IFCR_CTCIF4; // clear TC flag
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usart_txrdy = 1;
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}
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}
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