mirror of
https://github.com/eddyem/stm32samples.git
synced 2026-02-28 03:44:30 +03:00
add blink for G070 (NOT TESTED!)
This commit is contained in:
Edward Emelianov
57
G0:G070/inc/Fx/common_macros.h
Normal file
57
G0:G070/inc/Fx/common_macros.h
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@@ -0,0 +1,57 @@
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/*
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* common_macros.h - common usable things
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*
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* Copyright 2018 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
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||||
*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#pragma once
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#ifndef __COMMON_MACROS_H__
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#define __COMMON_MACROS_H__
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#include <stdint.h>
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#ifndef TRUE
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#define TRUE 1
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#endif
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#ifndef FALSE
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#define FALSE 0
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#endif
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#ifndef TRUE_INLINE
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#define TRUE_INLINE __attribute__((always_inline)) static inline
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#endif
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#ifndef NULL
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#define NULL (0)
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#endif
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// some good things from CMSIS
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#define nop() __NOP()
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#define pin_toggle(gpioport, gpios) do{ \
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register uint32_t __port = gpioport->ODR; \
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gpioport->BSRR = ((__port & gpios) << 16) | (~__port & gpios);}while(0)
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#define pin_set(gpioport, gpios) do{gpioport->BSRR = gpios;}while(0)
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#define pin_clear(gpioport, gpios) do{gpioport->BRR = gpios;}while(0)
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#define pin_read(gpioport, gpios) (gpioport->IDR & (gpios) ? 1 : 0)
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#define pin_write(gpioport, gpios) do{gpioport->ODR = gpios;}while(0)
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#endif // __COMMON_MACROS_H__
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12
G0:G070/inc/Fx/flash_size_reg.h
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12
G0:G070/inc/Fx/flash_size_reg.h
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@@ -0,0 +1,12 @@
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#define STM32F0_FlashAddr 0x1FFFF7CC // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F0
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#define STM32F1_FlashAddr 0x1FFFF7E0 // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F1
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#define STM32F2_FlashAddr 0x1FFF7A22 // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F2
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#define STM32F3_FlashAddr 0x1FFFF7CC // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F3
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#define STM32F4_FlashAddr 0x1FFF7A22 // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F4
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#define STM32F7_FlashAddr 0x1FF0F442 // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÆÌÜÛ-ÐÁÍÑÔÉ STM32F7
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#define STM32L0_FlashAddr 0x1FF8007C // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32L0
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#define STM32L1_FlashAddr 0x1FF8004C // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32L1
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#define STM32L4_FlashAddr 0x1FFF75E0 // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÅÍËÏÓÔÉ ÆÌÜÛ-ÐÁÍÑÔÉ STM32L4
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#define STM32H7_FlashAddr 0x1FF0F442 // âÁÚÏ×ÙÊ ÁÄÒÅÓ ÆÌÜÛ-ÐÁÍÑÔÉ STM32H7
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blocksize=2k if memory>=128k
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223
G0:G070/inc/Fx/stm32g0.h
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223
G0:G070/inc/Fx/stm32g0.h
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@@ -0,0 +1,223 @@
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/*
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* stm32f0.h
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*
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* Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#pragma once
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#ifndef __STM32F0_H__
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#define __STM32F0_H__
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#include "vector.h"
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#include "stm32g0xx.h"
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#include "common_macros.h"
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/************************* RCC *************************/
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// reset clocking registers
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TRUE_INLINE void sysreset(void){ // do nothing
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}
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/*
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* R=2..8, Q=2..8, P=2..32; N=8..86, M=1..8
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* fvco = 64..344MHz (after /M should be 2.66..16 -> for 8MHz HSE M=1..3!!!)
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* For 8MHZ:
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* fvco = (8/M)*N -> N(144)=18, M(144)=1
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* fpllp = fvco/P (<=122MHz) -> P(72)=2
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* fpllq = fvco/Q (<=128MHz) -> Q(48)=3
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* fpllr = fvco/R (<=64MHz) -> R(48)=3
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* AHB prescaler (72MHz) = 144/72 = 2
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* APB prescaler (72MHz) = 72/72 = 1
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*/
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#define WAITWHILE(x) do{StartUpCounter = 0; while((x) && (++StartUpCounter < 0xffffff)){nop();}}while(0)
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TRUE_INLINE void StartHSE(){
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uint32_t StartUpCounter;
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RCC->CR &= ~RCC_CR_PLLON; // disable PLL
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WAITWHILE(RCC->CR & RCC_CR_PLLRDY); // wait while PLL on
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RCC->CR |= RCC_CR_HSEON;
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WAITWHILE(!(RCC->CIFR & RCC_CIFR_HSERDYF)); // wait while HSE isn't on
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RCC->CICR = RCC_CICR_HSERDYC; // clear rdy flag
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RCC->CR |= RCC_CR_PLLON;
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RCC->PLLCFGR = (3<<29) | (3<<25) | (2<<17) | (18<<8) | (1<<4) | RCC_PLLCFGR_PLLSRC_HSE;
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RCC->CFGR = RCC_CFGR_HPRE_3 | RCC_CFGR_SW_1; // set sysclk switch to pll, set prescalers
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WAITWHILE((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1); // wait until status changed
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}
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/************************* GPIO *************************/
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/******************* Bit definition for GPIO_MODER register *****************/
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// _AI - analog inpt, _O - general output, _AF - alternate function
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#define GPIO_MODER_MODER0_AI ((uint32_t)0x00000003)
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#define GPIO_MODER_MODER0_O ((uint32_t)0x00000001)
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#define GPIO_MODER_MODER0_AF ((uint32_t)0x00000002)
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#define GPIO_MODER_MODER1_AI ((uint32_t)0x0000000C)
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#define GPIO_MODER_MODER1_O ((uint32_t)0x00000004)
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#define GPIO_MODER_MODER1_AF ((uint32_t)0x00000008)
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#define GPIO_MODER_MODER2_AI ((uint32_t)0x00000030)
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#define GPIO_MODER_MODER2_O ((uint32_t)0x00000010)
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#define GPIO_MODER_MODER2_AF ((uint32_t)0x00000020)
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#define GPIO_MODER_MODER3_AI ((uint32_t)0x000000C0)
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#define GPIO_MODER_MODER3_O ((uint32_t)0x00000040)
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#define GPIO_MODER_MODER3_AF ((uint32_t)0x00000080)
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#define GPIO_MODER_MODER4_AI ((uint32_t)0x00000300)
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#define GPIO_MODER_MODER4_O ((uint32_t)0x00000100)
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#define GPIO_MODER_MODER4_AF ((uint32_t)0x00000200)
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#define GPIO_MODER_MODER5_AI ((uint32_t)0x00000C00)
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#define GPIO_MODER_MODER5_O ((uint32_t)0x00000400)
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#define GPIO_MODER_MODER5_AF ((uint32_t)0x00000800)
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#define GPIO_MODER_MODER6_AI ((uint32_t)0x00003000)
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#define GPIO_MODER_MODER6_O ((uint32_t)0x00001000)
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#define GPIO_MODER_MODER6_AF ((uint32_t)0x00002000)
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#define GPIO_MODER_MODER7_AI ((uint32_t)0x0000C000)
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#define GPIO_MODER_MODER7_O ((uint32_t)0x00004000)
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#define GPIO_MODER_MODER7_AF ((uint32_t)0x00008000)
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#define GPIO_MODER_MODER8_AI ((uint32_t)0x00030000)
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#define GPIO_MODER_MODER8_O ((uint32_t)0x00010000)
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#define GPIO_MODER_MODER8_AF ((uint32_t)0x00020000)
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#define GPIO_MODER_MODER9_AI ((uint32_t)0x000C0000)
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#define GPIO_MODER_MODER9_O ((uint32_t)0x00040000)
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#define GPIO_MODER_MODER9_AF ((uint32_t)0x00080000)
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#define GPIO_MODER_MODER10_AI ((uint32_t)0x00300000)
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#define GPIO_MODER_MODER10_O ((uint32_t)0x00100000)
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#define GPIO_MODER_MODER10_AF ((uint32_t)0x00200000)
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#define GPIO_MODER_MODER11_AI ((uint32_t)0x00C00000)
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#define GPIO_MODER_MODER11_O ((uint32_t)0x00400000)
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#define GPIO_MODER_MODER11_AF ((uint32_t)0x00800000)
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#define GPIO_MODER_MODER12_AI ((uint32_t)0x03000000)
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#define GPIO_MODER_MODER12_O ((uint32_t)0x01000000)
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#define GPIO_MODER_MODER12_AF ((uint32_t)0x02000000)
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#define GPIO_MODER_MODER13_AI ((uint32_t)0x0C000000)
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#define GPIO_MODER_MODER13_O ((uint32_t)0x04000000)
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#define GPIO_MODER_MODER13_AF ((uint32_t)0x08000000)
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#define GPIO_MODER_MODER14_AI ((uint32_t)0x30000000)
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#define GPIO_MODER_MODER14_O ((uint32_t)0x10000000)
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#define GPIO_MODER_MODER14_AF ((uint32_t)0x20000000)
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#define GPIO_MODER_MODER15_AI ((uint32_t)0xC0000000)
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#define GPIO_MODER_MODER15_O ((uint32_t)0x40000000)
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#define GPIO_MODER_MODER15_AF ((uint32_t)0x80000000)
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/******************* Bit definition for GPIO_PUPDR register *****************/
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// no/pullup/pulldown/reserved
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// for n in $(seq 0 15); do echo "#define GPIO_PUPDR${n}_PU ((uint32_t)(1<<$((n*2))))";
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// echo "#define GPIO_PUPDR${n}_PD ((uint32_t)(1<<$((n*2+1))))"; done
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// alt+select column -> delete
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#define GPIO_PUPDR0_PU ((uint32_t)(1<<0))
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#define GPIO_PUPDR0_PD ((uint32_t)(1<<1))
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#define GPIO_PUPDR1_PU ((uint32_t)(1<<2))
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#define GPIO_PUPDR1_PD ((uint32_t)(1<<3))
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#define GPIO_PUPDR2_PU ((uint32_t)(1<<4))
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#define GPIO_PUPDR2_PD ((uint32_t)(1<<5))
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#define GPIO_PUPDR3_PU ((uint32_t)(1<<6))
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#define GPIO_PUPDR3_PD ((uint32_t)(1<<7))
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#define GPIO_PUPDR4_PU ((uint32_t)(1<<8))
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#define GPIO_PUPDR4_PD ((uint32_t)(1<<9))
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#define GPIO_PUPDR5_PU ((uint32_t)(1<<10))
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#define GPIO_PUPDR5_PD ((uint32_t)(1<<11))
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#define GPIO_PUPDR6_PU ((uint32_t)(1<<12))
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#define GPIO_PUPDR6_PD ((uint32_t)(1<<13))
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#define GPIO_PUPDR7_PU ((uint32_t)(1<<14))
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#define GPIO_PUPDR7_PD ((uint32_t)(1<<15))
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#define GPIO_PUPDR8_PU ((uint32_t)(1<<16))
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#define GPIO_PUPDR8_PD ((uint32_t)(1<<17))
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#define GPIO_PUPDR9_PU ((uint32_t)(1<<18))
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#define GPIO_PUPDR9_PD ((uint32_t)(1<<19))
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#define GPIO_PUPDR10_PU ((uint32_t)(1<<20))
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#define GPIO_PUPDR10_PD ((uint32_t)(1<<21))
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#define GPIO_PUPDR11_PU ((uint32_t)(1<<22))
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#define GPIO_PUPDR11_PD ((uint32_t)(1<<23))
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#define GPIO_PUPDR12_PU ((uint32_t)(1<<24))
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#define GPIO_PUPDR12_PD ((uint32_t)(1<<25))
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#define GPIO_PUPDR13_PU ((uint32_t)(1<<26))
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#define GPIO_PUPDR13_PD ((uint32_t)(1<<27))
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#define GPIO_PUPDR14_PU ((uint32_t)(1<<28))
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#define GPIO_PUPDR14_PD ((uint32_t)(1<<29))
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#define GPIO_PUPDR15_PU ((uint32_t)(1<<30))
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#define GPIO_PUPDR15_PD ((uint32_t)(1<<31))
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// OSPEEDR
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// for n in $(seq 0 15); do echo "#define GPIO_OSPEEDR${n}_MED ((uint32_t)(1<<$((n*2))))";
|
||||
// echo "#define GPIO_OSPEEDR${n}_HIGH ((uint32_t)(3<<$((2*n))))"; done
|
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#define GPIO_OSPEEDR0_MED ((uint32_t)(1<<0))
|
||||
#define GPIO_OSPEEDR0_HIGH ((uint32_t)(3<<0))
|
||||
#define GPIO_OSPEEDR1_MED ((uint32_t)(1<<2))
|
||||
#define GPIO_OSPEEDR1_HIGH ((uint32_t)(3<<2))
|
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#define GPIO_OSPEEDR2_MED ((uint32_t)(1<<4))
|
||||
#define GPIO_OSPEEDR2_HIGH ((uint32_t)(3<<4))
|
||||
#define GPIO_OSPEEDR3_MED ((uint32_t)(1<<6))
|
||||
#define GPIO_OSPEEDR3_HIGH ((uint32_t)(3<<6))
|
||||
#define GPIO_OSPEEDR4_MED ((uint32_t)(1<<8))
|
||||
#define GPIO_OSPEEDR4_HIGH ((uint32_t)(3<<8))
|
||||
#define GPIO_OSPEEDR5_MED ((uint32_t)(1<<10))
|
||||
#define GPIO_OSPEEDR5_HIGH ((uint32_t)(3<<10))
|
||||
#define GPIO_OSPEEDR6_MED ((uint32_t)(1<<12))
|
||||
#define GPIO_OSPEEDR6_HIGH ((uint32_t)(3<<12))
|
||||
#define GPIO_OSPEEDR7_MED ((uint32_t)(1<<14))
|
||||
#define GPIO_OSPEEDR7_HIGH ((uint32_t)(3<<14))
|
||||
#define GPIO_OSPEEDR8_MED ((uint32_t)(1<<16))
|
||||
#define GPIO_OSPEEDR8_HIGH ((uint32_t)(3<<16))
|
||||
#define GPIO_OSPEEDR9_MED ((uint32_t)(1<<18))
|
||||
#define GPIO_OSPEEDR9_HIGH ((uint32_t)(3<<18))
|
||||
#define GPIO_OSPEEDR10_MED ((uint32_t)(1<<20))
|
||||
#define GPIO_OSPEEDR10_HIGH ((uint32_t)(3<<20))
|
||||
#define GPIO_OSPEEDR11_MED ((uint32_t)(1<<22))
|
||||
#define GPIO_OSPEEDR11_HIGH ((uint32_t)(3<<22))
|
||||
#define GPIO_OSPEEDR12_MED ((uint32_t)(1<<24))
|
||||
#define GPIO_OSPEEDR12_HIGH ((uint32_t)(3<<24))
|
||||
#define GPIO_OSPEEDR13_MED ((uint32_t)(1<<26))
|
||||
#define GPIO_OSPEEDR13_HIGH ((uint32_t)(3<<26))
|
||||
#define GPIO_OSPEEDR14_MED ((uint32_t)(1<<28))
|
||||
#define GPIO_OSPEEDR14_HIGH ((uint32_t)(3<<28))
|
||||
#define GPIO_OSPEEDR15_MED ((uint32_t)(1<<30))
|
||||
#define GPIO_OSPEEDR15_HIGH ((uint32_t)(3<<30))
|
||||
|
||||
|
||||
|
||||
/****************** FLASH Keys **********************************************/
|
||||
#define RDP_Key ((uint16_t)0x00A5)
|
||||
#define FLASH_KEY1 ((uint32_t)0x45670123)
|
||||
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
|
||||
#define FLASH_SIZE_REG ((uint32_t)0x1FFFF7CC)
|
||||
|
||||
/************************* ADC *************************/
|
||||
/* inner termometer calibration values
|
||||
* Temp = (V30 - Vsense)/Avg_Slope + 30
|
||||
* Avg_Slope = (V30 - V110) / (110 - 30)
|
||||
*/
|
||||
#define TEMP110_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7C2))
|
||||
#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
|
||||
// VDDA_Actual = 3.3V * VREFINT_CAL / average vref value
|
||||
#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7BA))
|
||||
#define VDD_CALIB ((uint16_t) (330))
|
||||
#define VDD_APPLI ((uint16_t) (300))
|
||||
|
||||
/************************* USART *************************/
|
||||
|
||||
#define USART_CR2_ADD_SHIFT 24
|
||||
// set address/character match value
|
||||
#define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)
|
||||
|
||||
/************************* IWDG *************************/
|
||||
#define IWDG_REFRESH (uint32_t)(0x0000AAAA)
|
||||
#define IWDG_WRITE_ACCESS (uint32_t)(0x00005555)
|
||||
#define IWDG_START (uint32_t)(0x0000CCCC)
|
||||
|
||||
|
||||
//#define do{}while(0)
|
||||
|
||||
|
||||
|
||||
|
||||
#endif // __STM32F0_H__
|
||||
7438
G0:G070/inc/Fx/stm32g030xx.h
Normal file
7438
G0:G070/inc/Fx/stm32g030xx.h
Normal file
File diff suppressed because it is too large
Load Diff
7979
G0:G070/inc/Fx/stm32g031xx.h
Normal file
7979
G0:G070/inc/Fx/stm32g031xx.h
Normal file
File diff suppressed because it is too large
Load Diff
8287
G0:G070/inc/Fx/stm32g041xx.h
Normal file
8287
G0:G070/inc/Fx/stm32g041xx.h
Normal file
File diff suppressed because it is too large
Load Diff
7562
G0:G070/inc/Fx/stm32g050xx.h
Normal file
7562
G0:G070/inc/Fx/stm32g050xx.h
Normal file
File diff suppressed because it is too large
Load Diff
8514
G0:G070/inc/Fx/stm32g051xx.h
Normal file
8514
G0:G070/inc/Fx/stm32g051xx.h
Normal file
File diff suppressed because it is too large
Load Diff
8822
G0:G070/inc/Fx/stm32g061xx.h
Normal file
8822
G0:G070/inc/Fx/stm32g061xx.h
Normal file
File diff suppressed because it is too large
Load Diff
7724
G0:G070/inc/Fx/stm32g070xx.h
Normal file
7724
G0:G070/inc/Fx/stm32g070xx.h
Normal file
File diff suppressed because it is too large
Load Diff
9248
G0:G070/inc/Fx/stm32g071xx.h
Normal file
9248
G0:G070/inc/Fx/stm32g071xx.h
Normal file
File diff suppressed because it is too large
Load Diff
9556
G0:G070/inc/Fx/stm32g081xx.h
Normal file
9556
G0:G070/inc/Fx/stm32g081xx.h
Normal file
File diff suppressed because it is too large
Load Diff
9340
G0:G070/inc/Fx/stm32g0b0xx.h
Normal file
9340
G0:G070/inc/Fx/stm32g0b0xx.h
Normal file
File diff suppressed because it is too large
Load Diff
11266
G0:G070/inc/Fx/stm32g0b1xx.h
Normal file
11266
G0:G070/inc/Fx/stm32g0b1xx.h
Normal file
File diff suppressed because it is too large
Load Diff
11574
G0:G070/inc/Fx/stm32g0c1xx.h
Normal file
11574
G0:G070/inc/Fx/stm32g0c1xx.h
Normal file
File diff suppressed because it is too large
Load Diff
244
G0:G070/inc/Fx/stm32g0xx.h
Normal file
244
G0:G070/inc/Fx/stm32g0xx.h
Normal file
@@ -0,0 +1,244 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32g0xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32G0xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32G0xx device used in the target application
|
||||
* - To use or not the peripherals drivers in application code(i.e.
|
||||
* code will be based on direct access to peripherals registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2018-2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32g0xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef STM32G0xx_H
|
||||
#define STM32G0xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32G0)
|
||||
#define STM32G0
|
||||
#endif /* STM32G0 */
|
||||
|
||||
/* Uncomment the line below according to the target STM32G0 device used in your
|
||||
application
|
||||
*/
|
||||
|
||||
#if !defined (STM32G071xx) && !defined (STM32G081xx) && !defined (STM32G070xx) \
|
||||
&& !defined (STM32G030xx) && !defined (STM32G031xx) && !defined (STM32G041xx) \
|
||||
&& !defined (STM32G0B0xx) && !defined (STM32G0B1xx) && !defined (STM32G0C1xx) \
|
||||
&& !defined (STM32G050xx) && !defined (STM32G051xx) && !defined (STM32G061xx)
|
||||
/* #define STM32G0B0xx */ /*!< STM32G0B0xx Devices */
|
||||
/* #define STM32G0B1xx */ /*!< STM32G0B1xx Devices */
|
||||
/* #define STM32G0C1xx */ /*!< STM32G0C1xx Devices */
|
||||
/* #define STM32G070xx */ /*!< STM32G070xx Devices */
|
||||
/* #define STM32G071xx */ /*!< STM32G071xx Devices */
|
||||
/* #define STM32G081xx */ /*!< STM32G081xx Devices */
|
||||
/* #define STM32G050xx */ /*!< STM32G050xx Devices */
|
||||
/* #define STM32G051xx */ /*!< STM32G051xx Devices */
|
||||
/* #define STM32G061xx */ /*!< STM32G061xx Devices */
|
||||
/* #define STM32G030xx */ /*!< STM32G030xx Devices */
|
||||
/* #define STM32G031xx */ /*!< STM32G031xx Devices */
|
||||
/* #define STM32G041xx */ /*!< STM32G041xx Devices */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
/*#define USE_HAL_DRIVER */
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number $VERSION$
|
||||
*/
|
||||
#define __STM32G0_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32G0_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
|
||||
#define __STM32G0_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
|
||||
#define __STM32G0_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32G0_CMSIS_VERSION ((__STM32G0_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32G0_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__STM32G0_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__STM32G0_CMSIS_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32G0B1xx)
|
||||
#include "stm32g0b1xx.h"
|
||||
#elif defined(STM32G0C1xx)
|
||||
#include "stm32g0c1xx.h"
|
||||
#elif defined(STM32G0B0xx)
|
||||
#include "stm32g0b0xx.h"
|
||||
#elif defined(STM32G071xx)
|
||||
#include "stm32g071xx.h"
|
||||
#elif defined(STM32G081xx)
|
||||
#include "stm32g081xx.h"
|
||||
#elif defined(STM32G070xx)
|
||||
#include "stm32g070xx.h"
|
||||
#elif defined(STM32G031xx)
|
||||
#include "stm32g031xx.h"
|
||||
#elif defined(STM32G041xx)
|
||||
#include "stm32g041xx.h"
|
||||
#elif defined(STM32G030xx)
|
||||
#include "stm32g030xx.h"
|
||||
#elif defined(STM32G051xx)
|
||||
#include "stm32g051xx.h"
|
||||
#elif defined(STM32G061xx)
|
||||
#include "stm32g061xx.h"
|
||||
#elif defined(STM32G050xx)
|
||||
#include "stm32g050xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32G0xx device used in your application (in stm32g0xx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SUCCESS = 0,
|
||||
ERROR = !SUCCESS
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macros
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
/* Use of interrupt control for register exclusive access */
|
||||
/* Atomic 32-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SET_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
SET_BIT((REG), (BIT)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
CLEAR_BIT((REG), (BIT)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \
|
||||
|
||||
/* Atomic 16-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
|
||||
/* Atomic 16-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
|
||||
/*#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (USE_HAL_DRIVER)
|
||||
#include "stm32g0xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* STM32G0xx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
77
G0:G070/inc/Fx/vector.h
Normal file
77
G0:G070/inc/Fx/vector.h
Normal file
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* vector.h
|
||||
*
|
||||
* Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
#pragma once
|
||||
#ifndef VECTOR_H
|
||||
#define VECTOR_H
|
||||
|
||||
#ifndef WEAK
|
||||
#define WEAK __attribute__((weak))
|
||||
#endif
|
||||
|
||||
void WEAK reset_handler(void);
|
||||
void WEAK nmi_handler(void);
|
||||
void WEAK hard_fault_handler(void);
|
||||
void WEAK sv_call_handler(void);
|
||||
void WEAK pend_sv_handler(void);
|
||||
void WEAK sys_tick_handler(void);
|
||||
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
void WEAK mem_manage_handler(void);
|
||||
void WEAK bus_fault_handler(void);
|
||||
void WEAK usage_fault_handler(void);
|
||||
void WEAK debug_monitor_handler(void);
|
||||
#endif
|
||||
|
||||
#if defined STM32G0
|
||||
void WEAK wwdg_isr(void);
|
||||
void WEAK rtc_isr(void);
|
||||
void WEAK flash_isr(void);
|
||||
void WEAK rcc_isr(void);
|
||||
void WEAK exti0_1_isr(void);
|
||||
void WEAK exti2_3_isr(void);
|
||||
void WEAK exti4_15_isr(void);
|
||||
void WEAK dma1_channel1_isr(void);
|
||||
void WEAK dma1_channel2_3_isr(void);
|
||||
void WEAK dmamux_isr(void);
|
||||
void WEAK adc_comp_isr(void);
|
||||
void WEAK tim1_brk_up_trg_com_isr(void);
|
||||
void WEAK tim1_cc_isr(void);
|
||||
void WEAK tim3_4_isr(void);
|
||||
void WEAK tim6_dac_isr(void);
|
||||
void WEAK tim7_isr(void);
|
||||
void WEAK tim14_isr(void);
|
||||
void WEAK tim15_isr(void);
|
||||
void WEAK tim16_isr(void);
|
||||
void WEAK tim17_isr(void);
|
||||
void WEAK i2c1_isr(void);
|
||||
void WEAK i2c2_3_isr(void);
|
||||
void WEAK spi1_isr(void);
|
||||
void WEAK spi2_3_isr(void);
|
||||
void WEAK usart1_isr(void);
|
||||
void WEAK usart2_isr(void);
|
||||
void WEAK usart3_6_isr(void);
|
||||
void WEAK cec_can_isr(void);
|
||||
void WEAK usb_isr(void);
|
||||
#else
|
||||
#error "Not supported platform"
|
||||
#endif
|
||||
|
||||
#endif // VECTOR_H
|
||||
Reference in New Issue
Block a user