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https://github.com/eddyem/stm32samples.git
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Add full ringbuffer @PL2303
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128
F0:F030,F042,F072/PL2303_ringbuffer/usbhw.c
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128
F0:F030,F042,F072/PL2303_ringbuffer/usbhw.c
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/*
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* This file is part of the MLX90640 project.
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* Copyright 2022 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "usb.h"
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#include "usbhw.h"
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#include "usb_lib.h"
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void USB_setup(){
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RCC->APB1ENR |= RCC_APB1ENR_CRSEN | RCC_APB1ENR_USBEN; // enable CRS (hsi48 sync) & USB
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RCC->CFGR3 &= ~RCC_CFGR3_USBSW; // reset USB
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RCC->CR2 |= RCC_CR2_HSI48ON; // turn ON HSI48
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uint32_t tmout = 16000000;
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while(!(RCC->CR2 & RCC_CR2_HSI48RDY)){if(--tmout == 0) break;}
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FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
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CRS->CFGR &= ~CRS_CFGR_SYNCSRC;
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CRS->CFGR |= CRS_CFGR_SYNCSRC_1; // USB SOF selected as sync source
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CRS->CR |= CRS_CR_AUTOTRIMEN; // enable auto trim
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CRS->CR |= CRS_CR_CEN; // enable freq counter & block CRS->CFGR as read-only
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RCC->CFGR |= RCC_CFGR_SW;
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// allow RESET and WKUPM interrupts
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USB->CNTR = USB_CNTR_RESETM | USB_CNTR_WKUPM;
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// clear flags
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USB->ISTR = 0;
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// and activate pullup
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USB->BCDR |= USB_BCDR_DPPU;
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NVIC_EnableIRQ(USB_IRQn);
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}
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static uint16_t lastaddr = LASTADDR_DEFAULT;
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/**
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* Endpoint initialisation
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* !!! when working with CAN bus change USB_BTABLE_SIZE to 768 !!!
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* @param number - EP num (0...7)
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* @param type - EP type (EP_TYPE_BULK, EP_TYPE_CONTROL, EP_TYPE_ISO, EP_TYPE_INTERRUPT)
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* @param txsz - transmission buffer size @ USB/CAN buffer
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* @param rxsz - reception buffer size @ USB/CAN buffer
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* @param uint16_t (*func)(ep_t *ep) - EP handler function
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* @return 0 if all OK
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*/
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int EP_Init(uint8_t number, uint8_t type, uint16_t txsz, uint16_t rxsz, void (*func)()){
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if(number >= STM32ENDPOINTS) return 4; // out of configured amount
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if(txsz > USB_BTABLE_SIZE || rxsz > USB_BTABLE_SIZE) return 1; // buffer too large
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if(lastaddr + txsz + rxsz >= USB_BTABLE_SIZE) return 2; // out of btable
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USB->EPnR[number] = (type << 9) | (number & USB_EPnR_EA);
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USB->EPnR[number] ^= USB_EPnR_STAT_RX | USB_EPnR_STAT_TX_1;
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if(rxsz & 1 || rxsz > USB_BTABLE_SIZE) return 3; // wrong rx buffer size
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uint16_t countrx = 0;
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if(rxsz < 64) countrx = rxsz / 2;
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else{
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if(rxsz & 0x1f) return 3; // should be multiple of 32
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countrx = 31 + rxsz / 32;
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}
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USB_BTABLE->EP[number].USB_ADDR_TX = lastaddr;
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endpoints[number].tx_buf = (uint16_t *)(USB_BTABLE_BASE + lastaddr);
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endpoints[number].txbufsz = txsz;
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lastaddr += txsz;
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USB_BTABLE->EP[number].USB_COUNT_TX = 0;
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USB_BTABLE->EP[number].USB_ADDR_RX = lastaddr;
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endpoints[number].rx_buf = (uint8_t *)(USB_BTABLE_BASE + lastaddr);
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lastaddr += rxsz;
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// buffer size: Table127 of RM
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USB_BTABLE->EP[number].USB_COUNT_RX = countrx << 10;
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endpoints[number].func = func;
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return 0;
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}
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// standard IRQ handler
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void usb_isr(){
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if (USB->ISTR & USB_ISTR_RESET){
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// Reinit registers
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USB->CNTR = USB_CNTR_RESETM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
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USB->ISTR = 0;
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// Endpoint 0 - CONTROL
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// ON USB LS size of EP0 may be 8 bytes, but on FS it should be 64 bytes!
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lastaddr = LASTADDR_DEFAULT; // roll back to beginning of buffer
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EP_Init(0, EP_TYPE_CONTROL, USB_EP0_BUFSZ, USB_EP0_BUFSZ, EP0_Handler);
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// clear address, leave only enable bit
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USB->DADDR = USB_DADDR_EF;
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// state is default - wait for enumeration
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USB_Dev.USB_Status = USB_STATE_DEFAULT;
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}
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if(USB->ISTR & USB_ISTR_CTR){
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// EP number
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uint8_t n = USB->ISTR & USB_ISTR_EPID;
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// copy status register
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uint16_t epstatus = USB->EPnR[n];
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// copy received bytes amount
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endpoints[n].rx_cnt = USB_BTABLE->EP[n].USB_COUNT_RX & 0x3FF; // low 10 bits is counter
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// check direction
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if(USB->ISTR & USB_ISTR_DIR){ // OUT interrupt - receive data, CTR_RX==1 (if CTR_TX == 1 - two pending transactions: receive following by transmit)
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if(n == 0){ // control endpoint
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if(epstatus & USB_EPnR_SETUP){ // setup packet -> copy data to conf_pack
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EP_Read(0, (uint8_t*)&setup_packet);
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// interrupt handler will be called later
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}else if(epstatus & USB_EPnR_CTR_RX){ // data packet -> push received data to ep0databuf
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EP_Read(0, (uint8_t*)&ep0databuf);
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}
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}
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}
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// call EP handler
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if(endpoints[n].func) endpoints[n].func(endpoints[n]);
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}
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if(USB->ISTR & USB_ISTR_SUSP){ // suspend -> still no connection, may sleep
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usbON = 0;
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USB->CNTR |= USB_CNTR_FSUSP | USB_CNTR_LPMODE;
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USB->ISTR = ~USB_ISTR_SUSP;
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}
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if(USB->ISTR & USB_ISTR_WKUP){ // wakeup
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USB->CNTR &= ~(USB_CNTR_FSUSP | USB_CNTR_LPMODE); // clear suspend flags
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USB->ISTR = ~USB_ISTR_WKUP;
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}
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}
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