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This commit is contained in:
Edward Emelianov
296
F1:F103/FX3U/can.c
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296
F1:F103/FX3U/can.c
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/*
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* This file is part of the fx3u project.
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* Copyright 2024 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "can.h"
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#include "hardware.h"
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#include "proto.h"
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#include "usart.h"
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// REMAPPED to PD0/PD1!!!
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#include <string.h> // memcpy
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// circular buffer for received messages
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static CAN_message messages[CAN_INMESSAGE_SIZE];
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static uint8_t first_free_idx = 0; // index of first empty cell
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static int8_t first_nonfree_idx = -1; // index of first data cell
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static uint16_t oldspeed = 100; // speed of last init
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static CAN_status can_status = CAN_STOP;
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static void can_process_fifo(uint8_t fifo_num);
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CAN_status CAN_get_status(){
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int st = can_status;
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can_status = CAN_OK;
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return st;
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}
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// push next message into buffer; return 1 if buffer overfull
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static int CAN_messagebuf_push(CAN_message *msg){
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//MSG("Try to push\n");
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#ifdef EBUG
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usart_send("push\n");
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#endif
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if(first_free_idx == first_nonfree_idx){
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#ifdef EBUG
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usart_send("INBUF OVERFULL\n");
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#endif
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return 1; // no free space
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}
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if(first_nonfree_idx < 0) first_nonfree_idx = 0; // first message in empty buffer
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memcpy(&messages[first_free_idx++], msg, sizeof(CAN_message));
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// need to roll?
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if(first_free_idx == CAN_INMESSAGE_SIZE) first_free_idx = 0;
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return 0;
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}
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// pop message from buffer
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CAN_message *CAN_messagebuf_pop(){
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if(first_nonfree_idx < 0) return NULL;
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CAN_message *msg = &messages[first_nonfree_idx++];
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if(first_nonfree_idx == CAN_INMESSAGE_SIZE) first_nonfree_idx = 0;
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if(first_nonfree_idx == first_free_idx){ // buffer is empty - refresh it
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first_nonfree_idx = -1;
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first_free_idx = 0;
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}
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return msg;
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}
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void CAN_reinit(uint16_t speed){
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CAN1->TSR |= CAN_TSR_ABRQ0 | CAN_TSR_ABRQ1 | CAN_TSR_ABRQ2;
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RCC->APB1RSTR |= RCC_APB1RSTR_CAN1RST;
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RCC->APB1RSTR &= ~RCC_APB1RSTR_CAN1RST;
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CAN_setup(speed);
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}
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/*
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Can filtering: FSCx=0 (CAN1->FS1R) -> 16-bit identifiers
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MASK: FBMx=0 (CAN1->FM1R), two filters (n in FR1 and n+1 in FR2)
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ID: CAN1->sFilterRegister[x].FRn[0..15]
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MASK: CAN1->sFilterRegister[x].FRn[16..31]
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FR bits: STID[10:0] RTR IDE EXID[17:15]
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LIST: FBMx=1, four filters (n&n+1 in FR1, n+2&n+3 in FR2)
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IDn: CAN1->sFilterRegister[x].FRn[0..15]
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IDn+1: CAN1->sFilterRegister[x].FRn[16..31]
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*/
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/*
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Can timing: main freq - APB (PLL=48MHz)
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segment = 1sync + TBS1 + TBS2, sample point is between TBS1 and TBS2,
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so if TBS1=4 and TBS2=3, sum=8, bit sampling freq is 48/8 = 6MHz
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-> to get 100kbps we need prescaler=60
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250kbps - 24
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500kbps - 12
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1MBps - 6
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*/
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// speed - in kbps
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void CAN_setup(uint16_t speed){
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if(speed == 0) speed = oldspeed;
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else if(speed < 50) speed = 50;
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else if(speed > 3000) speed = 3000;
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oldspeed = speed;
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uint32_t tmout = 16000000;
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// Configure GPIO: PD0 - CAN_Rx, PD1 - CAN_Tx
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AFIO->MAPR |= AFIO_MAPR_CAN_REMAP_REMAP3;
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GPIOD->CRL = (GPIOD->CRL & ~(CRL(0,0xf)|CRL(1,0xf))) |
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CRL(0, CNF_FLINPUT | MODE_INPUT) | CRL(1, CNF_AFPP | MODE_NORMAL);
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/* Enable the peripheral clock CAN */
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RCC->APB1ENR |= RCC_APB1ENR_CAN1EN;
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/* Configure CAN */
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/* (1) Enter CAN init mode to write the configuration */
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/* (2) Wait the init mode entering */
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/* (3) Exit sleep mode */
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/* (4) Normal mode, set timing to 100kb/s: TBS1 = 4, TBS2 = 3, prescaler = 60 */
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/* (5) Leave init mode */
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/* (6) Wait the init mode leaving */
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/* (7) Enter filter init mode, (16-bit + mask, bank 0 for FIFO 0) */
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/* (8) Acivate filter 0 for two IDs */
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/* (9) Identifier list mode */
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/* (10) Set the Id list */
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/* (12) Leave filter init */
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/* (13) Set error interrupts enable (& bus off) */
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CAN1->MCR |= CAN_MCR_INRQ; /* (1) */
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while((CAN1->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) /* (2) */
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if(--tmout == 0) break;
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CAN1->MCR &=~ CAN_MCR_SLEEP; /* (3) */
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CAN1->MCR |= CAN_MCR_ABOM; /* allow automatically bus-off */
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CAN1->BTR = 2 << 20 | 3 << 16 | (4500/speed - 1); //| CAN_BTR_SILM | CAN_BTR_LBKM; /* (4) */
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CAN1->MCR &= ~CAN_MCR_INRQ; /* (5) */
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tmout = 16000000;
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while((CAN1->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) /* (6) */
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if(--tmout == 0) break;
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// accept ALL
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CAN1->FMR = CAN_FMR_FINIT; /* (7) */
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CAN1->FA1R = CAN_FA1R_FACT0 | CAN_FA1R_FACT1; /* (8) */
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// set to 1 all needed bits of CAN1->FFA1R to switch given filters to FIFO1
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CAN1->sFilterRegister[0].FR1 = (1<<21)|(1<<5); // all odd IDs
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CAN1->FFA1R = 2; // filter 1 for FIFO1, filter 0 - for FIFO0
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CAN1->sFilterRegister[1].FR1 = (1<<21); // all even IDs
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CAN1->FMR &= ~CAN_FMR_FINIT; /* (12) */
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CAN1->IER |= CAN_IER_ERRIE | CAN_IER_FOVIE0 | CAN_IER_FOVIE1 | CAN_IER_BOFIE; /* (13) */
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/* Configure IT */
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NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0); // RX FIFO0 IRQ
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NVIC_SetPriority(CAN1_RX1_IRQn, 0); // RX FIFO1 IRQ
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NVIC_SetPriority(CAN1_SCE_IRQn, 0); // RX status changed IRQ
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NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
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NVIC_EnableIRQ(CAN1_RX1_IRQn);
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NVIC_EnableIRQ(CAN1_SCE_IRQn);
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CAN1->MSR = 0; // clear SLAKI, WKUI, ERRI
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can_status = CAN_READY;
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}
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void can_proc(){
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// check for messages in FIFO0 & FIFO1
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if(CAN1->RF0R & CAN_RF0R_FMP0){
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can_process_fifo(0);
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}
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if(CAN1->RF1R & CAN_RF1R_FMP1){
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can_process_fifo(1);
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}
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IWDG->KR = IWDG_REFRESH;
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if(CAN1->ESR & (CAN_ESR_BOFF | CAN_ESR_EPVF | CAN_ESR_EWGF)){ // much errors - restart CAN BUS
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usart_send("\nToo much errors, restarting CAN!\n");
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// request abort for all mailboxes
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CAN1->TSR |= CAN_TSR_ABRQ0 | CAN_TSR_ABRQ1 | CAN_TSR_ABRQ2;
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// reset CAN bus
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RCC->APB1RSTR |= RCC_APB1RSTR_CAN1RST;
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RCC->APB1RSTR &= ~RCC_APB1RSTR_CAN1RST;
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CAN_setup(0);
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}
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}
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CAN_status can_send(uint8_t *msg, uint8_t len, uint16_t target_id){
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uint8_t mailbox = 0;
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// check first free mailbox
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if(CAN1->TSR & (CAN_TSR_TME)){
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mailbox = (CAN1->TSR & CAN_TSR_CODE) >> 24;
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}else{ // no free mailboxes
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return CAN_BUSY;
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}
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CAN_TxMailBox_TypeDef *box = &CAN1->sTxMailBox[mailbox];
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uint32_t lb = 0, hb = 0;
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switch(len){
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case 8:
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hb |= (uint32_t)msg[7] << 24;
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__attribute__((fallthrough));
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case 7:
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hb |= (uint32_t)msg[6] << 16;
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__attribute__((fallthrough));
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case 6:
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hb |= (uint32_t)msg[5] << 8;
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__attribute__((fallthrough));
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case 5:
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hb |= (uint32_t)msg[4];
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__attribute__((fallthrough));
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case 4:
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lb |= (uint32_t)msg[3] << 24;
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__attribute__((fallthrough));
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case 3:
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lb |= (uint32_t)msg[2] << 16;
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__attribute__((fallthrough));
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case 2:
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lb |= (uint32_t)msg[1] << 8;
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__attribute__((fallthrough));
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default:
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lb |= (uint32_t)msg[0];
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}
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box->TDLR = lb;
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box->TDHR = hb;
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box->TDTR = len;
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box->TIR = (target_id & 0x7FF) << 21 | CAN_TI0R_TXRQ;
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return CAN_OK;
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}
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static void can_process_fifo(uint8_t fifo_num){
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if(fifo_num > 1) return;
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CAN_FIFOMailBox_TypeDef *box = &CAN1->sFIFOMailBox[fifo_num];
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volatile uint32_t *RFxR = (fifo_num) ? &CAN1->RF1R : &CAN1->RF0R;
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// read all
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while(*RFxR & CAN_RF0R_FMP0){ // amount of messages pending
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// CAN_RDTxR: (16-31) - timestamp, (8-15) - filter match index, (0-3) - data length
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/* TODO: check filter match index if more than one ID can receive */
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CAN_message msg;
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uint8_t *dat = msg.data;
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uint8_t len = box->RDTR & 0x0f;
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msg.length = len;
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msg.ID = box->RIR >> 21;
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//msg.filterNo = (box->RDTR >> 8) & 0xff;
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//msg.fifoNum = fifo_num;
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if(len){ // message can be without data
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uint32_t hb = box->RDHR, lb = box->RDLR;
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switch(len){
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case 8:
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dat[7] = hb>>24;
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__attribute__((fallthrough));
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case 7:
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dat[6] = (hb>>16) & 0xff;
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__attribute__((fallthrough));
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case 6:
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dat[5] = (hb>>8) & 0xff;
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__attribute__((fallthrough));
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case 5:
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dat[4] = hb & 0xff;
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__attribute__((fallthrough));
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case 4:
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dat[3] = lb>>24;
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__attribute__((fallthrough));
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case 3:
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dat[2] = (lb>>16) & 0xff;
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__attribute__((fallthrough));
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case 2:
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dat[1] = (lb>>8) & 0xff;
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__attribute__((fallthrough));
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case 1:
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dat[0] = lb & 0xff;
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}
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}
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if(CAN_messagebuf_push(&msg)) return; // error: buffer is full, try later
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*RFxR |= CAN_RF0R_RFOM0; // release fifo for access to next message
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}
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//if(*RFxR & CAN_RF0R_FULL0) *RFxR &= ~CAN_RF0R_FULL0;
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*RFxR = 0; // clear FOVR & FULL
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}
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void usb_lp_can_rx0_isr(){ // Rx FIFO0 (overrun)
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if(CAN1->RF0R & CAN_RF0R_FOVR0){ // FIFO overrun
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CAN1->RF0R &= ~CAN_RF0R_FOVR0;
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can_status = CAN_FIFO_OVERRUN;
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}
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}
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void can_rx1_isr(){ // Rx FIFO1 (overrun)
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if(CAN1->RF1R & CAN_RF1R_FOVR1){
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CAN1->RF1R &= ~CAN_RF1R_FOVR1;
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can_status = CAN_FIFO_OVERRUN;
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}
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}
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void can_sce_isr(){ // status changed
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if(CAN1->MSR & CAN_MSR_ERRI){ // Error
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CAN1->MSR &= ~CAN_MSR_ERRI;
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// request abort for problem mailbox
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if(CAN1->TSR & CAN_TSR_TERR0) CAN1->TSR |= CAN_TSR_ABRQ0;
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if(CAN1->TSR & CAN_TSR_TERR1) CAN1->TSR |= CAN_TSR_ABRQ1;
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if(CAN1->TSR & CAN_TSR_TERR2) CAN1->TSR |= CAN_TSR_ABRQ2;
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can_status = CAN_ERR;
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}
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}
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