From b89b548e0a9015ca577eeeb1819c7395ad6e3e1c Mon Sep 17 00:00:00 2001 From: Edward Emelianov Date: Sat, 23 Mar 2024 17:43:38 +0300 Subject: [PATCH] add encoder support (LIR-OM158A) --- F3:F303/CANbus4BTA/BTA_CAN.bin | Bin 24560 -> 24924 bytes F3:F303/CANbus4BTA/Readme.md | 1 + F3:F303/CANbus4BTA/canbus4bta.creator.user | 2 +- F3:F303/CANbus4BTA/commonfunctions.c | 17 ++++- F3:F303/CANbus4BTA/encoder.c | 29 +++++--- F3:F303/CANbus4BTA/encoder.h | 3 +- F3:F303/CANbus4BTA/hardware.h | 2 + F3:F303/CANbus4BTA/main.c | 21 +++--- F3:F303/CANbus4BTA/spi.c | 80 ++++++++++++++------- F3:F303/CANbus4BTA/spi.h | 5 +- F3:F303/CANbus4BTA/version.inc | 4 +- 11 files changed, 108 insertions(+), 56 deletions(-) diff --git a/F3:F303/CANbus4BTA/BTA_CAN.bin b/F3:F303/CANbus4BTA/BTA_CAN.bin index fbcf156d502f42f0e9232d681ae87d97635bd4c8..074d8955eafe05f24ca31aa07080e3a57cdc6648 100755 GIT binary patch delta 5524 zcmb_gdvue>m7n<}*|PjVet|8U@L>^ZkO4mk*pdOo57kHpTrim67-WZs2MO!(?QcHG zkkbBg<|NGRevVRoT ziE61o>~R&?1nELtWh=0$rAy)TCbcva9yq|I|C*GZS9D)jq-6`w*j_qA22T(oUVzQu zD!)#1l?vPIvVHvuh<9LGrAkl_5HA&kXH6eTC3F_e=2Bg zQc1SB#Zlxc%Hq?_k8&qeQf=Ifo|^bWyeDI{pZCp7_RWpYN1rLqX6szu+p+0r+=}Hu zQ6;HW#3TeBfaH&{OhqCn5(6Y3$I=uDRU}g&xe`-5NQuG8J$x&s#j1Q*RSzX1*+{Gf ztwcKms0G#nTY(;+7w`f5fR_vLc@uaGI1T(e5CCqpvf1f%!V59BE&Y|WC?vfwd&!@f zv4PS{{wFf4DE)x_G;0pM!am6A&|Tt_mJ_RfwSU2+5}K78QAs}@mqQ=PWKdkqHtQE- z)X(*4f*?lOiJTI_8Ux8^pXEGHf53L+E}~DdIeFYgxvb^zTA3GXT)XcEJ94_9gn*`%_u!nUtpus7fSZ1q}$;Z*buh4~5#6vxX}6Kyrn z05k(@fr(WU>D@c`VnK-S?dMMTd-H0kNhReWnFZ-nnHVFT`e2_c;?8X->g5g_lXI!U zA~Zf^ALUP>|LG6qSJ1k4WVIm8#h?LY(7@e6-H0krP`k_rO_c}Sv}&N!<0|Si*aqCJ z?#3t|nJu&KDF*MO@bM_HPw|x;pX6xoM%a*)Qvy6?k-$SlDh_7{(;Ws^IwThjI+Jdg zN?pi*V$uXOkZJ6>P7)-8zB73^g!_1I0s8^pNpd_rX>+un>kCp%j3Ni#yQ2$dLz5tV5iNu}md(U4{u9=^B73FnI2h?cL=cXA(66^5PI2B+3&*@Z)WFtXP&wZJBa-ar-+ zlRA)SExp4dlt^*DKxHgDQ(&ZX{2v#nXpTEd1}9Gag^)arxY+H&ktv&E5fnr!JsU}E zYe$T4Upf2Kuwn7+7&Usjz7?E?rO$|2y4%S(PlNqjzdEU3py>Z^RPPvdB}$SekO%#Y z7~5B5%__rEYJp~8Z5#Vt(E*{fjjbZIc-0V7>Lmt;IcDeX` z%0`TW`Y)!=r3d}LpZYyI^+klmiscbCX$pWJ0uBN^TraUFr~MCo(f^3}d#W+Z+(=c) zwd_PBkA0KA7+AwX-_uVy~mu&hy1_ z+gC1!o{OV6-H}79W4j&g2vLx(FYuoClRdw}@jMsKsLTtBNc3m9M#*Kg6X%;q?LOvHR7A}X2D~U-pVutx0a!xSO&I%-Qn@X=m&V>u0Rlv0ZpaPXTWI41aLPa^W z842)wcuHj%*70h1O39%*F)+&xt}?f$6c(H0lH@`bCf!&f8zHZiU-d$XuVYoRqYA}_ zN+~dX8evt3d6j6_@;brK^pdff<9eKy%i$T77Y&Uj@9m1?88D5Vti;xYXMIZag4OrM z0-|i`)~f=~f4rrd_#Lw!DWpp#$Xno#^7a)7&VmWF`BO?CQ?YBB+6BtBpt41FMD`F9 zk#6`Rdju2t^L5bO_LX5{xu?_P<`*dcu5(8AP}9nx?d%^+-}ZLc)9Z7)+ToLNtY_CF z_WCh#SFUp{lEb&s(7A?RyPc~Yhuy8{@vUO8vtlgRWpK7Q+TAPc^;qYs&gCdj>zvCR z%k77p&5i?@Cj&u#Qtk?JKdjPTUp=C7xL;G!w=<)}ywlv5I$Ibv_i4>$wxsL{TEdQ% z8FLJdQFkGqrT!vjdHBz2fd$KoX%35(O)+O8`WBozDrH3l6boK35?2cuyn<-(GsQzm z%Bi)O2-XbHtBBO~HdZ%hjc}!n9h!5onsW&5?W&l%Yj@$d&x#FKEq6O4G4*e^axO`4$re$xaz_@)k7Fh!#> zMFFO8L91GEEYgWe+ocXh+@mf}H>!4*r(0zTT_Z+IR|^(1(5VW}b$AmeJ>ur;;O{LM zS8l*r@c&Q41MX5~9pAzvxymG;j1%Jm+zXa&Lqo)!QI*qc=;3#TDp)iT8O0XA6g5MM z>teEE%j3>hY~{n&=i@vkXUB=xsE3EDFEfN+!z90Ce%Ej4vA|zTm$}=6Tjt0`9<^~@MU0pM_BFY`8F90D%(tO z3fp_VRC!Sq1bGcmDOV63B5+FQNVktT(;RA~aVm~Nijvs5PCA`yZi{oL`0dLb;@Ooj z${%e+(ddY;kbL#+-5%#8eiVAL9B;r<7A$4jjW{B?PP{QPMk@Msj&(c0>PGstjzi!^ z`coVuJMLX>d;)?ACMIE5%J>%*l3l}a-ytITSBCU>-!Puu{@aUsF0~60lm!oL^VPU|z1^tcj zQ!Y8QKzYFvX>oj>NTlp|7nZ{B?b%6rWomp8Iy7>q^W<3&2m_9lp@ZOpbjIwF^fBKp}nbCdYaXkr&1SdGaH-MVAhG}Eg9smk}C*l zDGv5^PzliUQr>|#1gIXAmv#}f44BX5!08R_H|Dz8zm2ECq3W0x7t)0Dsd$|bNv%wi zEF*)>9c-@UU3E0{ip(U7NH4MMT9bfExw!U}w=OypMwTew+USGeYoZSYk!~m*=|d%G zS42Io!^#C+7B$1T9GRx{^H>?t*AC6B(L!hzD=i+Ibmdh;q}*r+Mtl;gixK{b;m-wbCeBw(6@11h3iijD29ykTC3)bc=-ryZv zkfHL=eE2LaJ{o@zC;A6C1QYK`<<_XC)(kBZ>fbHI4^uG@C;%p`aszrcTwg>NvajkL zy3=TH<(sQz_J+Aaik9^?RMH=_V+{*=n^y{2Ez>P~Uyx&L zWLYJRvdra==cr*)3oKnuw8OwJm$L)Qk7ONdA=c!cwCDjxeJ~6g;^@m>ZF<0ldEt@v-H#re^Zx=xl ze|S5PYGU2hE?ULP^2+&h%B$v7R_WN% zNB_lp7G*yb{=5e&0V?oe(BemMuE5U#Z3Z&Iw}S2lQouh0dJu@ovivgWdw>S=OQ1J_ zIOJi_ymdsI19>rMIe@xGYC)TUNrZSwE0|s&gBt~X6G#Vt6f^*&fxikm1_;3jeLxgW><2vo@Q%}<0bnxttDraA@y|O{UNVLTK^4vhuLTtW zo+hQB4M0Bl7SJ9b3;Z*nF9WbIzYYq~-M_PFUr5TzQJv-kwLk;V0;~mcsGgg*df2n; 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- if(read_encoder(msg->data + 4)) return ERR_OK; - return ERR_CANTRUN; + uint8_t buf[8]; + if(!read_encoder(buf)) return ERR_CANTRUN; + *((uint32_t*)(msg->data+4)) = *((uint32_t*)buf); +#ifdef EBUG + uint32_t val = buf[0] << 24 | buf[1] << 16 | buf[2] << 8 | buf[3]; + uint32_t timest = *((uint32_t*)(buf + 4)); + USB_sendstr("\nEncoder="); + USB_sendstr(u2str((val & 0x7fffffff)>>5)); + USB_sendstr(", timest="); + USB_sendstr(u2str(timest)); + USB_sendstr(" (raw: "); USB_sendstr(uhex2str(val)); + USB_sendstr(", masked: "); USB_sendstr(uhex2str((val & 0x7fffffff)>>5)); + USB_sendstr(")\n"); +#endif + return ERR_OK; } // reinit encoder static errcodes encreinit(CAN_message _U_ *msg){ diff --git a/F3:F303/CANbus4BTA/encoder.c b/F3:F303/CANbus4BTA/encoder.c index 8a905d9..e1ce862 100644 --- a/F3:F303/CANbus4BTA/encoder.c +++ b/F3:F303/CANbus4BTA/encoder.c @@ -24,6 +24,21 @@ #include "usart.h" #include +#include + +static int rdy = 0; + +void encoder_process(){ + if(!FLAG(ENC_IS_SSI)) return; + static uint32_t lastT = 0; + if(!rdy){ + encoder_setup(); + return; + } + if(Tms - lastT > ENCODER_RD_INTERVAL){ + if(spi_start_enc()) lastT = Tms; // start rd process + } +} void encoder_setup(){ if(FLAG(ENC_IS_SSI)){ @@ -33,15 +48,16 @@ void encoder_setup(){ spi_deinit(ENCODER_SPI); usart_setup(); } + rdy = 1; } // read encoder value into buffer `outbuf` // return TRUE if all OK -int read_encoder(uint8_t outbuf[4]){ - *((uint32_t*)outbuf) = 0; +int read_encoder(uint8_t outbuf[8]){ + bzero(outbuf, 8); if(FLAG(ENC_IS_SSI)){ - int r = spi_read(ENCODER_SPI, outbuf, 4); - return r; + spi_read_enc(outbuf); + return TRUE; } usart_rstbuf(); // just send some trash over USART1 if encoder is RS-422 @@ -62,11 +78,6 @@ int read_encoder(uint8_t outbuf[4]){ void CANsendEnc(){ CAN_message msg = {.data = {0}, .ID = the_conf.encoderID, .length = 8}; if(!read_encoder(msg.data)) return; - uint32_t ctr = TIM2->CNT; - //msg.data[4] = 0; - msg.data[5] = (ctr >> 16) & 0xff; - msg.data[6] = (ctr >> 8 ) & 0xff; - msg.data[7] = (ctr >> 0 ) & 0xff; CAN_send(&msg); } // send limit-switches data diff --git a/F3:F303/CANbus4BTA/encoder.h b/F3:F303/CANbus4BTA/encoder.h index 41addc3..5a6ceed 100644 --- a/F3:F303/CANbus4BTA/encoder.h +++ b/F3:F303/CANbus4BTA/encoder.h @@ -21,6 +21,7 @@ #include void encoder_setup(); -int read_encoder(uint8_t outbuf[4]); +void encoder_process(); +int read_encoder(uint8_t outbuf[8]); void CANsendEnc(); void CANsendLim(); diff --git a/F3:F303/CANbus4BTA/hardware.h b/F3:F303/CANbus4BTA/hardware.h index 26dd084..d953857 100644 --- a/F3:F303/CANbus4BTA/hardware.h +++ b/F3:F303/CANbus4BTA/hardware.h @@ -46,5 +46,7 @@ extern volatile uint32_t Tms; // SPI1 is encoder, SPI2 is ext #define ENCODER_SPI (1) +// read encoder each 10ms +#define ENCODER_RD_INTERVAL (10) void hw_setup(); diff --git a/F3:F303/CANbus4BTA/main.c b/F3:F303/CANbus4BTA/main.c index 4778379..a2168cf 100644 --- a/F3:F303/CANbus4BTA/main.c +++ b/F3:F303/CANbus4BTA/main.c @@ -83,23 +83,20 @@ int main(void){ if(ans) USB_sendstr(ans); } ESW_process(); - static uint8_t oldswitches[2] = {0}; - int send = 0; - for(int i = 0; i < 2; ++i){ - uint8_t new = getESW(i); - if(oldswitches[i] != new){ - send = 1; - oldswitches[i] = new; - USB_sendstr("ESW"); USB_putbyte('0' + i); - USB_sendstr(" changed @"); printu(Tms); - USB_sendstr(" to "); printuhex(new); newline(); - } + static uint8_t oldswitches = 0; + uint8_t new = getESW(1); + if(oldswitches != new){ + oldswitches = new; + USB_sendstr("ESW changed @"); printu(Tms); + USB_sendstr(" to "); printuhex(new); newline(); + CANsendLim(); } + encoder_process(); if(FLAG(EMULATE_PEP)){ if(Tms - encT > ENCODER_PERIOD){ encT = Tms; CANsendEnc(); - } else if(send) CANsendLim(); + } } } } diff --git a/F3:F303/CANbus4BTA/spi.c b/F3:F303/CANbus4BTA/spi.c index 37278e2..b5758a1 100644 --- a/F3:F303/CANbus4BTA/spi.c +++ b/F3:F303/CANbus4BTA/spi.c @@ -18,14 +18,13 @@ #include "hardware.h" #include "spi.h" +#include // memcpy #include "usb.h" #ifdef EBUG #include "strfunc.h" #endif -//#define SPIDR *((volatile uint8_t*)&SPI2->DR) - #define CHKIDX(idx) do{if(idx == 0 || idx > AMOUNT_OF_SPI) return;}while(0) #define CHKIDXR(idx) do{if(idx == 0 || idx > AMOUNT_OF_SPI) return 0;}while(0) @@ -33,6 +32,8 @@ spiStatus spi_status[AMOUNT_OF_SPI+1] = {0, SPI_NOTREADY, SPI_NOTREADY}; static volatile SPI_TypeDef* const SPIs[AMOUNT_OF_SPI+1] = {NULL, SPI1, SPI2}; #define WAITX(x) do{volatile uint32_t wctr = 0; while((x) && (++wctr < 360000)) IWDG->KR = IWDG_REFRESH; if(wctr==360000){ DBG("timeout"); return 0;}}while(0) +static uint8_t encoderbuf[8] = {0}; + // SPI DMA Rx buffer (set by spi_write_dma call) for SPI2 //static uint8_t *rxbufptr = NULL; //static uint32_t rxbuflen = 0; @@ -54,6 +55,13 @@ void spi_setup(uint8_t idx){ RCC->APB1RSTR = 0; // clear reset RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; SPI->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_RXONLY; // software slave management (without hardware NSS pin); RX only + // setup SPI2 DMA + RCC->AHBENR |= RCC_AHBENR_DMA1EN; + SPI1->CR2 = SPI_CR2_RXDMAEN; + // Rx + DMA1_Channel2->CPAR = (uint32_t)&(SPI1->DR); + DMA1_Channel2->CCR = DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_TEIE; // mem inc, hw->mem, Rx complete and error interrupt + NVIC_EnableIRQ(DMA1_Channel2_IRQn); // enable Rx interrupt }else if(idx == 2){ // PB12..PB15 GPIOB->AFR[1] = (GPIOB->AFR[1] & ~(GPIO_AFRH_AFRH4 | GPIO_AFRH_AFRH5 | GPIO_AFRH_AFRH6 | GPIO_AFRH_AFRH7)) | AFRf(5, 12) | AFRf(5, 13) | AFRf(5, 14) | AFRf(5, 15); @@ -62,19 +70,7 @@ void spi_setup(uint8_t idx){ RCC->APB1RSTR = RCC_APB1RSTR_SPI2RST; // reset SPI RCC->APB1RSTR = 0; // clear reset RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; - SPI->CR2 = SPI_CR2_SSOE; // hardware NSS management - // setup SPI2 DMA - //RCC->AHBENR |= RCC_AHBENR_DMA1EN; - //SPI->CR2 |= SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN; - // Tx - /*DMA1_Channel5->CPAR = (uint32_t)&(SPI2->DR); // hardware - DMA1_Channel5->CCR = DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TEIE; // memory increment, mem->hw, error interrupt - // Rx - DMA1_Channel4->CPAR = (uint32_t)&(SPI2->DR); - DMA1_Channel4->CCR = DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_TEIE; // mem inc, hw->mem, Rx complete and error interrupt - NVIC_EnableIRQ(DMA1_Channel4_IRQn); // enable Rx interrupt - NVIC_EnableIRQ(DMA1_Channel5_IRQn); // enable Tx interrupt - */ + SPI->CR2 = SPI_CR2_SSOE | SPI_CR2_FRXTH; // hardware NSS management, RXNE after 8bit; 8bit transfer (default) }else return; // err // Baudrate = 0b110 - fpclk/128 SPI->CR1 |= SPI_CR1_MSTR | SPI_CR1_BR_2 | SPI_CR1_BR_1; @@ -128,13 +124,14 @@ int spi_writeread(uint8_t idx, uint8_t *data, uint32_t n){ DBG("not ready"); return 0; } + volatile SPI_TypeDef *SPI = SPIs[idx]; // clear SPI Rx FIFO - for(int i = 0; i < 4; ++i) (void) SPI2->DR; + for(int i = 0; i < 4; ++i) (void) SPI->DR; for(uint32_t x = 0; x < n; ++x){ - WAITX(!(SPIs[idx]->SR & SPI_SR_TXE)); - *((volatile uint8_t*)&SPIs[idx]->DR) = data[x]; - WAITX(!(SPIs[idx]->SR & SPI_SR_RXNE)); - data[x] = *((volatile uint8_t*)&SPIs[idx]->DR); + WAITX(!(SPI->SR & SPI_SR_TXE)); + *((volatile uint8_t*)&SPI->DR) = data[x]; + WAITX(!(SPI->SR & SPI_SR_RXNE)); + data[x] = *((volatile uint8_t*)&SPI->DR); } return 1; } @@ -146,19 +143,50 @@ int spi_read(uint8_t idx, uint8_t *data, uint32_t n){ DBG("not ready"); return 0; } + volatile SPI_TypeDef *SPI = SPIs[idx]; // clear SPI Rx FIFO - for(int i = 0; i < 4; ++i) (void) SPI2->DR; + for(int i = 0; i < 4; ++i) (void) SPI->DR; spi_onoff(idx, TRUE); for(uint32_t x = 0; x < n; ++x){ - if(x == n - 1) SPIs[idx]->CR1 &= ~SPI_CR1_RXONLY; - WAITX(!(SPIs[idx]->SR & SPI_SR_RXNE)); - data[x] = *((volatile uint8_t*)&SPIs[idx]->DR); + if(x == n - 1) SPI->CR1 &= ~SPI_CR1_RXONLY; // clear RXonly bit to stop CLK generation after next byte + WAITX(!(SPI->SR & SPI_SR_RXNE)); + data[x] = *((volatile uint8_t*)&SPI->DR); } - spi_onoff(idx, FALSE); - SPIs[idx]->CR1 |= SPI_CR1_RXONLY; + spi_onoff(idx, FALSE); // turn off SPI + SPI->CR1 |= SPI_CR1_RXONLY; // and return RXonly bit return 1; } +// just copy last read encoder value into `buf` +void spi_read_enc(uint8_t buf[8]){ + memcpy(buf, encoderbuf, 8); +} + +// start encoder reading over DMA +// @return FALSE if SPI is busy +int spi_start_enc(){ + if(spi_status[1] != SPI_READY) return FALSE; + if(!spi_waitbsy(1)) return FALSE; + DMA1_Channel2->CMAR = (uint32_t) encoderbuf; + DMA1_Channel2->CNDTR = 4; + DMA1_Channel2->CCR |= DMA_CCR_EN; + spi_onoff(1, 1); + return TRUE; +} + +// SSI got fresh data +void dma1_channel2_isr(){ + spi_onoff(1, 0); + uint32_t ctr = TIM2->CNT; + spi_status[1] = SPI_READY; // ready independent on errors or Rx ready + DMA1->IFCR = DMA_IFCR_CTCIF2 | DMA_IFCR_CTEIF2; + // turn off DMA + DMA1_Channel2->CCR &= ~DMA_CCR_EN; + encoderbuf[5] = (ctr >> 16) & 0xff; + encoderbuf[6] = (ctr >> 8 ) & 0xff; + encoderbuf[7] = (ctr >> 0 ) & 0xff; +} + /** * @brief spi_send_dma - send data over SPI2 through DMA (used both for writing and reading) * @param data - data to read diff --git a/F3:F303/CANbus4BTA/spi.h b/F3:F303/CANbus4BTA/spi.h index ea6d691..53101c4 100644 --- a/F3:F303/CANbus4BTA/spi.h +++ b/F3:F303/CANbus4BTA/spi.h @@ -35,6 +35,5 @@ void spi_setup(uint8_t idx); int spi_waitbsy(uint8_t idx); int spi_writeread(uint8_t idx, uint8_t *data, uint32_t n); int spi_read(uint8_t idx, uint8_t *data, uint32_t n); -//int spi_write_dma(const uint8_t *data, uint8_t *rxbuf, uint32_t n); -//int spi_read(uint8_t idx, uint8_t *data, uint32_t n); -//uint8_t *spi_read_dma(uint32_t *n); +int spi_start_enc(); +void spi_read_enc(uint8_t buf[8]); diff --git a/F3:F303/CANbus4BTA/version.inc b/F3:F303/CANbus4BTA/version.inc index 1e7bae8..d46762e 100644 --- a/F3:F303/CANbus4BTA/version.inc +++ b/F3:F303/CANbus4BTA/version.inc @@ -1,2 +1,2 @@ -#define BUILD_NUMBER "93" -#define BUILD_DATE "2024-03-17" +#define BUILD_NUMBER "100" +#define BUILD_DATE "2024-03-23"