diff --git a/F3:F303/CANbus4BTA/BTA_CAN.bin b/F3:F303/CANbus4BTA/BTA_CAN.bin
index fbcf156..074d895 100755
Binary files a/F3:F303/CANbus4BTA/BTA_CAN.bin and b/F3:F303/CANbus4BTA/BTA_CAN.bin differ
diff --git a/F3:F303/CANbus4BTA/Readme.md b/F3:F303/CANbus4BTA/Readme.md
index a33949a..3f1c916 100644
--- a/F3:F303/CANbus4BTA/Readme.md
+++ b/F3:F303/CANbus4BTA/Readme.md
@@ -119,6 +119,7 @@ PP - push-pull, OD - open drain, I - floating input, A - analog input, AFn - alt
 ## DMA1
 
 Channel1 - ADC1.
+Channel2 - SPI1_Rx (SSI interface).
 
 ## DMA2
 
diff --git a/F3:F303/CANbus4BTA/canbus4bta.creator.user b/F3:F303/CANbus4BTA/canbus4bta.creator.user
index 3293279..85c8feb 100644
--- a/F3:F303/CANbus4BTA/canbus4bta.creator.user
+++ b/F3:F303/CANbus4BTA/canbus4bta.creator.user
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <!DOCTYPE QtCreatorProject>
-<!-- Written by QtCreator 12.0.2, 2024-03-18T00:40:28. -->
+<!-- Written by QtCreator 12.0.2, 2024-03-23T17:42:29. -->
 <qtcreator>
  <data>
   <variable>EnvironmentId</variable>
diff --git a/F3:F303/CANbus4BTA/commonfunctions.c b/F3:F303/CANbus4BTA/commonfunctions.c
index 1daa126..f240355 100644
--- a/F3:F303/CANbus4BTA/commonfunctions.c
+++ b/F3:F303/CANbus4BTA/commonfunctions.c
@@ -148,8 +148,21 @@ static errcodes sendspi2(CAN_message *msg){
 // read encoder value and send over CAN
 static errcodes encget(CAN_message *msg){
     FIXDL(msg);
-    if(read_encoder(msg->data + 4)) return ERR_OK;
-    return ERR_CANTRUN;
+    uint8_t buf[8];
+    if(!read_encoder(buf)) return ERR_CANTRUN;
+    *((uint32_t*)(msg->data+4)) = *((uint32_t*)buf);
+#ifdef EBUG
+    uint32_t val = buf[0] << 24 | buf[1] << 16 | buf[2] << 8 | buf[3];
+    uint32_t timest = *((uint32_t*)(buf + 4));
+    USB_sendstr("\nEncoder=");
+    USB_sendstr(u2str((val & 0x7fffffff)>>5));
+    USB_sendstr(", timest=");
+    USB_sendstr(u2str(timest));
+    USB_sendstr(" (raw: "); USB_sendstr(uhex2str(val));
+    USB_sendstr(", masked: "); USB_sendstr(uhex2str((val & 0x7fffffff)>>5));
+    USB_sendstr(")\n");
+#endif
+    return ERR_OK;
 }
 // reinit encoder
 static errcodes encreinit(CAN_message _U_ *msg){
diff --git a/F3:F303/CANbus4BTA/encoder.c b/F3:F303/CANbus4BTA/encoder.c
index 8a905d9..e1ce862 100644
--- a/F3:F303/CANbus4BTA/encoder.c
+++ b/F3:F303/CANbus4BTA/encoder.c
@@ -24,6 +24,21 @@
 #include "usart.h"
 
 #include <string.h>
+#include <strings.h>
+
+static int rdy = 0;
+
+void encoder_process(){
+    if(!FLAG(ENC_IS_SSI)) return;
+    static uint32_t lastT = 0;
+    if(!rdy){
+        encoder_setup();
+        return;
+    }
+    if(Tms - lastT > ENCODER_RD_INTERVAL){
+        if(spi_start_enc()) lastT = Tms; // start rd process
+    }
+}
 
 void encoder_setup(){
     if(FLAG(ENC_IS_SSI)){
@@ -33,15 +48,16 @@ void encoder_setup(){
         spi_deinit(ENCODER_SPI);
         usart_setup();
     }
+    rdy = 1;
 }
 
 // read encoder value into buffer `outbuf`
 // return TRUE if all OK
-int read_encoder(uint8_t outbuf[4]){
-    *((uint32_t*)outbuf) = 0;
+int read_encoder(uint8_t outbuf[8]){
+    bzero(outbuf, 8);
     if(FLAG(ENC_IS_SSI)){
-        int r = spi_read(ENCODER_SPI, outbuf, 4);
-        return r;
+        spi_read_enc(outbuf);
+        return TRUE;
     }
     usart_rstbuf();
     // just send some trash over USART1 if encoder is RS-422
@@ -62,11 +78,6 @@ int read_encoder(uint8_t outbuf[4]){
 void CANsendEnc(){
     CAN_message msg = {.data = {0}, .ID = the_conf.encoderID, .length = 8};
     if(!read_encoder(msg.data)) return;
-    uint32_t ctr = TIM2->CNT;
-    //msg.data[4] = 0;
-    msg.data[5] = (ctr >> 16) & 0xff;
-    msg.data[6] = (ctr >> 8 ) & 0xff;
-    msg.data[7] = (ctr >> 0 ) & 0xff;
     CAN_send(&msg);
 }
 // send limit-switches data
diff --git a/F3:F303/CANbus4BTA/encoder.h b/F3:F303/CANbus4BTA/encoder.h
index 41addc3..5a6ceed 100644
--- a/F3:F303/CANbus4BTA/encoder.h
+++ b/F3:F303/CANbus4BTA/encoder.h
@@ -21,6 +21,7 @@
 #include <stdint.h>
 
 void encoder_setup();
-int read_encoder(uint8_t outbuf[4]);
+void encoder_process();
+int read_encoder(uint8_t outbuf[8]);
 void CANsendEnc();
 void CANsendLim();
diff --git a/F3:F303/CANbus4BTA/hardware.h b/F3:F303/CANbus4BTA/hardware.h
index 26dd084..d953857 100644
--- a/F3:F303/CANbus4BTA/hardware.h
+++ b/F3:F303/CANbus4BTA/hardware.h
@@ -46,5 +46,7 @@ extern volatile uint32_t Tms;
 
 // SPI1 is encoder, SPI2 is ext
 #define ENCODER_SPI     (1)
+// read encoder each 10ms
+#define ENCODER_RD_INTERVAL (10)
 
 void hw_setup();
diff --git a/F3:F303/CANbus4BTA/main.c b/F3:F303/CANbus4BTA/main.c
index 4778379..a2168cf 100644
--- a/F3:F303/CANbus4BTA/main.c
+++ b/F3:F303/CANbus4BTA/main.c
@@ -83,23 +83,20 @@ int main(void){
             if(ans) USB_sendstr(ans);
         }
         ESW_process();
-        static uint8_t oldswitches[2] = {0};
-        int send = 0;
-        for(int i = 0; i < 2; ++i){
-            uint8_t new = getESW(i);
-            if(oldswitches[i] != new){
-                send = 1;
-                oldswitches[i] = new;
-                USB_sendstr("ESW"); USB_putbyte('0' + i);
-                USB_sendstr(" changed @"); printu(Tms);
-                USB_sendstr(" to "); printuhex(new); newline();
-            }
+        static uint8_t oldswitches = 0;
+        uint8_t new = getESW(1);
+        if(oldswitches != new){
+            oldswitches = new;
+            USB_sendstr("ESW changed @"); printu(Tms);
+            USB_sendstr(" to "); printuhex(new); newline();
+            CANsendLim();
         }
+        encoder_process();
         if(FLAG(EMULATE_PEP)){
             if(Tms - encT > ENCODER_PERIOD){
                 encT = Tms;
                 CANsendEnc();
-            } else if(send) CANsendLim();
+            }
         }
     }
 }
diff --git a/F3:F303/CANbus4BTA/spi.c b/F3:F303/CANbus4BTA/spi.c
index 37278e2..b5758a1 100644
--- a/F3:F303/CANbus4BTA/spi.c
+++ b/F3:F303/CANbus4BTA/spi.c
@@ -18,14 +18,13 @@
 
 #include "hardware.h"
 #include "spi.h"
+#include <string.h> // memcpy
 
 #include "usb.h"
 #ifdef EBUG
 #include "strfunc.h"
 #endif
 
-//#define SPIDR   *((volatile uint8_t*)&SPI2->DR)
-
 #define CHKIDX(idx) do{if(idx == 0 || idx > AMOUNT_OF_SPI) return;}while(0)
 #define CHKIDXR(idx) do{if(idx == 0 || idx > AMOUNT_OF_SPI) return 0;}while(0)
 
@@ -33,6 +32,8 @@ spiStatus spi_status[AMOUNT_OF_SPI+1] = {0, SPI_NOTREADY, SPI_NOTREADY};
 static volatile SPI_TypeDef* const SPIs[AMOUNT_OF_SPI+1] = {NULL, SPI1, SPI2};
 #define WAITX(x)  do{volatile uint32_t  wctr = 0; while((x) && (++wctr < 360000)) IWDG->KR = IWDG_REFRESH; if(wctr==360000){ DBG("timeout"); return 0;}}while(0)
 
+static uint8_t encoderbuf[8] = {0};
+
 // SPI DMA Rx buffer (set by spi_write_dma call) for SPI2
 //static uint8_t *rxbufptr = NULL;
 //static uint32_t rxbuflen = 0;
@@ -54,6 +55,13 @@ void spi_setup(uint8_t idx){
         RCC->APB1RSTR = 0; // clear reset
         RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
         SPI->CR1 = SPI_CR1_SSM | SPI_CR1_SSI | SPI_CR1_RXONLY; // software slave management (without hardware NSS pin); RX only
+        // setup SPI2 DMA
+        RCC->AHBENR |= RCC_AHBENR_DMA1EN;
+        SPI1->CR2 = SPI_CR2_RXDMAEN;
+        // Rx
+        DMA1_Channel2->CPAR = (uint32_t)&(SPI1->DR);
+        DMA1_Channel2->CCR = DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_TEIE; // mem inc, hw->mem, Rx complete and error interrupt
+        NVIC_EnableIRQ(DMA1_Channel2_IRQn); // enable Rx interrupt
     }else if(idx == 2){ // PB12..PB15
         GPIOB->AFR[1] = (GPIOB->AFR[1] & ~(GPIO_AFRH_AFRH4 | GPIO_AFRH_AFRH5 | GPIO_AFRH_AFRH6 | GPIO_AFRH_AFRH7)) |
                         AFRf(5, 12) | AFRf(5, 13) | AFRf(5, 14) | AFRf(5, 15);
@@ -62,19 +70,7 @@ void spi_setup(uint8_t idx){
         RCC->APB1RSTR = RCC_APB1RSTR_SPI2RST; // reset SPI
         RCC->APB1RSTR = 0; // clear reset
         RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
-        SPI->CR2 = SPI_CR2_SSOE; // hardware NSS management
-        // setup SPI2 DMA
-        //RCC->AHBENR |= RCC_AHBENR_DMA1EN;
-        //SPI->CR2 |= SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN;
-        // Tx
-        /*DMA1_Channel5->CPAR = (uint32_t)&(SPI2->DR); // hardware
-        DMA1_Channel5->CCR = DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TEIE; // memory increment, mem->hw, error interrupt
-        // Rx
-        DMA1_Channel4->CPAR = (uint32_t)&(SPI2->DR);
-        DMA1_Channel4->CCR = DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_TEIE; // mem inc, hw->mem, Rx complete and error interrupt
-        NVIC_EnableIRQ(DMA1_Channel4_IRQn); // enable Rx interrupt
-        NVIC_EnableIRQ(DMA1_Channel5_IRQn); // enable Tx interrupt
-        */
+        SPI->CR2 = SPI_CR2_SSOE | SPI_CR2_FRXTH; // hardware NSS management, RXNE after 8bit; 8bit transfer (default)
     }else return; // err
     // Baudrate = 0b110 - fpclk/128
     SPI->CR1 |= SPI_CR1_MSTR | SPI_CR1_BR_2 | SPI_CR1_BR_1;
@@ -128,13 +124,14 @@ int spi_writeread(uint8_t idx, uint8_t *data, uint32_t n){
         DBG("not ready");
         return 0;
     }
+    volatile SPI_TypeDef *SPI = SPIs[idx];
     // clear SPI Rx FIFO
-    for(int i = 0; i < 4; ++i) (void) SPI2->DR;
+    for(int i = 0; i < 4; ++i) (void) SPI->DR;
     for(uint32_t x = 0; x < n; ++x){
-        WAITX(!(SPIs[idx]->SR & SPI_SR_TXE));
-        *((volatile uint8_t*)&SPIs[idx]->DR) = data[x];
-        WAITX(!(SPIs[idx]->SR & SPI_SR_RXNE));
-        data[x] = *((volatile uint8_t*)&SPIs[idx]->DR);
+        WAITX(!(SPI->SR & SPI_SR_TXE));
+        *((volatile uint8_t*)&SPI->DR) = data[x];
+        WAITX(!(SPI->SR & SPI_SR_RXNE));
+        data[x] = *((volatile uint8_t*)&SPI->DR);
     }
     return 1;
 }
@@ -146,19 +143,50 @@ int spi_read(uint8_t idx, uint8_t *data, uint32_t n){
         DBG("not ready");
         return 0;
     }
+    volatile SPI_TypeDef *SPI = SPIs[idx];
     // clear SPI Rx FIFO
-    for(int i = 0; i < 4; ++i) (void) SPI2->DR;
+    for(int i = 0; i < 4; ++i) (void) SPI->DR;
     spi_onoff(idx, TRUE);
     for(uint32_t x = 0; x < n; ++x){
-        if(x == n - 1) SPIs[idx]->CR1 &= ~SPI_CR1_RXONLY;
-        WAITX(!(SPIs[idx]->SR & SPI_SR_RXNE));
-        data[x] = *((volatile uint8_t*)&SPIs[idx]->DR);
+        if(x == n - 1) SPI->CR1 &= ~SPI_CR1_RXONLY; // clear RXonly bit to stop CLK generation after next byte
+        WAITX(!(SPI->SR & SPI_SR_RXNE));
+        data[x] = *((volatile uint8_t*)&SPI->DR);
     }
-    spi_onoff(idx, FALSE);
-    SPIs[idx]->CR1 |= SPI_CR1_RXONLY;
+    spi_onoff(idx, FALSE); // turn off SPI
+    SPI->CR1 |= SPI_CR1_RXONLY; // and return RXonly bit
     return 1;
 }
 
+// just copy last read encoder value into `buf`
+void spi_read_enc(uint8_t buf[8]){
+    memcpy(buf, encoderbuf, 8);
+}
+
+// start encoder reading over DMA
+// @return FALSE if SPI is busy
+int spi_start_enc(){
+    if(spi_status[1] != SPI_READY) return FALSE;
+    if(!spi_waitbsy(1)) return FALSE;
+    DMA1_Channel2->CMAR = (uint32_t) encoderbuf;
+    DMA1_Channel2->CNDTR = 4;
+    DMA1_Channel2->CCR |= DMA_CCR_EN;
+    spi_onoff(1, 1);
+    return TRUE;
+}
+
+// SSI got fresh data
+void dma1_channel2_isr(){
+    spi_onoff(1, 0);
+    uint32_t ctr = TIM2->CNT;
+    spi_status[1] = SPI_READY; // ready independent on errors or Rx ready
+    DMA1->IFCR = DMA_IFCR_CTCIF2 | DMA_IFCR_CTEIF2;
+    // turn off DMA
+    DMA1_Channel2->CCR &= ~DMA_CCR_EN;
+    encoderbuf[5] = (ctr >> 16) & 0xff;
+    encoderbuf[6] = (ctr >> 8 ) & 0xff;
+    encoderbuf[7] = (ctr >> 0 ) & 0xff;
+}
+
 /**
  * @brief spi_send_dma - send data over SPI2 through DMA (used both for writing and reading)
  * @param data - data to read
diff --git a/F3:F303/CANbus4BTA/spi.h b/F3:F303/CANbus4BTA/spi.h
index ea6d691..53101c4 100644
--- a/F3:F303/CANbus4BTA/spi.h
+++ b/F3:F303/CANbus4BTA/spi.h
@@ -35,6 +35,5 @@ void spi_setup(uint8_t idx);
 int spi_waitbsy(uint8_t idx);
 int spi_writeread(uint8_t idx, uint8_t *data, uint32_t n);
 int spi_read(uint8_t idx, uint8_t *data, uint32_t n);
-//int spi_write_dma(const uint8_t *data, uint8_t *rxbuf, uint32_t n);
-//int spi_read(uint8_t idx, uint8_t *data, uint32_t n);
-//uint8_t *spi_read_dma(uint32_t *n);
+int spi_start_enc();
+void spi_read_enc(uint8_t buf[8]);
diff --git a/F3:F303/CANbus4BTA/version.inc b/F3:F303/CANbus4BTA/version.inc
index 1e7bae8..d46762e 100644
--- a/F3:F303/CANbus4BTA/version.inc
+++ b/F3:F303/CANbus4BTA/version.inc
@@ -1,2 +1,2 @@
-#define BUILD_NUMBER "93"
-#define BUILD_DATE "2024-03-17"
+#define BUILD_NUMBER "100"
+#define BUILD_DATE "2024-03-23"