mirror of
https://github.com/eddyem/stm32samples.git
synced 2026-02-28 03:44:30 +03:00
test USART with ringbuffer - OK; TODO: rewrite all proto for usage USB & USART
This commit is contained in:
Edward Emelianov
386
F3:F303/MLX90640-allsky/i2c.c
Normal file
386
F3:F303/MLX90640-allsky/i2c.c
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@@ -0,0 +1,386 @@
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/*
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* This file is part of the i2cscan project.
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* Copyright 2023 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stm32f3.h>
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#include <string.h>
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#include "i2c.h"
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#include "strfunc.h" // hexdump
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#include "usb_dev.h"
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i2c_speed_t i2c_curspeed = I2C_SPEED_AMOUNT;
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extern volatile uint32_t Tms;
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static uint32_t cntr;
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volatile uint8_t i2c_scanmode = 0; // == 1 when I2C is in scan mode
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static volatile uint8_t i2c_got_DMA = 0; // got DMA data
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static uint8_t i2caddr = I2C_ADDREND; // current address in scan mode
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static volatile int I2Cbusy = 0, goterr = 0; // busy==1 when DMA active, goterr==1 if 't was error @ last sent
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static uint16_t I2Cbuf[I2C_BUFSIZE];
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static uint16_t i2cbuflen = 0; // buffer for DMA rx and its len
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static volatile uint16_t dma_remain = 0; // remain bytes of DMA read/write
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static uint8_t dmaaddr = 0; // address to continuous read by DMA
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// macros for I2C rx/tx
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#define DMARXCCR (DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_TEIE)
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#define DMATXCCR (DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE | DMA_CCR_TEIE)
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// macro for I2CCR1
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#define I2CCR1 (I2C_CR1_PE | I2C_CR1_RXDMAEN | I2C_CR1_TXDMAEN)
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// return 1 if I2Cbusy is set & timeout reached
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static inline int isI2Cbusy(){
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cntr = Tms;
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do{
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if(Tms - cntr > I2C_TIMEOUT){ USND("Timeout, DMA transfer in progress?"); return 1;}
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}while(I2Cbusy);
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return 0;
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}
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static void swapbytes(uint16_t *data, uint16_t datalen){
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if(!datalen) return;
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for(int i = 0; i < datalen; ++i)
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data[i] = __REV16(data[i]);
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}
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// GPIO Resources: I2C1_SCL - PB6 (AF4), I2C1_SDA - PB7 (AF4)
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void i2c_setup(i2c_speed_t speed){
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uint8_t PRESC, SCLDEL = 0x04, SDADEL = 0x03, SCLH, SCLL; // I2C1->TIMINGR fields
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switch(speed){
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case I2C_SPEED_10K:
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PRESC = 0x0F;
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SCLH = 0xDA;
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SCLL = 0xE0;
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break;
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case I2C_SPEED_100K:
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PRESC = 0x0F;
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SCLH = 0x13;
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SCLL = 0x16;
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break;
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case I2C_SPEED_400K:
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PRESC = 0x07;
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SCLH = 0x08;
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SCLL = 0x09;
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break;
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case I2C_SPEED_1M:
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SDADEL = 1;
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SCLDEL = 2;
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PRESC = 0x3;
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SCLH = 0x4;
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SCLL = 0x6;
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break;
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case I2C_SPEED_2M:
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SDADEL = 0;
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SCLDEL = 1;
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PRESC = 0x0;
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SCLH = 0x1;
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SCLL = 0x2;
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break;
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default:
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USND("Wrong I2C speed!");
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return; // wrong speed
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}
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RCC->AHBENR |= RCC_AHBENR_GPIOBEN;
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I2C1->CR1 = 0; // disable I2C for setup
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I2C1->ICR = 0x3f38; // clear all errors
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GPIOB->AFR[0] = (GPIOB->AFR[0] & ~(GPIO_AFRL_AFRL6 | GPIO_AFRL_AFRL7)) |
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AFRf(4, 6) | AFRf(4, 7);
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GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER6 | GPIO_MODER_MODER7)) |
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MODER_AF(6) | MODER_AF(7);
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GPIOB->PUPDR = (GPIOB->PUPDR & !(GPIO_PUPDR_PUPDR6 | GPIO_PUPDR_PUPDR7)) |
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PUPD_PU(6) | PUPD_PU(7); // pullup (what if there's no external pullup?)
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GPIOB->OTYPER |= OTYPER_OD(6) | OTYPER_OD(7); // both open-drain outputs
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GPIOB->OSPEEDR = (GPIOB->OSPEEDR & OSPEED_CLR(6) & OSPEED_CLR(7)) |
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OSPEED_HI(6) | OSPEED_HI(7);
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// I2C (default timing from sys clock - 72MHz)
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RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // clocking
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if(speed < I2C_SPEED_400K){ // slow cpeed - common mode
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SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_I2C1_FMP | SYSCFG_CFGR1_I2C_PB6_FMP | SYSCFG_CFGR1_I2C_PB7_FMP);
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}else{ // activate "fast mode plus"
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SYSCFG->CFGR1 |= SYSCFG_CFGR1_I2C1_FMP | SYSCFG_CFGR1_I2C_PB6_FMP | SYSCFG_CFGR1_I2C_PB7_FMP;
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}
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I2C1->TIMINGR = (PRESC<<I2C_TIMINGR_PRESC_Pos) | (SCLDEL<<I2C_TIMINGR_SCLDEL_Pos) |
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(SDADEL<<I2C_TIMINGR_SDADEL_Pos) | (SCLH<<I2C_TIMINGR_SCLH_Pos) | (SCLL<< I2C_TIMINGR_SCLL_Pos);
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I2C1->CR1 = I2CCR1;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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NVIC_EnableIRQ(DMA1_Channel6_IRQn);
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NVIC_EnableIRQ(DMA1_Channel7_IRQn);
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I2Cbusy = 0;
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i2c_curspeed = speed;
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}
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// setup DMA for rx (tx==0) or tx (tx==1)
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// DMA channels: 7 - I2C1_Rx, 6 - I2C1_Tx
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static void i2cDMAsetup(int tx, uint16_t len){
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i2cbuflen = len;
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if(len > 255) len = 255;
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if(tx){
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DMA1_Channel6->CCR = DMATXCCR;
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DMA1_Channel6->CPAR = (uint32_t) &I2C1->TXDR;
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DMA1_Channel6->CMAR = (uint32_t) I2Cbuf;
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DMA1_Channel6->CNDTR = len;
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}else{
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DMA1_Channel7->CCR = DMARXCCR;
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DMA1_Channel7->CPAR = (uint32_t) &I2C1->RXDR;
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DMA1_Channel7->CMAR = (uint32_t) I2Cbuf;
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DMA1_Channel7->CNDTR = len;
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}
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}
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// wait until bit set or clear; return 1 if OK, 0 in case of timeout
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static uint8_t waitISRbit(uint32_t bit, uint8_t isset){
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uint32_t waitwhile = (isset) ? 0 : bit; // wait until !=
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cntr = Tms;
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while((I2C1->ISR & bit) == waitwhile){
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IWDG->KR = IWDG_REFRESH;
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if(I2C1->ISR & I2C_ISR_NACKF){
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goto goterr;
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}
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if(Tms - cntr > I2C_TIMEOUT){
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goto goterr;
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}
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}
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return 1;
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goterr:
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I2C1->ICR = 0xff;
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return 0;
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}
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// start writing
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static uint8_t i2c_startw(uint8_t addr, uint8_t nbytes, uint8_t stop){
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if(!waitISRbit(I2C_ISR_BUSY, 0)) return 0;
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uint32_t cr2 = nbytes << 16 | addr | I2C_CR2_START;
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if(stop) cr2 |= I2C_CR2_AUTOEND;
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// now start transfer
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I2C1->CR2 = cr2;
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return 1;
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}
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/**
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* write command byte to I2C
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* @param addr - device address
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* @param data - bytes to write
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* @param nbytes - amount of bytes to write
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* @param stop - to set STOP
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* @return 0 if error
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*/
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static uint8_t i2c_writes(uint8_t addr, uint8_t *data, uint8_t nbytes, uint8_t stop){
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if(!i2c_startw(addr, nbytes, stop)) return 0;
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for(int i = 0; i < nbytes; ++i){
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cntr = Tms;
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while(!(I2C1->ISR & I2C_ISR_TXIS)){ // ready to transmit
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IWDG->KR = IWDG_REFRESH;
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if(I2C1->ISR & I2C_ISR_NACKF){
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I2C1->ICR |= I2C_ICR_NACKCF;
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return 0;
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}
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if(Tms - cntr > I2C_TIMEOUT){
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return 0;
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}
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}
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I2C1->TXDR = data[i]; // send data
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}
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cntr = Tms;
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if(stop){
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if(!waitISRbit(I2C_ISR_BUSY, 0)) return 0;
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}else{ // repeated start
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if(!waitISRbit(I2C_ISR_TC, 1)) return 0;
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}
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return 1;
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}
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uint8_t i2c_write(uint8_t addr, uint16_t *data, uint8_t nwords){
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if(nwords < 1 || nwords > 127) return 0;
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if(isI2Cbusy()) return 0;
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uint16_t nbytes = nwords << 1;
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swapbytes(data, nwords);
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return i2c_writes(addr, (uint8_t*)data, nbytes, 1);
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}
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uint8_t i2c_write_dma16(uint8_t addr, uint16_t *data, uint8_t nwords){
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if(!data || nwords < 1 || nwords > 127) return 0;
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if(isI2Cbusy()) return 0;
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uint16_t nbytes = nwords << 1;
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swapbytes(data, nwords);
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i2cDMAsetup(1, nbytes);
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goterr = 0;
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if(!i2c_startw(addr, nbytes, 1)) return 0;
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I2Cbusy = 1;
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DMA1_Channel6->CCR = DMATXCCR | DMA_CCR_EN; // start transfer
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return 1;
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}
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// start reading of `nbytes` from `addr`; if `start`==`, set START
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static uint8_t i2c_startr(uint8_t addr, uint16_t nbytes, uint8_t start){
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uint32_t cr2 = addr | I2C_CR2_RD_WRN;
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if(nbytes > 255) cr2 |= I2C_CR2_RELOAD | (0xff0000);
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else cr2 |= I2C_CR2_AUTOEND | (nbytes << 16);
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I2C1->CR2 = (start) ? cr2 | I2C_CR2_START : cr2;
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return 1;
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}
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/**
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* read nbytes of data from I2C line
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* all functions with `addr` should have addr = address << 1
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* `data` should be an array with at least `nbytes` length
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* @return 1 if all OK, 0 if NACK or no device found
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*/
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static uint8_t *i2c_readb(uint8_t addr, uint16_t nbytes){
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uint8_t start = 1;
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uint8_t *bptr = (uint8_t*)I2Cbuf;
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while(nbytes){
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if(!i2c_startr(addr, nbytes, start)) return NULL;
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if(nbytes < 256){
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for(int i = 0; i < nbytes; ++i){
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if(!waitISRbit(I2C_ISR_RXNE, 1)) return NULL;
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*bptr++ = I2C1->RXDR;
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}
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break;
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}else while(!(I2C1->ISR & I2C_ISR_TCR)){ // until first part read
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if(!waitISRbit(I2C_ISR_RXNE, 1)) return NULL;
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*bptr++ = I2C1->RXDR;
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}
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nbytes -= 255;
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start = 0;
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}
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return (uint8_t*)I2Cbuf;
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}
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uint8_t *i2c_read(uint8_t addr, uint16_t nbytes){
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if(isI2Cbusy() || !waitISRbit(I2C_ISR_BUSY, 0) || nbytes < 1 || nbytes > I2C_BUFSIZE*2) return 0;
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return i2c_readb(addr, nbytes);
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}
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static uint8_t dmard(uint8_t addr, uint16_t nbytes){
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if(nbytes < 1 || nbytes > I2C_BUFSIZE*2) return 0;
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i2cDMAsetup(0, nbytes);
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goterr = 0;
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i2c_got_DMA = 0;
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(void) I2C1->RXDR; // avoid wrong first byte
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DMA1_Channel7->CCR = DMARXCCR | DMA_CCR_EN; // init DMA before START sequence
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if(!i2c_startr(addr, nbytes, 1)) return 0;
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dmaaddr = addr;
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dma_remain = nbytes > 255 ? nbytes - 255 : 0; // remainder after first read finish
|
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I2Cbusy = 1;
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return 1;
|
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}
|
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|
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uint8_t i2c_read_dma16(uint8_t addr, uint16_t nwords){
|
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if(nwords > I2C_BUFSIZE) return 0; // what if `nwords` is very large? we should check it
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if(isI2Cbusy() || !waitISRbit(I2C_ISR_BUSY, 0)) return 0;
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return dmard(addr, nwords<<1);
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}
|
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|
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// read 16bit register reg
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uint16_t *i2c_read_reg16(uint8_t addr, uint16_t reg16, uint16_t nwords, uint8_t isdma){
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if(isI2Cbusy() || !waitISRbit(I2C_ISR_BUSY, 0) || nwords < 1 || nwords > I2C_BUFSIZE) return 0;
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reg16 = __REV16(reg16);
|
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if(!i2c_writes(addr, (uint8_t*)®16, 2, 0)) return NULL;
|
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if(isdma){
|
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if(dmard(addr, nwords<<1)) return I2Cbuf;
|
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return NULL;
|
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}
|
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if(!i2c_readb(addr, nwords<<1)) return NULL;
|
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swapbytes((uint16_t*)I2Cbuf, nwords);
|
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return (uint16_t*)I2Cbuf;
|
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}
|
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|
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void i2c_init_scan_mode(){
|
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i2caddr = 1; // start from 1 as 0 is a broadcast address
|
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i2c_scanmode = 1;
|
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}
|
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|
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// return 1 if next addr is active & return in as `addr`
|
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// if addresses are over, return 1 and set addr to I2C_NOADDR
|
||||
// if scan mode inactive, return 0 and set addr to I2C_NOADDR
|
||||
int i2c_scan_next_addr(uint8_t *addr){
|
||||
if(isI2Cbusy()) return 0;
|
||||
*addr = i2caddr;
|
||||
if(i2caddr == I2C_ADDREND){
|
||||
*addr = I2C_ADDREND;
|
||||
i2c_scanmode = 0;
|
||||
return 0;
|
||||
}
|
||||
if(!i2c_read((i2caddr++)<<1, 1)) return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
// dump I2Cbuf
|
||||
void i2c_bufdudump(){
|
||||
if(goterr){
|
||||
USND("DMARDERR");
|
||||
goterr = 0;
|
||||
}
|
||||
if(i2cbuflen < 1) return;
|
||||
USND("DMARD=");
|
||||
hexdump16(USB_sendstr, (uint16_t*)I2Cbuf, i2cbuflen);
|
||||
}
|
||||
|
||||
// get DMA buffer with conversion to little-endian (if transfer was for 16-bit)
|
||||
uint16_t *i2c_dma_getbuf(uint16_t *len){
|
||||
//if(i2c_got_DMA) USND("DMA GOT!");
|
||||
//U("T="); U(u2str(Tms)); U("; cndtr: "); USND(u2str(DMA1_Channel7->CNDTR));
|
||||
if(!i2c_got_DMA || i2cbuflen < 1) return NULL;
|
||||
i2c_got_DMA = 0;
|
||||
i2cbuflen >>= 1; // for hexdump16 - now buffer have uint16_t!
|
||||
swapbytes((uint16_t*)I2Cbuf, i2cbuflen);
|
||||
if(len) *len = i2cbuflen;
|
||||
return I2Cbuf;
|
||||
}
|
||||
|
||||
int i2c_dma_haderr(){
|
||||
int r = goterr;
|
||||
goterr = 0;
|
||||
return r;
|
||||
}
|
||||
|
||||
int i2c_busy(){ return I2Cbusy;}
|
||||
|
||||
// Rx (7) /Tx (6) interrupts
|
||||
static void I2C_isr(int rx){
|
||||
uint32_t isr = DMA1->ISR;
|
||||
DMA_Channel_TypeDef *ch = (rx) ? DMA1_Channel7 : DMA1_Channel6;
|
||||
ch->CCR &= ~DMA_CCR_EN; // clear enable for further settings
|
||||
if(isr & (DMA_ISR_TEIF6 | DMA_ISR_TEIF7)){
|
||||
goterr = 1; goto ret;
|
||||
}
|
||||
if(dma_remain){ // receive/send next portion
|
||||
uint16_t len = (dma_remain > 255) ? 255 : dma_remain;
|
||||
ch->CNDTR = len;
|
||||
if(rx){
|
||||
if(!i2c_startr(dmaaddr, dma_remain, 0)){
|
||||
goterr = 1; goto ret;
|
||||
}
|
||||
ch->CMAR += 255;
|
||||
}
|
||||
dma_remain -= len;
|
||||
ch->CCR |= DMA_CCR_EN;
|
||||
DMA1->IFCR = DMA_IFCR_CTCIF6 | DMA_IFCR_CTCIF7;
|
||||
return;
|
||||
}else if(rx) i2c_got_DMA = 1; // last transfer was Rx and all data read
|
||||
ret:
|
||||
ch->CCR = 0;
|
||||
I2Cbusy = 0;
|
||||
DMA1->IFCR = 0x0ff00000; // clear all flags for channel6/7
|
||||
}
|
||||
|
||||
void dma1_channel6_isr(){
|
||||
I2C_isr(0);
|
||||
}
|
||||
|
||||
void dma1_channel7_isr(){
|
||||
I2C_isr(1);
|
||||
}
|
||||
Reference in New Issue
Block a user