I can't understand this shit with UART!

F0:F030,F042,F072/TSYS_controller/main.c

@@ -44,7 +44,7 @@ void sys_tick_handler(void){
     ++Tms;
 }
 
-#if 0
+#ifdef EBUG
 static void iwdg_setup(){
     /* Enable the peripheral clock RTC */
     /* (1) Enable the LSI (40kHz) */

F0:F030,F042,F072/TSYS_controller/proto.c

@@ -56,9 +56,20 @@ uint8_t noLED =
 void sendbuf(){
     IWDG->KR = IWDG_REFRESH;
     if(blen == 0) return;
+#ifdef EBUG
+    USB_send("  sendbuf()\n");
+#endif
     *bptr = 0;
     if(USBcmd) USB_send(buff);
-    else for(int i = 0; (i < 9999) && (LINE_BUSY == usart_send(buff, blen)); ++i){IWDG->KR = IWDG_REFRESH;}
+    else for(int i = 0; (i < WAITFOR) && (LINE_BUSY == usart_send(buff, blen)); ++i){
+#ifdef EBUG
+    USB_send("    line busy\n");
+#endif
+        IWDG->KR = IWDG_REFRESH;
+    }
+#ifdef EBUG
+    USB_send("  sendbuf() done\n");
+#endif
     bptr = buff;
     blen = 0;
 }
@@ -69,7 +80,7 @@ void addtobuf(const char *txt){
     if(l > UARTBUFSZ){
         sendbuf(); // send prevoius data in buffer
         if(USBcmd) USB_send(txt);
-        else for(int i = 0; (i < 9999) && (LINE_BUSY == usart_send_blocking(txt, l)); ++i){IWDG->KR = IWDG_REFRESH;}
+        else for(int i = 0; (i < WAITFOR) && (LINE_BUSY == usart_send_blocking(txt, l)); ++i){IWDG->KR = IWDG_REFRESH;}
     }else{
         if(blen+l > UARTBUFSZ){
             sendbuf();

F0:F030,F042,F072/TSYS_controller/sensors_manage.c

@@ -65,11 +65,11 @@ const char *sensors_get_statename(SensorsState x){
 
 // TODO: check if we can convert double to float!
 
-#ifndef EBUG
-#define TYPE double
-#else
+//#ifndef EBUG
+//#define TYPE double
+//#else
 #define TYPE float
-#endif
+//#endif
 
 const TYPE mul[5] = {-1.5e-2, 1., -2., 4., -2.};
 /**

F0:F030,F042,F072/TSYS_controller/usart.c

@@ -29,8 +29,6 @@
 #include "usb.h"
 #endif
 
-#define WAITFOR (72000000)
-
 extern volatile uint32_t Tms;
 static int datalen[2] = {0,0}; // received data line length (including '\n')
 
@@ -109,15 +107,6 @@ TXstatus usart_send_blocking(const char *str, int len){
 #endif
     return ALL_OK;
 }
-/*
-void usart_send_blck(const char *str){
-    while(!txrdy){IWDG->KR = IWDG_REFRESH;}
-    bufovr = 0;
-    while(*str){
-        USARTX -> TDR = *str++;
-        while(!(USARTX->ISR & USART_ISR_TXE)){IWDG->KR = IWDG_REFRESH;};
-    }
-}*/
 
 void usart_setup(){
 // Nucleo's USART2 connected to VCP proxy of st-link
@@ -133,7 +122,7 @@ void usart_setup(){
     DMA1_Channel4->CMAR = (uint32_t) tbuf; // mem
     DMA1_Channel4->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq
     // Tx CNDTR set @ each transmission due to data size
-    NVIC_SetPriority(DMA1_Channel4_5_IRQn, 3);
+    NVIC_SetPriority(DMA1_Channel4_5_IRQn, 0);
     NVIC_EnableIRQ(DMA1_Channel4_5_IRQn);
     NVIC_SetPriority(USART2_IRQn, 0);
     // setup usart2
@@ -159,7 +148,7 @@ void usart_setup(){
     DMA1_Channel2->CMAR = (uint32_t) tbuf; // mem
     DMA1_Channel2->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq
     // Tx CNDTR set @ each transmission due to data size
-    NVIC_SetPriority(DMA1_Channel2_3_IRQn, 3);
+    NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0);
     NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
     NVIC_SetPriority(USART1_IRQn, 0);
     // setup usart1

F0:F030,F042,F072/TSYS_controller/usart.h

@@ -31,6 +31,9 @@
 #define TIMEOUT_MS (1500)
 #endif
 
+// timeout for cycles
+#define WAITFOR (72000000)
+
 typedef enum{
     ALL_OK,
     LINE_BUSY,

F0:F030,F042,F072/TSYS_controller/usb_lib.c

@@ -30,6 +30,8 @@
 #ifdef EBUG
 #include "usart.h"
 #define MSG(x) do{usart_send(x, sizeof(x));}while(0)
+#else
+#define MSG(x)
 #endif
 
 

F0:F030,F042,F072/TSYS_controller/version.inc

@@ -1,3 +1,3 @@
-#define BUILD_NUMBER "80"
-#define BUILD_DATE "2023-09-12"
-#define BUILDNO 80
+#define BUILD_NUMBER "90"
+#define BUILD_DATE "2023-09-15"
+#define BUILDNO 91