diff --git a/F0:F030,F042,F072/usbcan_ringbuffer/Makefile b/F0:F030,F042,F072/usbcan_ringbuffer/Makefile index 3ecb35b..03d8a04 100644 --- a/F0:F030,F042,F072/usbcan_ringbuffer/Makefile +++ b/F0:F030,F042,F072/usbcan_ringbuffer/Makefile @@ -1,8 +1,8 @@ BINARY := usbcan # MCU code -MCU := F042x6 +MCU := F072xB # change this linking script depending on particular MCU model, -LDSCRIPT := stm32f042x6.ld +LDSCRIPT := stm32f072x8.ld DEFINES := -DUSB2_16 diff --git a/F0:F030,F042,F072/usbcan_ringbuffer/hardware.c b/F0:F030,F042,F072/usbcan_ringbuffer/hardware.c index d74ea6f..a71c422 100644 --- a/F0:F030,F042,F072/usbcan_ringbuffer/hardware.c +++ b/F0:F030,F042,F072/usbcan_ringbuffer/hardware.c @@ -21,13 +21,14 @@ uint8_t ledsON = 0; void gpio_setup(void){ - RCC->AHBENR |= RCC_AHBENR_GPIOBEN; - // Set LEDS (PB0/1) as output + RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN; + // Set LEDS (PB15/PA8) as output pin_set(LED0_port, LED0_pin); // clear LEDs pin_set(LED1_port, LED1_pin); - GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER0 | GPIO_MODER_MODER1) - ) | - GPIO_MODER_MODER0_O | GPIO_MODER_MODER1_O; + GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER15)) | + GPIO_MODER_MODER15_O; + GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER8)) | + GPIO_MODER_MODER8_O; } void iwdg_setup(){ @@ -53,12 +54,6 @@ void iwdg_setup(){ IWDG->KR = IWDG_REFRESH; /* (6) */ } -// pause in milliseconds for some purposes -void pause_ms(uint32_t pause){ - uint32_t Tnxt = Tms + pause; - while(Tms < Tnxt) nop(); -} - void Jump2Boot(){ void (*SysMemBootJump)(void); volatile uint32_t addr = 0x1FFFC800; diff --git a/F0:F030,F042,F072/usbcan_ringbuffer/hardware.h b/F0:F030,F042,F072/usbcan_ringbuffer/hardware.h index 69fbdb0..0c63074 100644 --- a/F0:F030,F042,F072/usbcan_ringbuffer/hardware.h +++ b/F0:F030,F042,F072/usbcan_ringbuffer/hardware.h @@ -27,28 +27,23 @@ #define FORMUSART(X) CONCAT(USART, X) #define USARTX FORMUSART(USARTNUM) -// LEDS: 0 - PB0, 1 - PB1 +// LEDS: 0 - PB15, 1 - PA8 // LED0 #define LED0_port GPIOB -#define LED0_pin (1<<0) +#define LED0_pin (1<<15) // LED1 -#define LED1_port GPIOB -#define LED1_pin (1<<1) +#define LED1_port GPIOA +#define LED1_pin (1<<8) #define LED_blink(x) do{if(ledsON) pin_toggle(x ## _port, x ## _pin);}while(0) #define LED_on(x) do{if(ledsON) pin_clear(x ## _port, x ## _pin);}while(0) #define LED_off(x) do{pin_set(x ## _port, x ## _pin);}while(0) -// CAN address - PB14(0), PB15(1), PA8(2) -#define READ_CAN_INV_ADDR() (((GPIOA->IDR & (1<<8))>>6)|((GPIOB->IDR & (3<<14))>>14)) - - extern volatile uint32_t Tms; extern uint8_t ledsON; void gpio_setup(void); void iwdg_setup(); -void pause_ms(uint32_t pause); void Jump2Boot(); diff --git a/F0:F030,F042,F072/usbcan_ringbuffer/openocd.cfg b/F0:F030,F042,F072/usbcan_ringbuffer/openocd.cfg new file mode 100644 index 0000000..4d268f6 --- /dev/null +++ b/F0:F030,F042,F072/usbcan_ringbuffer/openocd.cfg @@ -0,0 +1,96 @@ +# script for stm32f0x family + +# +# stm32 devices support SWD transports only. +# +source [find interface/stlink-v2-1.cfg] +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f0x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 4kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +# Allow overriding the Flash bank size +if { [info exists FLASH_SIZE] } { + set _FLASH_SIZE $FLASH_SIZE +} else { + # autodetect size + set _FLASH_SIZE 0 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0091 + # Section 29.5.3 + set _CPUTAPID 0x0bb11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME + +# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +adapter speed 1000 + +adapter srst delay 100 + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +proc stm32f0x_default_reset_start {} { + # Reset clock is HSI (8 MHz) + adapter speed 1000 +} + +proc stm32f0x_default_examine_end {} { + # Enable debug during low power modes (uses more power) + mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP + + # Stop watchdog counters during halt + mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP +} + +proc stm32f0x_default_reset_init {} { + # Configure PLL to boost clock to HSI x 6 (48 MHz) + mww 0x40021004 0x00100000 ;# RCC_CFGR = PLLMUL[2] + mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON + mww 0x40022000 0x00000011 ;# FLASH_ACR = PRFTBE | LATENCY[0] + sleep 10 ;# Wait for PLL to lock + mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1] + + # Boost JTAG frequency + adapter speed 8000 +} + +# Default hooks +$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end } +$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start } +$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init } diff --git a/F0:F030,F042,F072/usbcan_ringbuffer/usbcan.bin b/F0:F030,F042,F072/usbcan_ringbuffer/usbcan.bin index 2fd182c..f3cbb58 100755 Binary files a/F0:F030,F042,F072/usbcan_ringbuffer/usbcan.bin and b/F0:F030,F042,F072/usbcan_ringbuffer/usbcan.bin differ diff --git a/F0:F030,F042,F072/usbcan_ringbuffer/usbcanrb.creator.user b/F0:F030,F042,F072/usbcan_ringbuffer/usbcanrb.creator.user index 3f190b9..fc3798c 100644 --- a/F0:F030,F042,F072/usbcan_ringbuffer/usbcanrb.creator.user +++ b/F0:F030,F042,F072/usbcan_ringbuffer/usbcanrb.creator.user @@ -1,14 +1,14 @@ - + EnvironmentId - {7bd84e39-ca37-46d3-be9d-99ebea85bc0d} + {cf63021e-ef53-49b0-b03b-2f2570cdf3b6} ProjectExplorer.Project.ActiveTarget - 0 + 0 ProjectExplorer.Project.EditorSettings @@ -28,7 +28,7 @@ QmlJSGlobal - 2 + 2 KOI8-R false 4 @@ -37,23 +37,25 @@ true true 1 + 0 false - true + false false - 0 + 1 true true 0 8 true false - 1 + 2 true - false + true true *.md, *.MD, Makefile - false + true true + true @@ -74,7 +76,8 @@ true true Builtin.DefaultTidyAndClazy - 2 + 4 + false @@ -88,12 +91,12 @@ Desktop Desktop Desktop - {65a14f9e-e008-4c1b-89df-4eaa4774b6e3} - 0 - 0 - 0 + {91347f2c-5221-46a7-80b1-0a054ca02f79} + 0 + 0 + 0 - /Big/Data/00__Electronics/STM32/F0-nolib/usbcan_ringbuffer + /home/eddy/Docs/SAO/ELECTRONICS/STM32/F0-srcs/usbcan_ringbuffer @@ -102,7 +105,7 @@ true GenericProjectManager.GenericMakeStep - 1 + 1 Сборка Сборка ProjectExplorer.BuildSteps.Build @@ -115,7 +118,7 @@ true GenericProjectManager.GenericMakeStep - 1 + 1 Очистка Очистка ProjectExplorer.BuildSteps.Clean @@ -128,10 +131,10 @@ По умолчанию GenericProjectManager.GenericBuildConfiguration - 1 + 1 - 0 + 0 Развёртывание Развёртывание ProjectExplorer.BuildSteps.Deploy @@ -141,24 +144,29 @@ false ProjectExplorer.DefaultDeployConfiguration - 1 + 1 + true + true + true 2 + false + -e cpu-cycles --call-graph dwarf,4096 -F 250 + ProjectExplorer.CustomExecutableRunConfiguration - false + false true - false true - 1 + 1 ProjectExplorer.Project.TargetCount - 1 + 1 ProjectExplorer.Project.Updater.FileVersion