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https://github.com/eddyem/stm32samples.git
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add usart over DMA Rx/Tx for G070
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172
G0:G070/usart/usart.c
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172
G0:G070/usart/usart.c
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/*
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* This file is part of the usart project.
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* Copyright 2023 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stm32g0.h>
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#include <string.h>
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#include "usart.h"
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// RX/TX DMA->CCR without EN flag
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#define DMARXCCR (DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_TEIE)
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#define DMATXCCR (DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE | DMA_CCR_TEIE)
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static int txrdy = 1, rxrdy = 0; // transmission done, next line received
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static int bufovr = 0, wasbufovr = 0; // Rx buffer overflow or error flag -> delete next line
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static int rbufno = 0, tbufno = 0; // current buf number
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static char rbuf[2][UARTBUFSZ], tbuf[2][UARTBUFSZ]; // receive & transmit buffers
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static int rxlen[2] = {0}, txlen[2] = {0};
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char *usart3_getline(int *wasbo){
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if(wasbo) *wasbo = wasbufovr;
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wasbufovr = 0;
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if(!rxrdy) return NULL;
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rxrdy = 0; // clear ready flag
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return rbuf[!rbufno]; // current buffer is in filling stage, return old - filled - buffer
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}
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// USART3 @ PD8 (Tx) and PD9 (Rx) - both AF0
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void usart3_setup(){
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RCC->IOPENR |= RCC_IOPENR_GPIODEN; // enable PD
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RCC->AHBENR |= RCC_AHBENR_DMA1EN; // enable DMA1
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// set PD8 and PD9 as AF
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GPIOD->MODER = (GPIOD->MODER & ~(GPIO_MODER_MODE8 | GPIO_MODER_MODE9))
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| GPIO_MODER_MODER8_AF | GPIO_MODER_MODER9_AF;
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// AF0 for USART3 @ PD8/PD9
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GPIOD->AFR[1] = GPIOD->AFR[1] & ~(GPIO_AFRH_AFSEL8 | GPIO_AFRH_AFSEL9);
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// enable USART3 clocking
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RCC->APBENR1 |= RCC_APBENR1_USART3EN;
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// baudrate 115200
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USART3->BRR = 640000 / 1152;
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// eol character: '/n'
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USART3->CR2 = USART_CR2_ADD_VAL('\n');
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// enable DMA transmission
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USART3->CR3 = USART_CR3_DMAT | USART_CR3_DMAR;
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// set up DMA channels: 2 - Tx, 3 - Rx
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// Tx channel: mem++, mem->periph, 8bit, compl.&err. irq
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DMA1_Channel2->CCR = DMATXCCR;
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DMA1_Channel2->CPAR = (uint32_t) &USART3->TDR; // peripherial address
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// Rx channel: mem++, periph->mem, 8bit, compl.&err. irq
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DMA1_Channel3->CCR = DMARXCCR;
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DMA1_Channel3->CPAR = (uint32_t) &USART3->RDR; // peripherial address
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DMA1_Channel3->CNDTR = UARTBUFSZ;
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DMA1_Channel3->CMAR = (uint32_t)&rbuf[rbufno];
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// set up DMAMUX channels: 55 - USART3_TX, 54 - USART3_RX
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// enumeration of DMAMUX starts from 0 (DMA - from 1)!
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DMAMUX1_Channel1->CCR = 55;
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DMAMUX1_Channel2->CCR = 54;
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// charmatch interrupt, enable transmitter and receiver, enable usart
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USART3->CR1 = USART_CR1_CMIE | USART_CR1_TE | USART_CR1_RE | USART_CR1_UE;
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USART3->ICR = 0xffffffff; // clear all flags
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DMA1_Channel3->CCR = DMARXCCR | DMA_CCR_EN; // start receiving right now
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NVIC_EnableIRQ(USART3_4_IRQn);
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NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
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}
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static void mymemcpy(char *dest, const char *src, int len){
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while(len--) *dest++ = *src++;
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}
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int usart3_send(const char *str, int len){
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int rest = UARTBUFSZ - txlen[tbufno];
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if(rest == 0 && !txrdy) return 0; // buffer is full while transmission in process
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if(len < rest) rest = len;
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mymemcpy(tbuf[tbufno] + txlen[tbufno], str, rest);
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txlen[tbufno] += rest;
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if(!txrdy) return rest;
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if(txlen[tbufno] == UARTBUFSZ) usart3_sendbuf();
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if(rest == len) return len;
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len -= rest;
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// now fill another - empty - buffer
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if(len > UARTBUFSZ) len = UARTBUFSZ;
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mymemcpy(tbuf[tbufno], str + rest, len);
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txlen[tbufno] = len;
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return rest + len;
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}
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int usart3_sendstr(const char *str){
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int l = strlen(str);
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return usart3_send(str, l);
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}
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/**
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* @brief usart3_sendbuf - send current buffer
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*/
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void usart3_sendbuf(){
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if(!txrdy || txlen[tbufno] == 0) return;
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// set up DMA
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DMA1_Channel2->CCR = DMATXCCR;
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DMA1_Channel2->CMAR = (uint32_t)&tbuf[tbufno];
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DMA1_Channel2->CNDTR = txlen[tbufno];
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USART3->ICR = USART_ICR_TCCF; // clear TC flag
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txrdy = 0;
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// activate DMA
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DMA1_Channel2->CCR = DMATXCCR | DMA_CCR_EN;
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tbufno = !tbufno; // swap buffers
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txlen[tbufno] = 0;
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}
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// return amount of bytes sents
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int usart3_send_blocking(const char *str, int len){
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if(!txrdy) return 0;
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USART3->CR1 |= USART_CR1_TE;
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for(int i = 0; i < len; ++i){
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while(!(USART3->ISR & USART_ISR_TXE_TXFNF));
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USART3->TDR = *str++;
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}
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return len;
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}
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// interrupt by '\n'
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void usart3_4_isr(){
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if(USART3->ISR & USART_ISR_CMF){ // got '\n' @ USART3
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DMA1_Channel3->CCR = DMARXCCR;
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if(!bufovr){ // forget about broken line @ buffer overflow
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rxrdy = 1;
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int l = UARTBUFSZ - DMA1_Channel3->CNDTR - 1; // strlen
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rxlen[rbufno] = l;
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rbuf[rbufno][l] = 0;
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rbufno = !rbufno;
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}else{
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bufovr = 0;
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wasbufovr = 1;
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}
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// reload DMA Rx with next buffer
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DMA1_Channel3->CMAR = (uint32_t)&rbuf[rbufno];
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DMA1_Channel3->CNDTR = UARTBUFSZ;
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DMA1_Channel3->CCR = DMARXCCR | DMA_CCR_EN;
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}
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USART3->ICR = 0xffffffff; // clear all flags
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}
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// ch2 - Tx, ch3 - Rx
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void dma1_channel2_3_isr(){
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uint32_t isr = DMA1->ISR;
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if(isr & (DMA_ISR_TCIF2 | DMA_ISR_TEIF2)){ // transfer complete or error
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txrdy = 1;
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//DMA1_Channel2->CCR = DMATXCCR;
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}
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if(isr & (DMA_ISR_TCIF3 | DMA_ISR_TEIF3)){ // receive complete or error -> buffer overflow
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if(rbuf[rbufno][UARTBUFSZ-1] != '\n'){ // last symbol is not a newline
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bufovr = 1;
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DMA1_Channel3->CCR = DMARXCCR;
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DMA1_Channel3->CNDTR = UARTBUFSZ;
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DMA1_Channel3->CCR = DMARXCCR | DMA_CCR_EN;
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}
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}
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DMA1->IFCR = 0xffffffff; // clear all flags
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}
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