From 83080900bf6ea6194135a7501438a34be3b0ad6d Mon Sep 17 00:00:00 2001
From: Edward Emelianov <eddy@sao.ru>
Date: Sun, 3 Feb 2019 10:42:15 +0300
Subject: [PATCH] fix startHSI48

---
 F0-nolib/canbus/kicad/stm32.pro |  2 +-
 F0-nolib/inc/F0/stm32f0.h       | 23 +++++++++++------------
 F1-nolib/inc/ld/stm32f030f.ld   | 12 ++++++++++++
 3 files changed, 24 insertions(+), 13 deletions(-)
 create mode 100644 F1-nolib/inc/ld/stm32f030f.ld

diff --git a/F0-nolib/canbus/kicad/stm32.pro b/F0-nolib/canbus/kicad/stm32.pro
index 6c6ebd2..1aa9434 100644
--- a/F0-nolib/canbus/kicad/stm32.pro
+++ b/F0-nolib/canbus/kicad/stm32.pro
@@ -1,4 +1,4 @@
-update=Вс 06 янв 2019 17:11:01
+update=Ср 30 янв 2019 22:57:36
 version=1
 last_client=kicad
 [pcbnew]
diff --git a/F0-nolib/inc/F0/stm32f0.h b/F0-nolib/inc/F0/stm32f0.h
index b220ed9..763ccef 100644
--- a/F0-nolib/inc/F0/stm32f0.h
+++ b/F0-nolib/inc/F0/stm32f0.h
@@ -121,18 +121,17 @@ TRUE_INLINE void StartHSE(){
 
 #if !defined (STM32F030x4) && !defined (STM32F030x6) && !defined (STM32F030x8) && !defined (STM32F031x6) && !defined (STM32F038xx) && !defined (STM32F030xC)
 TRUE_INLINE void StartHSI48(){
-    // disable PLL
-    RCC->CR &= ~RCC_CR_PLLON;
-    RCC->CR2 &= RCC_CR2_HSI48ON; // turn on HSI48
-    while((RCC->CR2 & RCC_CR2_HSI48RDY) == 0);
-    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL));
-    // HSI48/2 * 2 = HSI48
-    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI48_PREDIV | RCC_CFGR_PLLMUL2);
-    RCC->CR |= RCC_CR_PLLON;
-    // select HSI48 as system clock source
-    RCC->CFGR &= ~RCC_CFGR_SW;
-    RCC->CFGR |= RCC_CFGR_SW_HSI48;
-    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI48){}
+    RCC->APB1ENR |= RCC_APB1ENR_CRSEN | RCC_APB1ENR_USBEN; // enable CRS (hsi48 sync) & USB
+    RCC->CFGR3 &= ~RCC_CFGR3_USBSW; // reset USB
+    RCC->CR2 |= RCC_CR2_HSI48ON; // turn ON HSI48
+    uint32_t tmout = 16000000;
+    while(!(RCC->CR2 & RCC_CR2_HSI48RDY)){if(--tmout == 0) break;}
+    FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
+    CRS->CFGR &= ~CRS_CFGR_SYNCSRC;
+    CRS->CFGR |= CRS_CFGR_SYNCSRC_1; // USB SOF selected as sync source
+    CRS->CR |= CRS_CR_AUTOTRIMEN; // enable auto trim
+    CRS->CR |= CRS_CR_CEN; // enable freq counter & block CRS->CFGR as read-only
+    RCC->CFGR |= RCC_CFGR_SW;
 }
 #endif
 
diff --git a/F1-nolib/inc/ld/stm32f030f.ld b/F1-nolib/inc/ld/stm32f030f.ld
new file mode 100644
index 0000000..ca27421
--- /dev/null
+++ b/F1-nolib/inc/ld/stm32f030f.ld
@@ -0,0 +1,12 @@
+/* Linker script for STM32F030f4, 16K flash, 4K RAM. */
+
+/* Define memory regions. */
+MEMORY
+{
+    rom   (rx) : ORIGIN = 0x08000000, LENGTH = 16K
+    ram  (rwx) : ORIGIN = 0x20000000, LENGTH = 4K
+}
+
+/* Include the common ld script. */
+INCLUDE stm32f01234.ld
+