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https://github.com/eddyem/stm32samples.git
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restructuring
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175
F1:F103/Tetris/hardware.c
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175
F1:F103/Tetris/hardware.c
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/*
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* This file is part of the TETRIS project.
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* Copyright 2021 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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#include "usb.h"
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uint8_t transfer_done = 0; // ==1 when DMA transfer ready
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// buffer for DMA
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static uint32_t dmabuf[SCREEN_WIDTH];
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void iwdg_setup(){
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uint32_t tmout = 16000000;
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/* Enable the peripheral clock RTC */
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/* (1) Enable the LSI (40kHz) */
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/* (2) Wait while it is not ready */
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RCC->CSR |= RCC_CSR_LSION; /* (1) */
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while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY){if(--tmout == 0) break;} /* (2) */
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/* Configure IWDG */
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/* (1) Activate IWDG (not needed if done in option bytes) */
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/* (2) Enable write access to IWDG registers */
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/* (3) Set prescaler by 64 (1.6ms for each tick) */
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/* (4) Set reload value to have a rollover each 2s */
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/* (5) Check if flags are reset */
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/* (6) Refresh counter */
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IWDG->KR = IWDG_START; /* (1) */
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IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
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IWDG->PR = IWDG_PR_PR_1; /* (3) */
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IWDG->RLR = 1250; /* (4) */
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tmout = 16000000;
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while(IWDG->SR){if(--tmout == 0) break;} /* (5) */
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IWDG->KR = IWDG_REFRESH; /* (6) */
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}
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static inline void gpio_setup(){
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// Enable clocks to the GPIO subsystems, turn on AFIO clocking to disable SWD/JTAG
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RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN;
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// turn off JTAG (PB3/4 is in use)
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AFIO->MAPR = AFIO_MAPR_SWJ_CFG_JTAGDISABLE;
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// turn off USB pullup
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USBPU_OFF();
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// Set led as opendrain output
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GPIOC->CRH = CRH(13, CNF_ODOUTPUT|MODE_SLOW);
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// SCREEN color PINs: PA0..PA5
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GPIOA->CRL = CRL(0, CNF_PPOUTPUT|MODE_FAST) | CRL(1, CNF_PPOUTPUT|MODE_FAST) | CRL(2, CNF_PPOUTPUT|MODE_FAST) |
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CRL(3, CNF_PPOUTPUT|MODE_FAST) | CRL(4, CNF_PPOUTPUT|MODE_FAST) | CRL(5, CNF_PPOUTPUT|MODE_FAST);
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// USB pullup - opendrain output
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GPIOA->CRH = CRH(15, CNF_PPOUTPUT|MODE_SLOW);
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// A..D, LAT
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GPIOB->CRL = CRL(4, CNF_PPOUTPUT|MODE_FAST) | CRL(5, CNF_PPOUTPUT|MODE_FAST) | CRL(6, CNF_PPOUTPUT|MODE_FAST) | CRL(7, CNF_PPOUTPUT|MODE_FAST);
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// nOE: PB4..PB9; Joystick: PB10..PB15 (pullup input)
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GPIOB->ODR = 0b111111 << 10; // pullup
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GPIOB->CRH = CRH(8, CNF_PPOUTPUT|MODE_FAST) | CRH(9, CNF_PPOUTPUT|MODE_FAST) |
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CRH(10, CNF_PUDINPUT|MODE_INPUT) | CRH(11, CNF_PUDINPUT|MODE_INPUT) | CRH(12, CNF_PUDINPUT|MODE_INPUT) |
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CRH(13, CNF_PUDINPUT|MODE_INPUT) | CRH(14, CNF_PUDINPUT|MODE_INPUT) | CRH(15, CNF_PUDINPUT|MODE_INPUT);
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}
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// setup timer3 for DMA transfers & SCK @ TIM3_CH1 (PA6)
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static inline void tim_setup(){
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SCRN_DISBL(); // turn off output
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GPIOA->CRL |= CRL(6, CNF_AFPP|MODE_FAST);
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RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;
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// PCS=1 don't work;
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TIM3->PSC = 4; // 7.2MHz
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TIM3->ARR = 7;
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TIM3->CCMR1 = TIM_CCMR1_OC1M; // PWM mode 2 (inactive->active)
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//TIM3->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; // PWM mode 1 (active->inactive)
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TIM3->CCER = TIM_CCER_CC1E; // output 1 enable
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TIM3->DIER = TIM_DIER_UDE; // enable DMA requests
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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// memsize 32bit, periphsize 32bit, memincr, mem2periph, full transfer interrupt
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DMA1_Channel3->CCR = DMA_CCR_PSIZE_1 | DMA_CCR_MSIZE_1 | DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE;
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DMA1_Channel3->CMAR = (uint32_t)dmabuf;
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DMA1_Channel3->CPAR = (uint32_t)&GPIOA->BSRR;
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NVIC_EnableIRQ(DMA1_Channel3_IRQn);
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}
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void hw_setup(){
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gpio_setup();
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tim_setup();
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}
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void stopTIMDMA(){
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DMA1_Channel3->CCR &= ~DMA_CCR_EN; // stop DMA
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TIM3->CR1 = 0; // turn off timer
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}
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static inline uint8_t getcolrvals(uint8_t colr, uint8_t Ntick){
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uint8_t result = 0; // bits: 0-R, 1-G, 2-B
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#ifdef SCREEN_IS_NEGATIVE
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if(colr >> 5 <= Ntick) result = 1;
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colr &= 0x1f;
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if(colr >> 2 <= Ntick) result |= 2;
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colr &= 3;
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if(colr) colr = (colr << 1) + 1;
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if(colr <= Ntick) result |= 4;
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#else
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if(colr >> 5 > Ntick) result = 1;
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colr &= 0x1f;
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if(colr >> 2 > Ntick) result |= 2;
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colr &= 3;
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if(colr) colr = (colr << 1) + 1;
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if(colr > Ntick) result |= 4;
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#endif
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return result;
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}
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/**
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* @brief ConvertScreenBuf - convert creen buffer into DMA buffer
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* @param sbuf - screen buffer
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* @param Nrow - current row number
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* @param Ntick - tick number (0..7) for quasi-PWM colors
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*/
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void ConvertScreenBuf(uint8_t *sbuf, uint8_t Nrow, uint8_t Ntick){ // __attribute__((unused))
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//USB_send("ConvertScreenBuf\n");
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uint8_t *_1st = &sbuf[SCREEN_WIDTH*Nrow], *_2nd = _1st + SCREEN_WIDTH*NBLOCKS; // first and second lines
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for(int i = 0; i < SCREEN_WIDTH; ++i){ // ~50us for 64 pixels
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uint8_t pinsset = getcolrvals(_1st[i], Ntick);
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pinsset |= getcolrvals(_2nd[i], Ntick) << 3;
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//dmabuf[i] = (i%2) ? ((COLR_pin<<16) | i) : (0b100010);
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dmabuf[i] = (COLR_pin << 16) | pinsset; // All BR are 1, BS depending on color
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}
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}
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static uint8_t blknum_curr = 0;
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/**
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* @brief TIM_DMA_transfer - start DMA transfer
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* @param buf - buffer with data for GPIOA->BSRR
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* @param blknum - number of active block
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*/
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void TIM_DMA_transfer(uint8_t blknum){
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//USB_send("TIM_DMA_transfer\n");
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TIM3->CR1 = 0; // turn off timer
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transfer_done = 0;
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// set first pixel color
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//COLR_port->BSRR = dmabuf[0];
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DMA1_Channel3->CNDTR = SCREEN_WIDTH;
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DMA1_Channel3->CCR |= DMA_CCR_EN; // start DMA
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TIM3->CCR1 = 4; // 50% PWM
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TIM3->CR1 = TIM_CR1_CEN; // turn on timer
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blknum_curr = blknum;
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}
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// DMA transfer complete - stop transfer
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void dma1_channel3_isr(){
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//TIM3->CR1 |= TIM_CR1_OPM; // set one pulse mode to turn off timer after last CLK pulse
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//TIM3->SR = 0;
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TIM3->CR1 = 0;
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DMA1_Channel3->CCR &= ~DMA_CCR_EN; // stop DMA
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//while(!(TIM3->SR & TIM_SR_UIF)); // wait for last pulse
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SCRN_DISBL(); // clear main output
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ADDR_port->ODR = (ADDR_port->ODR & ~(ADDR_pin)) | (blknum_curr << ADDR_roll); // set address
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SET(LAT); // activate latch
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DMA1->IFCR = DMA_IFCR_CGIF3;
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transfer_done = 1;
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CLEAR(LAT);
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SCRN_ENBL(); // activate main output
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process_screen();
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//USB_send("transfer done\n");
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}
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