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restructuring
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178
F0:F030,F042,F072/F0_testbrd/spi.c
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178
F0:F030,F042,F072/F0_testbrd/spi.c
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/*
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* This file is part of the F0testbrd project.
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* Copyright 2021 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "hardware.h"
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#include "proto.h"
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#include "spi.h"
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#include "usb.h"
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#include <string.h> // memcpy
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// buffers for DMA rx/tx
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static uint8_t inbuff[SPInumber][SPIBUFSZ], outbuf[SPInumber][SPIBUFSZ];
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volatile uint8_t SPIoverfl[SPInumber] = {0, 0};
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spiStatus SPI_status[SPInumber] = {SPI_NOTREADY, SPI_NOTREADY};
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static DMA_Channel_TypeDef * const rxDMA[SPInumber] = {DMA1_Channel2, DMA1_Channel4};
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static DMA_Channel_TypeDef * const txDMA[SPInumber] = {DMA1_Channel3, DMA1_Channel5};
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static const uint32_t txDMAirqn[SPInumber] = {DMA1_Channel2_3_IRQn, DMA1_Channel4_5_6_7_IRQn};
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static SPI_TypeDef * const SPI[SPInumber] = {SPI1, SPI2};
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// setup SPI by data from arrays above,
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// @param SPIidx - index in arrays
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// @param master - == 0 for slave
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static void spicommonsetup(uint8_t SPIidx, uint8_t master){
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if(SPIidx >= SPInumber) return;
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// Configure DMA SPI
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/* SPI_RX DMA config */
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/* (1) Peripheral address */
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/* (2) Memory address */
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/* (3) Data size */
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/* (4) Memory increment */
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/* Peripheral to memory */
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/* 8-bit transfer */
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/* Overflow IR */
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rxDMA[SPIidx]->CCR &= ~DMA_CCR_EN;
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rxDMA[SPIidx]->CPAR = (uint32_t)&(SPI[SPIidx]->DR); /* (1) */
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rxDMA[SPIidx]->CMAR = (uint32_t)inbuff[SPIidx]; /* (2) */
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rxDMA[SPIidx]->CNDTR = SPIBUFSZ; /* (3) */
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rxDMA[SPIidx]->CCR |= DMA_CCR_MINC | DMA_CCR_TEIE | DMA_CCR_EN; /* (4) */
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/* SPI_TX DMA config */
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/* (5) Peripheral address */
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/* (6) Memory address */
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/* (7) Memory increment */
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/* Memory to peripheral*/
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/* 8-bit transfer */
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/* Transfer complete IT */
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txDMA[SPIidx]->CCR &= ~DMA_CCR_EN;
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txDMA[SPIidx]->CPAR = (uint32_t)&(SPI[SPIidx]->DR); /* (5) */
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txDMA[SPIidx]->CMAR = (uint32_t)outbuf[SPIidx]; /* (6) */
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txDMA[SPIidx]->CCR |= DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_DIR; /* (7) */
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/* Configure IT */
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/* (8) Set priority */
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/* (9) Enable DMA */
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NVIC_SetPriority(txDMAirqn[SPIidx], 0);
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NVIC_EnableIRQ(txDMAirqn[SPIidx]);
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/* Configure SPI */
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/* (1) Master selection, BR: Fpclk/256 CPOL and CPHA at zero (rising first edge) */
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/* (1a) software slave management (SSI inactive) */
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/* (2) TX and RX with DMA, 8-bit Rx fifo */
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/* (3) Enable SPI */
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if(master) SPI[SPIidx]->CR1 = SPI_CR1_MSTR | SPI_CR1_BR | SPI_CR1_SSM | SPI_CR1_SSI; /* (1) */
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else SPI[SPIidx]->CR1 = SPI_CR1_SSM; // (1a)
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SPI[SPIidx]->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN | SPI_CR2_FRXTH | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (2) */
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SPI[SPIidx]->CR1 |= SPI_CR1_SPE; /* (3) */
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SPI_status[SPIidx] = SPI_READY;
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SPI_prep_receive(SPIidx);
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}
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// SPI1 (AF0): PB3 - SCK, PB4 - MISO, PB5 - MOSI; RxDMA - ch2, TxDMA - ch3
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// SPI2 (AF0): PB13 - SCK, PB14 - MISO, PB15 - MOSI; RxDMA - ch4, TxDMA - ch5
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void spi_setup(){
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// RCC->AHBENR |= RCC_AHBENR_GPIOBEN; // uncomment in common case
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/* (1) Select AF mode on pins */
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/* (2) AF0 for SPI1 signals */
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GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER3 | GPIO_MODER_MODER4 | GPIO_MODER_MODER5|
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GPIO_MODER_MODER13 | GPIO_MODER_MODER14 | GPIO_MODER_MODER15)) |
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GPIO_MODER_MODER3_AF | GPIO_MODER_MODER4_AF | GPIO_MODER_MODER5_AF |
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GPIO_MODER_MODER13_AF | GPIO_MODER_MODER14_AF | GPIO_MODER_MODER15_AF; /* (1) */
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GPIOB->AFR[0] = (GPIOB->AFR[0] & ~(GPIO_AFRL_AFRL3 | GPIO_AFRL_AFRL4 | GPIO_AFRL_AFRL5)); /* (2) */
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GPIOB->AFR[1] = (GPIOB->AFR[1] & ~(GPIO_AFRH_AFRH5 | GPIO_AFRH_AFRH6 | GPIO_AFRH_AFRH7)); /* (2) */
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// enable clocking
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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// SPI1 - master, SPI2 - slave
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spicommonsetup(0, 1);
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spicommonsetup(1, 0);
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}
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void spi_stop(){
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RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN;
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RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
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}
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/**
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* @brief SPI_transmit - transmit data over SPI DMA
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* @param N - SPI number (0 - SPI1, 1 - SPI2)
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* @param buf - data to transmit
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* @param len - its length
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* @return 0 if all OK
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*/
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uint8_t SPI_transmit(uint8_t N, const uint8_t *buf, uint8_t len){
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if(!buf || !len || len > SPIBUFSZ || N >= SPInumber) return 1; // bad data format
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if(SPI_status[N] != SPI_READY) return 2; // spi not ready to transmit data
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int ctr = 0;
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while(SPI[N]->SR & SPI_SR_FTLVL && ++ctr < 99999); // wait for transmission buffer empty
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ctr = 0;
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while(SPI[N]->SR & SPI_SR_BSY && ++ctr < 99999); // wait while busy
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USND("SPI->SR="); USB_sendstr(uhex2str(SPI[N]->SR)); USND("\n");
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txDMA[N]->CCR &=~ DMA_CCR_EN;
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memcpy(outbuf[N], buf, len);
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txDMA[N]->CNDTR = len;
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//txDMA[N]->CMAR = (uint32_t)outbuf[N];
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SPI_prep_receive(N);
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SPI_status[N] = SPI_BUSY;
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txDMA[N]->CCR |= DMA_CCR_EN;
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return 0;
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}
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// prepare channel N to receive data, return 0 if all OK
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uint8_t SPI_prep_receive(uint8_t N){
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if(N >= SPInumber) return 1;
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if(SPI_status[N] != SPI_READY) return 2; // still transmitting data
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SPIoverfl[N] = 0;
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rxDMA[N]->CCR &= ~DMA_CCR_EN;
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(void)SPI[N]->DR; // read DR and SR to clear OVR flag
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(void)SPI[N]->SR;
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rxDMA[N]->CNDTR = SPIBUFSZ;
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//rxDMA[N]->CMAR = (uint32_t)inbuff[N];
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rxDMA[N]->CCR |= DMA_CCR_EN;
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return 0;
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}
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/**
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* @brief SPI_getdata - get data received by DMA & reload receiver
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* @param N - number of channel (0/1)
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* @param buf - buffer for data (with length maxlen) or NULL
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* @param maxlen - (I) - amount of received bytes (or 0 if buffer is empty),
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* (O) - amount of real bytes amount in buffer (could be > maxlen if maxlen < SPIBUFSZ)
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* @return 0 if all OK or error code
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*/
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uint8_t SPI_getdata(uint8_t N, uint8_t *buf, uint8_t *maxlen){
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if(N >= SPInumber) return 1;
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if(SPI_status[N] != SPI_READY) return 2; // still transmitting data
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rxDMA[N]->CCR &= ~DMA_CCR_EN;
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SPIoverfl[N] = 0;
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uint8_t remain = rxDMA[N]->CNDTR;
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if(maxlen){
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if(buf && *maxlen) memcpy(buf, inbuff[N], *maxlen);
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*maxlen = SPIBUFSZ - remain; // bytes received
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}
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rxDMA[N]->CNDTR = SPIBUFSZ;
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rxDMA[N]->CCR |= DMA_CCR_EN;
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return 0;
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}
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// return 1 if given channel overflowed & clear overflow flag
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// should be called BEFORE SPI_prep_receive() or SPI_getdata()
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uint8_t SPI_isoverflow(uint8_t N){
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if(N >= SPInumber) return 1;
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register uint8_t o = SPIoverfl[N];
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SPIoverfl[N] = 0;
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return o;
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}
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