mirror of
https://github.com/eddyem/stm32samples.git
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rename G0:G070
This commit is contained in:
Edward Emelianov
233
G0:G070,G0B1/inc/startup/vector.c
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233
G0:G070,G0B1/inc/startup/vector.c
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>,
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* Copyright (C) 2012 chrysn <chrysn@fsfe.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "vector.h"
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typedef void (*vector_table_entry_t)(void);
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typedef void (*funcp_t) (void);
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void main(void);
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void blocking_handler(void);
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void null_handler(void);
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/* Initialization template for the interrupt vector table. This definition is
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* used by the startup code generator (vector.c) to set the initial values for
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* the interrupt handling routines to the chip family specific _isr weak
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* symbols. */
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#if defined STM32G0
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#include "stm32g0xx.h"
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#else
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#error "Not supported STM32 family"
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#endif
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#define NVIC_IRQ_COUNT 32
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#if defined(STM32G070xx)
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[WWDG_IRQn] = wwdg_isr, \
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[RTC_TAMP_IRQn] = rtc_isr, \
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[FLASH_IRQn] = flash_isr, \
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[RCC_IRQn] = rcc_isr, \
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[EXTI0_1_IRQn] = exti0_1_isr, \
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[EXTI2_3_IRQn] = exti2_3_isr, \
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[EXTI4_15_IRQn] = exti4_15_isr, \
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[DMA1_Channel1_IRQn] = dma1_channel1_isr, \
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[DMA1_Channel2_3_IRQn] = dma1_channel2_3_isr, \
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[DMA1_Ch4_7_DMAMUX1_OVR_IRQn] = dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr, \
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[ADC1_IRQn] = adc_comp_isr, \
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[TIM1_BRK_UP_TRG_COM_IRQn] = tim1_brk_up_trg_com_isr, \
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[TIM1_CC_IRQn] = tim1_cc_isr, \
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[TIM3_IRQn] = tim3_4_isr, \
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[TIM6_IRQn] = tim6_dac_lptim1_isr, \
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[TIM7_IRQn] = tim7_lptim2_isr, \
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[TIM14_IRQn] = tim14_isr, \
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[TIM15_IRQn] = tim15_isr, \
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[TIM16_IRQn] = tim16_fdcan_it0_isr, \
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[TIM17_IRQn] = tim17_fdcan_it1_isr, \
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[I2C1_IRQn] = i2c1_isr, \
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[I2C2_IRQn] = i2c2_3_isr, \
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[SPI1_IRQn] = spi1_isr, \
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[SPI2_IRQn] = spi2_3_isr, \
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[USART1_IRQn] = usart1_isr, \
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[USART2_IRQn] = usart2_lpuart2_isr, \
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[USART3_4_IRQn] = usart3_6_lpuart1_isr
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#elif defined(STM32G0B1xx)
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#define IRQ_HANDLERS \
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[WWDG_IRQn] = wwdg_isr, \
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[PVD_VDDIO2_IRQn] = pvd_vddio2_isr, \
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[RTC_TAMP_IRQn] = rtc_isr, \
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[FLASH_IRQn] = flash_isr, \
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[RCC_CRS_IRQn] = rcc_isr, \
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[EXTI0_1_IRQn] = exti0_1_isr, \
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[EXTI2_3_IRQn] = exti2_3_isr, \
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[EXTI4_15_IRQn] = exti4_15_isr, \
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[USB_UCPD1_2_IRQn] = usb_ucpd1_2_isr, \
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[DMA1_Channel1_IRQn] = dma1_channel1_isr, \
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[DMA1_Channel2_3_IRQn] = dma1_channel2_3_isr, \
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[DMA1_Ch4_7_DMA2_Ch1_5_DMAMUX1_OVR_IRQn] = dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr, \
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[ADC1_COMP_IRQn] = adc_comp_isr, \
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[TIM1_BRK_UP_TRG_COM_IRQn] = tim1_brk_up_trg_com_isr, \
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[TIM1_CC_IRQn] = tim1_cc_isr, \
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[TIM2_IRQn] = tim2_isr, \
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[TIM3_TIM4_IRQn] = tim3_4_isr, \
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[TIM6_DAC_LPTIM1_IRQn] = tim6_dac_lptim1_isr, \
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[TIM7_LPTIM2_IRQn] = tim7_lptim2_isr, \
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[TIM14_IRQn] = tim14_isr, \
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[TIM15_IRQn] = tim15_isr, \
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[TIM16_FDCAN_IT0_IRQn] = tim16_fdcan_it0_isr, \
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[TIM17_FDCAN_IT1_IRQn] = tim17_fdcan_it1_isr, \
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[I2C1_IRQn] = i2c1_isr, \
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[I2C2_3_IRQn] = i2c2_3_isr, \
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[SPI1_IRQn] = spi1_isr, \
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[SPI2_3_IRQn] = spi2_3_isr, \
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[USART1_IRQn] = usart1_isr, \
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[USART2_LPUART2_IRQn] = usart2_lpuart2_isr, \
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[USART3_4_5_6_LPUART1_IRQn] = usart3_6_lpuart1_isr, \
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[CEC_IRQn] = cec_isr
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#else
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#error "Not supported STM32G0 MCU"
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#endif
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typedef struct {
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unsigned int *initial_sp_value; /**< Initial stack pointer value. */
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vector_table_entry_t reset;
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vector_table_entry_t nmi;
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vector_table_entry_t hard_fault;
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vector_table_entry_t reserved1[7];
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vector_table_entry_t sv_call;
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vector_table_entry_t reserved2[2];
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vector_table_entry_t pend_sv;
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vector_table_entry_t systick;
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vector_table_entry_t irq[NVIC_IRQ_COUNT];
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} vector_table_t;
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extern unsigned _stack;
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vector_table_t vector_table __attribute__ ((used, section(".vector_table"))) = {
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.initial_sp_value = &_stack,
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.reset = reset_handler,
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.nmi = nmi_handler,
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.hard_fault = hard_fault_handler,
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.sv_call = sv_call_handler,
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.pend_sv = pend_sv_handler,
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.systick = sys_tick_handler,
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.irq = {
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IRQ_HANDLERS
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}
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};
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void WEAK __attribute__ ((naked)) __attribute__ ((noreturn)) reset_handler(void){
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extern char _sdata; // .data section start
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extern char _edata; // .data section end
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extern char _sbss; // .bss section start
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extern char _ebss; // .bss section end
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extern char _ldata; // .data load address
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char *dst = &_sdata;
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char *src = &_ldata;
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// copy initialized variables data
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while ( dst < &_edata ) { *dst++ = *src++; }
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// clear uninitialized variables
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for ( dst = &_sbss; dst < &_ebss; dst++ ) { *dst = 0; }
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// call main
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main();
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// halt
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for(;;) {}
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}
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void blocking_handler(void)
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{
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while (1);
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}
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void null_handler(void)
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{
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/* Do nothing. */
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}
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#pragma weak nmi_handler = null_handler
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#pragma weak hard_fault_handler = blocking_handler
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#pragma weak sv_call_handler = null_handler
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#pragma weak pend_sv_handler = null_handler
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#pragma weak sys_tick_handler = null_handler
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#if defined STM32G070xx
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#pragma weak wwdg_isr = blocking_handler
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#pragma weak rtc_isr = blocking_handler
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#pragma weak flash_isr = blocking_handler
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#pragma weak rcc_isr = blocking_handler
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#pragma weak exti0_1_isr = blocking_handler
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#pragma weak exti2_3_isr = blocking_handler
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#pragma weak exti4_15_isr = blocking_handler
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#pragma weak dma1_channel1_isr = blocking_handler
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#pragma weak dma1_channel2_3_isr = blocking_handler
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#pragma weak dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr = blocking_handler
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#pragma weak adc_comp_isr = blocking_handler
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#pragma weak tim1_brk_up_trg_com_isr = blocking_handler
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#pragma weak tim1_cc_isr = blocking_handler
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#pragma weak tim3_4_isr = blocking_handler
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#pragma weak tim6_dac_lptim1_isr = blocking_handler
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#pragma weak tim7_lptim2_isr = blocking_handler
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#pragma weak tim14_isr = blocking_handler
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#pragma weak tim15_isr = blocking_handler
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#pragma weak tim16_fdcan_it0_isr = blocking_handler
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#pragma weak tim17_fdcan_it1_isr = blocking_handler
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#pragma weak i2c1_isr = blocking_handler
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#pragma weak i2c2_3_isr = blocking_handler
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#pragma weak spi1_isr = blocking_handler
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#pragma weak spi2_3_isr = blocking_handler
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#pragma weak usart1_isr = blocking_handler
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#pragma weak usart2_lpuart2_isr = blocking_handler
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#pragma weak usart3_6_lpuart1_isr = blocking_handler
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#pragma weak cec_isr = blocking_handler
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#elif defined STM32G0B1xx
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#pragma weak wwdg_isr = blocking_handler
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#pragma weak pvd_vddio2_isr = blocking_handler
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#pragma weak rtc_isr = blocking_handler
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#pragma weak flash_isr = blocking_handler
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#pragma weak rcc_isr = blocking_handler
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#pragma weak exti0_1_isr = blocking_handler
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#pragma weak exti2_3_isr = blocking_handler
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#pragma weak exti4_15_isr = blocking_handler
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#pragma weak usb_ucpd1_2_isr = blocking_handler
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#pragma weak dma1_channel1_isr = blocking_handler
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#pragma weak dma1_channel2_3_isr = blocking_handler
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#pragma weak dma1_ch4_7_dma2_ch1_5_dmamux_ovr_isr = blocking_handler
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#pragma weak adc_comp_isr = blocking_handler
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#pragma weak tim1_brk_up_trg_com_isr = blocking_handler
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#pragma weak tim1_cc_isr = blocking_handler
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#pragma weak tim3_4_isr = blocking_handler
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#pragma weak tim6_dac_lptim1_isr = blocking_handler
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#pragma weak tim7_lptim2_isr = blocking_handler
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#pragma weak tim14_isr = blocking_handler
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#pragma weak tim15_isr = blocking_handler
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#pragma weak tim16_fdcan_it0_isr = blocking_handler
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#pragma weak tim17_fdcan_it1_isr = blocking_handler
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#pragma weak i2c1_isr = blocking_handler
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#pragma weak i2c2_3_isr = blocking_handler
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#pragma weak spi1_isr = blocking_handler
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#pragma weak spi2_3_isr = blocking_handler
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#pragma weak usart1_isr = blocking_handler
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#pragma weak usart2_lpuart2_isr = blocking_handler
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#pragma weak usart3_6_lpuart1_isr = blocking_handler
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#pragma weak cec_isr = blocking_handler
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#endif
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