From 6df3b9f5c2c98ffa21b9bcb5e4bd65231c7ab78d Mon Sep 17 00:00:00 2001 From: eddyem Date: Sat, 8 Sep 2018 19:51:02 +0300 Subject: [PATCH] add CDC for STM32F042 (not working yet) --- F0-nolib/Readme.md | 1 + F0-nolib/usbcdc/Makefile | 149 + F0-nolib/usbcdc/Readme.md | 5 + F0-nolib/usbcdc/can.c | 335 +++ F0-nolib/usbcdc/can.h | 56 + F0-nolib/usbcdc/canbus.c.tags | 4433 ++++++++++++++++++++++++++++++ F0-nolib/usbcdc/hardware.c | 43 + F0-nolib/usbcdc/hardware.h | 54 + F0-nolib/usbcdc/ld/stm32f042k.ld | 12 + F0-nolib/usbcdc/main.c | 157 ++ F0-nolib/usbcdc/usart.c | 252 ++ F0-nolib/usbcdc/usart.h | 63 + F0-nolib/usbcdc/usb.c | 144 + F0-nolib/usbcdc/usb.h | 32 + F0-nolib/usbcdc/usb_defs.h | 69 + F0-nolib/usbcdc/usb_lib.c | 499 ++++ F0-nolib/usbcdc/usb_lib.h | 130 + F0-nolib/usbcdc/usbcan.bin | Bin 0 -> 8660 bytes F1/2.8TFT/Makefile | 133 + F1/2.8TFT/README | 5 + F1/2.8TFT/cdcacm.c | 310 +++ F1/2.8TFT/cdcacm.h | 54 + F1/2.8TFT/dma_gpio.bin | Bin 0 -> 7680 bytes F1/2.8TFT/dmagpio.c | 74 + F1/2.8TFT/dmagpio.h | 32 + F1/2.8TFT/hardware_ini.c | 72 + F1/2.8TFT/hardware_ini.h | 95 + F1/2.8TFT/lcd.c | 433 +++ F1/2.8TFT/lcd.h | 68 + F1/2.8TFT/ld/devices.data | 9 + F1/2.8TFT/ld/stm32f103x4.ld | 31 + F1/2.8TFT/ld/stm32f103x6.ld | 31 + F1/2.8TFT/ld/stm32f103x8.ld | 31 + F1/2.8TFT/ld/stm32f103xB.ld | 31 + F1/2.8TFT/ld/stm32f103xC.ld | 31 + F1/2.8TFT/ld/stm32f103xD.ld | 31 + F1/2.8TFT/ld/stm32f103xE.ld | 31 + F1/2.8TFT/ld/stm32f103xF.ld | 31 + F1/2.8TFT/ld/stm32f103xG.ld | 31 + F1/2.8TFT/main.c | 128 + F1/2.8TFT/main.h | 53 + F1/2.8TFT/registers.h | 172 ++ F1/2.8TFT/sync.c | 93 + F1/2.8TFT/sync.h | 53 + F1/2.8TFT/user_proto.c | 93 + F1/2.8TFT/user_proto.h | 47 + 46 files changed, 8637 insertions(+) create mode 100644 F0-nolib/usbcdc/Makefile create mode 100644 F0-nolib/usbcdc/Readme.md create mode 100644 F0-nolib/usbcdc/can.c create mode 100644 F0-nolib/usbcdc/can.h create mode 100644 F0-nolib/usbcdc/canbus.c.tags create mode 100644 F0-nolib/usbcdc/hardware.c create mode 100644 F0-nolib/usbcdc/hardware.h create mode 100644 F0-nolib/usbcdc/ld/stm32f042k.ld create mode 100644 F0-nolib/usbcdc/main.c create mode 100644 F0-nolib/usbcdc/usart.c create mode 100644 F0-nolib/usbcdc/usart.h create mode 100644 F0-nolib/usbcdc/usb.c create mode 100644 F0-nolib/usbcdc/usb.h create mode 100644 F0-nolib/usbcdc/usb_defs.h create mode 100644 F0-nolib/usbcdc/usb_lib.c create mode 100644 F0-nolib/usbcdc/usb_lib.h create mode 100755 F0-nolib/usbcdc/usbcan.bin create mode 100644 F1/2.8TFT/Makefile create mode 100644 F1/2.8TFT/README create mode 100644 F1/2.8TFT/cdcacm.c create mode 100644 F1/2.8TFT/cdcacm.h create mode 100755 F1/2.8TFT/dma_gpio.bin create mode 100644 F1/2.8TFT/dmagpio.c create mode 100644 F1/2.8TFT/dmagpio.h create mode 100644 F1/2.8TFT/hardware_ini.c create mode 100644 F1/2.8TFT/hardware_ini.h create mode 100644 F1/2.8TFT/lcd.c create mode 100644 F1/2.8TFT/lcd.h create mode 100644 F1/2.8TFT/ld/devices.data create mode 100644 F1/2.8TFT/ld/stm32f103x4.ld create mode 100644 F1/2.8TFT/ld/stm32f103x6.ld create mode 100644 F1/2.8TFT/ld/stm32f103x8.ld create mode 100644 F1/2.8TFT/ld/stm32f103xB.ld create mode 100644 F1/2.8TFT/ld/stm32f103xC.ld create mode 100644 F1/2.8TFT/ld/stm32f103xD.ld create mode 100644 F1/2.8TFT/ld/stm32f103xE.ld create mode 100644 F1/2.8TFT/ld/stm32f103xF.ld create mode 100644 F1/2.8TFT/ld/stm32f103xG.ld create mode 100644 F1/2.8TFT/main.c create mode 100644 F1/2.8TFT/main.h create mode 100644 F1/2.8TFT/registers.h create mode 100644 F1/2.8TFT/sync.c create mode 100644 F1/2.8TFT/sync.h create mode 100644 F1/2.8TFT/user_proto.c create mode 100644 F1/2.8TFT/user_proto.h diff --git a/F0-nolib/Readme.md b/F0-nolib/Readme.md index a11fbb4..68f98f2 100644 --- a/F0-nolib/Readme.md +++ b/F0-nolib/Readme.md @@ -11,3 +11,4 @@ This directory contains examples for F0 without any library - uart - USART over DMA with hardware end-of-string detection - uart_blink - code for STM32F030F4, echo data on USART1 and blink LEDS on PA4 and PA5 - uart_nucleo - USART over DMA for STM32F042-nucleo +- usbcdc - CDC for STM32F042 (emulation of ch340) diff --git a/F0-nolib/usbcdc/Makefile b/F0-nolib/usbcdc/Makefile new file mode 100644 index 0000000..e1c0cfb --- /dev/null +++ b/F0-nolib/usbcdc/Makefile @@ -0,0 +1,149 @@ +BINARY = usbcan +BOOTPORT ?= /dev/ttyUSB0 +BOOTSPEED ?= 57600 +# MCU FAMILY +FAMILY = F0 +# MCU code +MCU = F042x6 +# hardware definitions +DEFS += -DUSARTNUM=1 +#DEFS += -DCHECK_TMOUT +DEFS += -DEBUG +# change this linking script depending on particular MCU model, +# for example, if you have STM32F103VBT6, you should write: +LDSCRIPT = ld/stm32f042k.ld + +INDEPENDENT_HEADERS= + +FP_FLAGS ?= -msoft-float +ASM_FLAGS = -mthumb -mcpu=cortex-m0 -march=armv6-m -mtune=cortex-m0 +ARCH_FLAGS = $(ASM_FLAGS) $(FP_FLAGS) + +############################################################################### +# Executables +OPREFIX ?= /opt/bin/arm-none-eabi +#PREFIX ?= /usr/x86_64-pc-linux-gnu/arm-none-eabi/gcc-bin/7.3.0/arm-none-eabi +PREFIX ?= $(OPREFIX) + +RM := rm -f +RMDIR := rmdir +CC := $(PREFIX)-gcc +LD := $(PREFIX)-gcc +AR := $(PREFIX)-ar +AS := $(PREFIX)-as +OBJCOPY := $(OPREFIX)-objcopy +OBJDUMP := $(OPREFIX)-objdump +GDB := $(OPREFIX)-gdb +STFLASH := $(shell which st-flash) +STBOOT := $(shell which stm32flash) +DFUUTIL := $(shell which dfu-util) + +############################################################################### +# Source files +OBJDIR = mk +LDSCRIPT ?= $(BINARY).ld +SRC := $(wildcard *.c) +OBJS := $(addprefix $(OBJDIR)/, $(SRC:%.c=%.o)) +STARTUP = $(OBJDIR)/startup.o +OBJS += $(STARTUP) +DEPS := $(OBJS:.o=.d) + +INC_DIR ?= ../inc + +INCLUDE := -I$(INC_DIR)/F0 -I$(INC_DIR)/cm +LIB_DIR := $(INC_DIR)/ld + +############################################################################### +# C flags +CFLAGS += -O2 -g -MD -D__thumb2__=1 +CFLAGS += -Wall -Werror -Wextra -Wshadow -Wimplicit-function-declaration +CFLAGS += -Wredundant-decls $(INCLUDE) +# -Wmissing-prototypes -Wstrict-prototypes +CFLAGS += -fno-common -ffunction-sections -fdata-sections + +############################################################################### +# Linker flags +LDFLAGS += --static -nostartfiles +#--specs=nano.specs +LDFLAGS += -L$(LIB_DIR) +LDFLAGS += -T$(LDSCRIPT) +LDFLAGS += -Wl,-Map=$(OBJDIR)/$(BINARY).map +LDFLAGS += -Wl,--gc-sections + +############################################################################### +# Used libraries +LDLIBS += -Wl,--start-group -lc -lgcc -Wl,--end-group +LDLIBS += $(shell $(CC) $(CFLAGS) -print-libgcc-file-name) + +DEFS += -DSTM32$(FAMILY) -DSTM32$(MCU) + +#.SUFFIXES: .elf .bin .hex .srec .list .map .images +#.SECONDEXPANSION: +#.SECONDARY: + +ELF := $(OBJDIR)/$(BINARY).elf +LIST := $(OBJDIR)/$(BINARY).list +BIN := $(BINARY).bin +HEX := $(BINARY).hex + +all: bin list + +elf: $(ELF) +bin: $(BIN) +hex: $(HEX) +list: $(LIST) + +ifneq ($(MAKECMDGOALS),clean) +-include $(DEPS) +endif + +$(OBJDIR): + mkdir $(OBJDIR) + +$(STARTUP): $(INC_DIR)/startup/vector.c + $(CC) $(CFLAGS) $(DEFS) $(INCLUDE) $(ARCH_FLAGS) -o $@ -c $< + +$(OBJDIR)/%.o: %.c + @echo " CC $<" + $(CC) $(CFLAGS) $(DEFS) $(INCLUDE) $(ARCH_FLAGS) -o $@ -c $< + +#$(OBJDIR)/%.d: %.c $(OBJDIR) +# $(CC) -MM -MG $< | sed -e 's,^\([^:]*\)\.o[ ]*:,$(@D)/\1.o $(@D)/\1.d:,' >$@ + +$(BIN): $(ELF) + @echo " OBJCOPY $(BIN)" + $(OBJCOPY) -Obinary $(ELF) $(BIN) + +$(HEX): $(ELF) + @echo " OBJCOPY $(HEX)" + $(OBJCOPY) -Oihex $(ELF) $(HEX) + +$(LIST): $(ELF) + @echo " OBJDUMP $(LIST)" + $(OBJDUMP) -S $(ELF) > $(LIST) + +$(ELF): $(OBJDIR) $(OBJS) + @echo " LD $(ELF)" + $(LD) $(LDFLAGS) $(ARCH_FLAGS) $(OBJS) $(LDLIBS) -o $(ELF) + +clean: + @echo " CLEAN" + $(RM) $(OBJS) $(DEPS) $(ELF) $(HEX) $(LIST) $(OBJDIR)/*.map *.d + @rmdir $(OBJDIR) 2>/dev/null || true + +dfuboot: $(BIN) + @echo " LOAD $(BIN) THROUGH DFU" + $(DFUUTIL) -a0 -D $(BIN) -s 0x08000000 + +flash: $(BIN) + @echo " FLASH $(BIN)" + $(STFLASH) write $(BIN) 0x8000000 + +boot: $(BIN) + @echo " LOAD $(BIN) through bootloader" + $(STBOOT) -b$(BOOTSPEED) $(BOOTPORT) -w $(BIN) + +gentags: + CFLAGS="$(CFLAGS) $(DEFS)" geany -g $(BINARY).c.tags *[hc] 2>/dev/null + +.PHONY: clean flash boot gentags diff --git a/F0-nolib/usbcdc/Readme.md b/F0-nolib/usbcdc/Readme.md new file mode 100644 index 0000000..42c2d9b --- /dev/null +++ b/F0-nolib/usbcdc/Readme.md @@ -0,0 +1,5 @@ +Simple code for CAN/USB development board + + + +USB: https://github.com/majbthrd/CDCHIDwidget/blob/master/src/main.c \ No newline at end of file diff --git a/F0-nolib/usbcdc/can.c b/F0-nolib/usbcdc/can.c new file mode 100644 index 0000000..9f8b508 --- /dev/null +++ b/F0-nolib/usbcdc/can.c @@ -0,0 +1,335 @@ +/* + * geany_encoding=koi8-r + * can.c + * + * Copyright 2018 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ +#include // memcpy +#include "can.h" +#include "hardware.h" +#include "usart.h" + +#define CMD_TOGGLE (0xDA) +#define CMD_BCAST (0xAD) +#define CAN_ID_MASK (0x7F8) +#define CAN_ID_PREFIX (0xAAA) +#define TARG_ID (CAN_ID_PREFIX & CAN_ID_MASK) +#define BCAST_ID (0x7F7) + +#define CAN_FLAG_GOTDUMMY (1) +// incoming message buffer size +#define CAN_INMESSAGE_SIZE (6) + +extern volatile uint32_t Tms; + +// circular buffer for received messages +static CAN_message messages[CAN_INMESSAGE_SIZE]; +static uint8_t first_free_idx = 0; // index of first empty cell +static int8_t first_nonfree_idx = -1; // index of first data cell + +static uint16_t CANID = 0xFFFF; +static uint32_t last_err_code = 0; +static CAN_status can_status = CAN_STOP; + +static void can_process_fifo(uint8_t fifo_num); + +CAN_status CAN_get_status(){ + CAN_status st = can_status; + // give overrun message only once + if(st == CAN_FIFO_OVERRUN) can_status = CAN_READY; + return st; +} + +// push next message into buffer; return 1 if buffer overfull +static int CAN_messagebuf_push(CAN_message *msg){ + MSG("Try to push\n"); + if(first_free_idx == first_nonfree_idx) return 1; // no free space + if(first_nonfree_idx < 0) first_nonfree_idx = 0; // first message in empty buffer + memcpy(&messages[first_free_idx++], msg, sizeof(CAN_message)); + // need to roll? + if(first_free_idx == CAN_INMESSAGE_SIZE) first_free_idx = 0; + #ifdef EBUG + MSG("1st free: "); usart_putchar('0' + first_free_idx); newline(); + #endif + return 0; +} + +// pop message from buffer +CAN_message *CAN_messagebuf_pop(){ + if(first_nonfree_idx < 0) return NULL; + #ifdef EBUG + MSG("read from idx "); usart_putchar('0' + first_nonfree_idx); newline(); + #endif + CAN_message *msg = &messages[first_nonfree_idx++]; + if(first_nonfree_idx == CAN_INMESSAGE_SIZE) first_nonfree_idx = 0; + if(first_nonfree_idx == first_free_idx){ // buffer is empty - refresh it + first_nonfree_idx = -1; + first_free_idx = 0; + MSG("refresh buffer\n"); + } + return msg; +} + +// get CAN address data from GPIO pins +void readCANID(){ + uint8_t CAN_addr = READ_CAN_INV_ADDR(); + CAN_addr = ~CAN_addr & 0x7; + CANID = (CAN_ID_PREFIX & CAN_ID_MASK) | CAN_addr; +} + +uint16_t getCANID(){ + return CANID; +} + +void CAN_reinit(){ + readCANID(); + CAN->TSR |= CAN_TSR_ABRQ0 | CAN_TSR_ABRQ1 | CAN_TSR_ABRQ2; + RCC->APB1RSTR |= RCC_APB1RSTR_CANRST; + RCC->APB1RSTR &= ~RCC_APB1RSTR_CANRST; + CAN_setup(); +} + +void CAN_setup(){ + if(CANID == 0xFFFF) readCANID(); + // Configure GPIO: PB8 - CAN_Rx, PB9 - CAN_Tx + /* (1) Select AF mode (10) on PB8 and PB9 */ + /* (2) AF4 for CAN signals */ + GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER8 | GPIO_MODER_MODER9)) + | (GPIO_MODER_MODER8_AF | GPIO_MODER_MODER9_AF); /* (1) */ + GPIOB->AFR[1] = (GPIOB->AFR[1] &~ (GPIO_AFRH_AFRH0 | GPIO_AFRH_AFRH1))\ + | (4 << (0 * 4)) | (4 << (1 * 4)); /* (2) */ + /* Enable the peripheral clock CAN */ + RCC->APB1ENR |= RCC_APB1ENR_CANEN; + /* Configure CAN */ + /* (1) Enter CAN init mode to write the configuration */ + /* (2) Wait the init mode entering */ + /* (3) Exit sleep mode */ + /* (4) Loopback mode, set timing to 100kb/s: BS1 = 4, BS2 = 3, prescaler = 60 */ + /* (5) Leave init mode */ + /* (6) Wait the init mode leaving */ + /* (7) Enter filter init mode, (16-bit + mask, filter 0 for FIFO 0) */ + /* (8) Acivate filter 0 for two IDs */ + /* (9) Identifier list mode */ + /* (10) Set the Id list */ + /* (12) Leave filter init */ + /* (13) Set error interrupts enable */ + CAN->MCR |= CAN_MCR_INRQ; /* (1) */ + while((CAN->MSR & CAN_MSR_INAK)!=CAN_MSR_INAK) /* (2) */ + { + /* add time out here for a robust application */ + } + CAN->MCR &=~ CAN_MCR_SLEEP; /* (3) */ + CAN->MCR |= CAN_MCR_ABOM; + + CAN->BTR |= 2 << 20 | 3 << 16 | 59 << 0; /* (4) */ + CAN->MCR &=~ CAN_MCR_INRQ; /* (5) */ + while((CAN->MSR & CAN_MSR_INAK)==CAN_MSR_INAK) /* (6) */ + { + /* add time out here for a robust application */ + } + CAN->FMR = CAN_FMR_FINIT; /* (7) */ + CAN->FA1R = CAN_FA1R_FACT0; /* (8) */ + CAN->FM1R = CAN_FM1R_FBM0; /* (9) */ + CAN->sFilterRegister[0].FR1 = CANID << 5 | ((BCAST_ID << 5) << 16); /* (10) */ + + CAN->FMR &=~ CAN_FMR_FINIT; /* (12) */ + CAN->IER |= CAN_IER_ERRIE | CAN_IER_FOVIE0 | CAN_IER_FOVIE1; /* (13) */ + + /* Configure IT */ + /* (14) Set priority for CAN_IRQn */ + /* (15) Enable CAN_IRQn */ + NVIC_SetPriority(CEC_CAN_IRQn, 0); /* (14) */ + NVIC_EnableIRQ(CEC_CAN_IRQn); /* (15) */ + can_status = CAN_READY; +} + +void can_proc(){ + if(last_err_code){ +#ifdef EBUG + MSG("Error, ESR="); + printu(last_err_code); + newline(); +#endif + last_err_code = 0; + } + // check for messages in FIFO0 & FIFO1 + if(CAN->RF0R & CAN_RF0R_FMP0){ + can_process_fifo(0); + } + if(CAN->RF1R & CAN_RF1R_FMP1){ + can_process_fifo(1); + } + if(CAN->ESR & (CAN_ESR_BOFF | CAN_ESR_EPVF | CAN_ESR_EWGF)){ // much errors - restart CAN BUS + MSG("bus-off, restarting\n"); + // request abort for all mailboxes + CAN->TSR |= CAN_TSR_ABRQ0 | CAN_TSR_ABRQ1 | CAN_TSR_ABRQ2; + // reset CAN bus + RCC->APB1RSTR |= RCC_APB1RSTR_CANRST; + RCC->APB1RSTR &= ~RCC_APB1RSTR_CANRST; + CAN_setup(); + } + LED_off(LED1); +#ifdef EBUG + static uint32_t esr, msr, tsr; + uint32_t msr_now = CAN->MSR & 0xf; + if(esr != CAN->ESR || msr != msr_now || tsr != CAN->TSR){ + MSG("Timestamp: "); + printu(Tms); + newline(); + } + if((CAN->ESR) != esr){ + usart_putchar(((CAN->ESR & CAN_ESR_BOFF) != 0) + '0'); + esr = CAN->ESR; + MSG("CAN->ESR: "); + printuhex(esr); newline(); + } + if(msr_now != msr){ + msr = msr_now; + MSG("CAN->MSR & 0xf: "); + printuhex(msr); newline(); + } + if(CAN->TSR != tsr){ + tsr = CAN->TSR; + MSG("CAN->TSR: "); + printuhex(tsr); newline(); + } +#endif +} + +CAN_status can_send(uint8_t *msg, uint8_t len, uint16_t target_id){ + uint8_t mailbox = 0; + // check first free mailbox + if(CAN->TSR & (CAN_TSR_TME)){ + mailbox = (CAN->TSR & CAN_TSR_CODE) >> 24; + #ifdef EBUG + MSG("select "); usart_putchar('0'+mailbox); SEND(" mailbox\n"); + #endif + }else{ // no free mailboxes + return CAN_BUSY; + } + CAN_TxMailBox_TypeDef *box = &CAN->sTxMailBox[mailbox]; + uint32_t lb = 0, hb = 0; + switch(len){ + case 8: + hb |= (uint32_t)msg[7] << 24; + case 7: + hb |= (uint32_t)msg[6] << 16; + case 6: + hb |= (uint32_t)msg[5] << 8; + case 5: + hb |= (uint32_t)msg[4]; + case 4: + lb |= (uint32_t)msg[3] << 24; + case 3: + lb |= (uint32_t)msg[2] << 16; + case 2: + lb |= (uint32_t)msg[1] << 8; + default: + lb |= (uint32_t)msg[0]; + } + box->TDLR = lb; + box->TDHR = hb; + box->TDTR = len; + box->TIR = (target_id & 0x7FF) << 21 | CAN_TI0R_TXRQ; + return CAN_OK; +} + +void can_send_dummy(){ + uint8_t msg = CMD_TOGGLE; + if(CAN_OK != can_send(&msg, 1, TARG_ID)) SEND("Bus busy!\n"); + MSG("CAN->MSR: "); + printuhex(CAN->MSR); newline(); + MSG("CAN->TSR: "); + printuhex(CAN->TSR); newline(); + MSG("CAN->ESR: "); + printuhex(CAN->ESR); newline(); +} + +void can_send_broadcast(){ + uint8_t msg = CMD_BCAST; + if(CAN_OK != can_send(&msg, 1, BCAST_ID)) SEND("Bus busy!\n"); + MSG("Broadcast message sent\n"); +} + +static void can_process_fifo(uint8_t fifo_num){ + if(fifo_num > 1) return; + LED_on(LED1); // Toggle LED1 + CAN_FIFOMailBox_TypeDef *box = &CAN->sFIFOMailBox[fifo_num]; + volatile uint32_t *RFxR = (fifo_num) ? &CAN->RF1R : &CAN->RF0R; + MSG("Receive, RDTR="); + #ifdef EBUG + printuhex(box->RDTR); + newline(); + #endif + // read all + while(*RFxR & CAN_RF0R_FMP0){ // amount of messages pending + // CAN_RDTxR: (16-31) - timestamp, (8-15) - filter match index, (0-3) - data length + /* TODO: check filter match index if more than one ID can receive */ + CAN_message msg; + uint8_t *dat = msg.data; + uint8_t len = box->RDTR & 0x7; + msg.length = len; + if(len){ // message can be without data + uint32_t hb = box->RDHR, lb = box->RDLR; + switch(len){ + case 8: + dat[7] = hb>>24; + case 7: + dat[6] = (hb>>16) & 0xff; + case 6: + dat[5] = (hb>>8) & 0xff; + case 5: + dat[4] = hb & 0xff; + case 4: + dat[3] = lb>>24; + case 3: + dat[2] = (lb>>16) & 0xff; + case 2: + dat[1] = (lb>>8) & 0xff; + case 1: + dat[0] = lb & 0xff; + } + } + if(CAN_messagebuf_push(&msg)) return; // error: buffer is full, try later + *RFxR |= CAN_RF0R_RFOM0; // release fifo for access to next message + } + if(*RFxR & CAN_RF0R_FULL0) *RFxR &= ~CAN_RF0R_FULL0; +} + +void cec_can_isr(){ + if(CAN->RF0R & CAN_RF0R_FOVR0){ // FIFO overrun + CAN->RF0R &= ~CAN_RF0R_FOVR0; + can_status = CAN_FIFO_OVERRUN; + } + if(CAN->RF1R & CAN_RF1R_FOVR1){ + CAN->RF1R &= ~CAN_RF1R_FOVR1; + can_status = CAN_FIFO_OVERRUN; + } + #ifdef EBUG + if(can_status == CAN_FIFO_OVERRUN) MSG("fifo 0 overrun\n"); + #endif + if(CAN->MSR & CAN_MSR_ERRI){ // Error + CAN->MSR &= ~CAN_MSR_ERRI; + // request abort for problem mailbox + if(CAN->TSR & CAN_TSR_TERR0) CAN->TSR |= CAN_TSR_ABRQ0; + if(CAN->TSR & CAN_TSR_TERR1) CAN->TSR |= CAN_TSR_ABRQ1; + if(CAN->TSR & CAN_TSR_TERR2) CAN->TSR |= CAN_TSR_ABRQ2; + last_err_code = CAN->ESR; + } +} diff --git a/F0-nolib/usbcdc/can.h b/F0-nolib/usbcdc/can.h new file mode 100644 index 0000000..9759c8f --- /dev/null +++ b/F0-nolib/usbcdc/can.h @@ -0,0 +1,56 @@ +/* + * geany_encoding=koi8-r + * can.h + * + * Copyright 2018 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ +#pragma once +#ifndef __CAN_H__ +#define __CAN_H__ + +#include "hardware.h" + +typedef struct{ + uint8_t data[8]; + uint8_t length; +} CAN_message; + +typedef enum{ + CAN_STOP, + CAN_READY, + CAN_BUSY, + CAN_OK, + CAN_FIFO_OVERRUN +} CAN_status; + +CAN_status CAN_get_status(); + +void readCANID(); +uint16_t getCANID(); + +void CAN_reinit(); +void CAN_setup(); + +void can_send_dummy(); +void can_send_broadcast(); +void can_proc(); + +CAN_message *CAN_messagebuf_pop(); + +#endif // __CAN_H__ diff --git a/F0-nolib/usbcdc/canbus.c.tags b/F0-nolib/usbcdc/canbus.c.tags new file mode 100644 index 0000000..5bd97c6 --- /dev/null +++ b/F0-nolib/usbcdc/canbus.c.tags @@ -0,0 +1,4433 @@ +# format=tagmanager +ADC655360 +ADC1655360 +ADC1_BASE655360 +ADC1_COMP_IRQHandler655360 +ADC1_COMP_IRQn655360 +ADC_BASE655360 +ADC_CCR_TSEN655360 +ADC_CCR_VBATEN655360 +ADC_CCR_VREFEN655360 +ADC_CFGR1_ALIGN655360 +ADC_CFGR1_AUTDLY655360 +ADC_CFGR1_AUTOFF655360 +ADC_CFGR1_AWDCH655360 +ADC_CFGR1_AWDCH_0655360 +ADC_CFGR1_AWDCH_1655360 +ADC_CFGR1_AWDCH_2655360 +ADC_CFGR1_AWDCH_3655360 +ADC_CFGR1_AWDCH_4655360 +ADC_CFGR1_AWDEN655360 +ADC_CFGR1_AWDSGL655360 +ADC_CFGR1_CONT655360 +ADC_CFGR1_DISCEN655360 +ADC_CFGR1_DMACFG655360 +ADC_CFGR1_DMAEN655360 +ADC_CFGR1_EXTEN655360 +ADC_CFGR1_EXTEN_0655360 +ADC_CFGR1_EXTEN_1655360 +ADC_CFGR1_EXTSEL655360 +ADC_CFGR1_EXTSEL_0655360 +ADC_CFGR1_EXTSEL_1655360 +ADC_CFGR1_EXTSEL_2655360 +ADC_CFGR1_OVRMOD655360 +ADC_CFGR1_RES655360 +ADC_CFGR1_RES_0655360 +ADC_CFGR1_RES_1655360 +ADC_CFGR1_SCANDIR655360 +ADC_CFGR1_WAIT655360 +ADC_CFGR2_CKMODE655360 +ADC_CFGR2_CKMODE_0655360 +ADC_CFGR2_CKMODE_1655360 +ADC_CFGR2_JITOFFDIV2655360 +ADC_CFGR2_JITOFFDIV4655360 +ADC_CHSELR_CHSEL0655360 +ADC_CHSELR_CHSEL1655360 +ADC_CHSELR_CHSEL10655360 +ADC_CHSELR_CHSEL11655360 +ADC_CHSELR_CHSEL12655360 +ADC_CHSELR_CHSEL13655360 +ADC_CHSELR_CHSEL14655360 +ADC_CHSELR_CHSEL15655360 +ADC_CHSELR_CHSEL16655360 +ADC_CHSELR_CHSEL17655360 +ADC_CHSELR_CHSEL18655360 +ADC_CHSELR_CHSEL2655360 +ADC_CHSELR_CHSEL3655360 +ADC_CHSELR_CHSEL4655360 +ADC_CHSELR_CHSEL5655360 +ADC_CHSELR_CHSEL6655360 +ADC_CHSELR_CHSEL7655360 +ADC_CHSELR_CHSEL8655360 +ADC_CHSELR_CHSEL9655360 +ADC_CR_ADCAL655360 +ADC_CR_ADDIS655360 +ADC_CR_ADEN655360 +ADC_CR_ADSTART655360 +ADC_CR_ADSTP655360 +ADC_DR_DATA655360 +ADC_HTR_HT655360 +ADC_IER_ADRDYIE655360 +ADC_IER_AWDIE655360 +ADC_IER_EOCIE655360 +ADC_IER_EOSEQIE655360 +ADC_IER_EOSIE655360 +ADC_IER_EOSMPIE655360 +ADC_IER_OVRIE655360 +ADC_ISR_ADRDY655360 +ADC_ISR_AWD655360 +ADC_ISR_EOC655360 +ADC_ISR_EOS655360 +ADC_ISR_EOSEQ655360 +ADC_ISR_EOSMP655360 +ADC_ISR_OVR655360 +ADC_LTR_LT655360 +ADC_SMPR1_SMPR655360 +ADC_SMPR1_SMPR_0655360 +ADC_SMPR1_SMPR_1655360 +ADC_SMPR1_SMPR_2655360 +ADC_SMPR_SMP655360 +ADC_SMPR_SMP_0655360 +ADC_SMPR_SMP_1655360 +ADC_SMPR_SMP_2655360 +ADC_TR_HT655360 +ADC_TR_LT655360 +AHB2PERIPH_BASE655360 +AHBPERIPH_BASE655360 +ALL_OK4anon_enum_00 +APBPERIPH_BASE655360 +BCAST_ID655360 +CAN655360 +CANID163840uint16_t +CAN_BASE655360 +CAN_BTR_BRP655360 +CAN_BTR_LBKM655360 +CAN_BTR_SILM655360 +CAN_BTR_SJW655360 +CAN_BTR_SJW_0655360 +CAN_BTR_SJW_1655360 +CAN_BTR_TS1655360 +CAN_BTR_TS1_0655360 +CAN_BTR_TS1_1655360 +CAN_BTR_TS1_2655360 +CAN_BTR_TS1_3655360 +CAN_BTR_TS2655360 +CAN_BTR_TS2_0655360 +CAN_BTR_TS2_1655360 +CAN_BTR_TS2_2655360 +CAN_BUSY4anon_enum_20 +CAN_ESR_BOFF655360 +CAN_ESR_EPVF655360 +CAN_ESR_EWGF655360 +CAN_ESR_LEC655360 +CAN_ESR_LEC_0655360 +CAN_ESR_LEC_1655360 +CAN_ESR_LEC_2655360 +CAN_ESR_REC655360 +CAN_ESR_TEC655360 +CAN_F0R1_FB0655360 +CAN_F0R1_FB1655360 +CAN_F0R1_FB10655360 +CAN_F0R1_FB11655360 +CAN_F0R1_FB12655360 +CAN_F0R1_FB13655360 +CAN_F0R1_FB14655360 +CAN_F0R1_FB15655360 +CAN_F0R1_FB16655360 +CAN_F0R1_FB17655360 +CAN_F0R1_FB18655360 +CAN_F0R1_FB19655360 +CAN_F0R1_FB2655360 +CAN_F0R1_FB20655360 +CAN_F0R1_FB21655360 +CAN_F0R1_FB22655360 +CAN_F0R1_FB23655360 +CAN_F0R1_FB24655360 +CAN_F0R1_FB25655360 +CAN_F0R1_FB26655360 +CAN_F0R1_FB27655360 +CAN_F0R1_FB28655360 +CAN_F0R1_FB29655360 +CAN_F0R1_FB3655360 +CAN_F0R1_FB30655360 +CAN_F0R1_FB31655360 +CAN_F0R1_FB4655360 +CAN_F0R1_FB5655360 +CAN_F0R1_FB6655360 +CAN_F0R1_FB7655360 +CAN_F0R1_FB8655360 +CAN_F0R1_FB9655360 +CAN_F0R2_FB0655360 +CAN_F0R2_FB1655360 +CAN_F0R2_FB10655360 +CAN_F0R2_FB11655360 +CAN_F0R2_FB12655360 +CAN_F0R2_FB13655360 +CAN_F0R2_FB14655360 +CAN_F0R2_FB15655360 +CAN_F0R2_FB16655360 +CAN_F0R2_FB17655360 +CAN_F0R2_FB18655360 +CAN_F0R2_FB19655360 +CAN_F0R2_FB2655360 +CAN_F0R2_FB20655360 +CAN_F0R2_FB21655360 +CAN_F0R2_FB22655360 +CAN_F0R2_FB23655360 +CAN_F0R2_FB24655360 +CAN_F0R2_FB25655360 +CAN_F0R2_FB26655360 +CAN_F0R2_FB27655360 +CAN_F0R2_FB28655360 +CAN_F0R2_FB29655360 +CAN_F0R2_FB3655360 +CAN_F0R2_FB30655360 +CAN_F0R2_FB31655360 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+CAN_RDH1R_DATA6655360 +CAN_RDH1R_DATA7655360 +CAN_RDL0R_DATA0655360 +CAN_RDL0R_DATA1655360 +CAN_RDL0R_DATA2655360 +CAN_RDL0R_DATA3655360 +CAN_RDL1R_DATA0655360 +CAN_RDL1R_DATA1655360 +CAN_RDL1R_DATA2655360 +CAN_RDL1R_DATA3655360 +CAN_RDT0R_DLC655360 +CAN_RDT0R_FMI655360 +CAN_RDT0R_TIME655360 +CAN_RDT1R_DLC655360 +CAN_RDT1R_FMI655360 +CAN_RDT1R_TIME655360 +CAN_READY4anon_enum_20 +CAN_RF0R_FMP0655360 +CAN_RF0R_FOVR0655360 +CAN_RF0R_FULL0655360 +CAN_RF0R_RFOM0655360 +CAN_RF1R_FMP1655360 +CAN_RF1R_FOVR1655360 +CAN_RF1R_FULL1655360 +CAN_RF1R_RFOM1655360 +CAN_RI0R_EXID655360 +CAN_RI0R_IDE655360 +CAN_RI0R_RTR655360 +CAN_RI0R_STID655360 +CAN_RI1R_EXID655360 +CAN_RI1R_IDE655360 +CAN_RI1R_RTR655360 +CAN_RI1R_STID655360 +CAN_STOP4anon_enum_20 +CAN_TDH0R_DATA4655360 +CAN_TDH0R_DATA5655360 +CAN_TDH0R_DATA6655360 +CAN_TDH0R_DATA7655360 +CAN_TDH1R_DATA4655360 +CAN_TDH1R_DATA5655360 +CAN_TDH1R_DATA6655360 +CAN_TDH1R_DATA7655360 +CAN_TDH2R_DATA4655360 +CAN_TDH2R_DATA5655360 +CAN_TDH2R_DATA6655360 +CAN_TDH2R_DATA7655360 +CAN_TDL0R_DATA0655360 +CAN_TDL0R_DATA1655360 +CAN_TDL0R_DATA2655360 +CAN_TDL0R_DATA3655360 +CAN_TDL1R_DATA0655360 +CAN_TDL1R_DATA1655360 +CAN_TDL1R_DATA2655360 +CAN_TDL1R_DATA3655360 +CAN_TDL2R_DATA0655360 +CAN_TDL2R_DATA1655360 +CAN_TDL2R_DATA2655360 +CAN_TDL2R_DATA3655360 +CAN_TDT0R_DLC655360 +CAN_TDT0R_TGT655360 +CAN_TDT0R_TIME655360 +CAN_TDT1R_DLC655360 +CAN_TDT1R_TGT655360 +CAN_TDT1R_TIME655360 +CAN_TDT2R_DLC655360 +CAN_TDT2R_TGT655360 +CAN_TDT2R_TIME655360 +CAN_TI0R_EXID655360 +CAN_TI0R_IDE655360 +CAN_TI0R_RTR655360 +CAN_TI0R_STID655360 +CAN_TI0R_TXRQ655360 +CAN_TI1R_EXID655360 +CAN_TI1R_IDE655360 +CAN_TI1R_RTR655360 +CAN_TI1R_STID655360 +CAN_TI1R_TXRQ655360 +CAN_TI2R_EXID655360 +CAN_TI2R_IDE655360 +CAN_TI2R_RTR655360 +CAN_TI2R_STID655360 +CAN_TI2R_TXRQ655360 +CAN_TSR_ABRQ0655360 +CAN_TSR_ABRQ1655360 +CAN_TSR_ABRQ2655360 +CAN_TSR_ALST0655360 +CAN_TSR_ALST1655360 +CAN_TSR_ALST2655360 +CAN_TSR_CODE655360 +CAN_TSR_LOW655360 +CAN_TSR_LOW0655360 +CAN_TSR_LOW1655360 +CAN_TSR_LOW2655360 +CAN_TSR_RQCP0655360 +CAN_TSR_RQCP1655360 +CAN_TSR_RQCP2655360 +CAN_TSR_TERR0655360 +CAN_TSR_TERR1655360 +CAN_TSR_TERR2655360 +CAN_TSR_TME655360 +CAN_TSR_TME0655360 +CAN_TSR_TME1655360 +CAN_TSR_TME2655360 +CAN_TSR_TXOK0655360 +CAN_TSR_TXOK1655360 +CAN_TSR_TXOK2655360 +CAN_get_status16()0CAN_status +CAN_get_status1024()0CAN_status +CAN_message40960anon_struct_1 +CAN_messagebuf_pop16()0CAN_message * +CAN_messagebuf_pop1024()0CAN_message * +CAN_messagebuf_push16(CAN_message *msg)0int +CAN_reinit16()0void +CAN_reinit1024()0void +CAN_setup16()0void +CAN_setup1024()0void +CAN_status40960anon_enum_2 +CEC655360 +CEC_BASE655360 +CEC_CFGR_BRDNOGEN655360 +CEC_CFGR_BREGEN655360 +CEC_CFGR_BRESTP655360 +CEC_CFGR_LBPEGEN655360 +CEC_CFGR_LSTN655360 +CEC_CFGR_OAR655360 +CEC_CFGR_RXTOL655360 +CEC_CFGR_SFT655360 +CEC_CFGR_SFTOPT655360 +CEC_CR_CECEN655360 +CEC_CR_TXEOM655360 +CEC_CR_TXSOM655360 +CEC_IER_ARBLSTIE655360 +CEC_IER_BREIE655360 +CEC_IER_LBPEIE655360 +CEC_IER_RXACKEIE655360 +CEC_IER_RXBRIE655360 +CEC_IER_RXENDIE655360 +CEC_IER_RXOVRIE655360 +CEC_IER_SBPEIE655360 +CEC_IER_TXACKEIE655360 +CEC_IER_TXBRIE655360 +CEC_IER_TXENDIE655360 +CEC_IER_TXERRIE655360 +CEC_IER_TXUDRIE655360 +CEC_ISR_ARBLST655360 +CEC_ISR_BRE655360 +CEC_ISR_LBPE655360 +CEC_ISR_RXACKE655360 +CEC_ISR_RXBR655360 +CEC_ISR_RXEND655360 +CEC_ISR_RXOVR655360 +CEC_ISR_SBPE655360 +CEC_ISR_TXACKE655360 +CEC_ISR_TXBR655360 +CEC_ISR_TXEND655360 +CEC_ISR_TXERR655360 +CEC_ISR_TXUDR655360 +CEC_TXDR_RXD655360 +CEC_TXDR_TXD655360 +CLEAR_BIT131072(REG,BIT)0 +CLEAR_REG131072(REG)0 +CMD_BCAST655360 +CMD_TOGGLE655360 +CONCAT131072(a,b)0 +CRC655360 +CRC_BASE655360 +CRC_CR_RESET655360 +CRC_CR_REV_IN655360 +CRC_CR_REV_IN_0655360 +CRC_CR_REV_IN_1655360 +CRC_CR_REV_OUT655360 +CRC_DR_DR655360 +CRC_IDR_IDR655360 +CRC_INIT_INIT655360 +CRS655360 +CRS_BASE655360 +CRS_CFGR_FELIM655360 +CRS_CFGR_RELOAD655360 +CRS_CFGR_SYNCDIV655360 +CRS_CFGR_SYNCDIV_0655360 +CRS_CFGR_SYNCDIV_1655360 +CRS_CFGR_SYNCDIV_2655360 +CRS_CFGR_SYNCPOL655360 +CRS_CFGR_SYNCSRC655360 +CRS_CFGR_SYNCSRC_0655360 +CRS_CFGR_SYNCSRC_1655360 +CRS_CR_AUTOTRIMEN655360 +CRS_CR_CEN655360 +CRS_CR_ERRIE655360 +CRS_CR_ESYNCIE655360 +CRS_CR_SWSYNC655360 +CRS_CR_SYNCOKIE655360 +CRS_CR_SYNCWARNIE655360 +CRS_CR_TRIM655360 +CRS_ICR_ERRC655360 +CRS_ICR_ESYNCC655360 +CRS_ICR_SYNCOKC655360 +CRS_ICR_SYNCWARNC655360 +CRS_ISR_ERRF655360 +CRS_ISR_ESYNCF655360 +CRS_ISR_FECAP655360 +CRS_ISR_FEDIR655360 +CRS_ISR_SYNCERR655360 +CRS_ISR_SYNCMISS655360 +CRS_ISR_SYNCOKF655360 +CRS_ISR_SYNCWARNF655360 +CRS_ISR_TRIMOVF655360 +DBGMCU655360 +DBGMCU_APB1_FZ_DBG_CAN_STOP655360 +DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT655360 +DBGMCU_APB1_FZ_DBG_IWDG_STOP655360 +DBGMCU_APB1_FZ_DBG_RTC_STOP655360 +DBGMCU_APB1_FZ_DBG_TIM14_STOP655360 +DBGMCU_APB1_FZ_DBG_TIM2_STOP655360 +DBGMCU_APB1_FZ_DBG_TIM3_STOP655360 +DBGMCU_APB1_FZ_DBG_WWDG_STOP655360 +DBGMCU_APB2_FZ_DBG_TIM16_STOP655360 +DBGMCU_APB2_FZ_DBG_TIM17_STOP655360 +DBGMCU_APB2_FZ_DBG_TIM1_STOP655360 +DBGMCU_BASE655360 +DBGMCU_CR_DBG_STANDBY655360 +DBGMCU_CR_DBG_STOP655360 +DBGMCU_IDCODE_DEV_ID655360 +DBGMCU_IDCODE_REV_ID655360 +DBGMCU_IDCODE_REV_ID_0655360 +DBGMCU_IDCODE_REV_ID_1655360 +DBGMCU_IDCODE_REV_ID_10655360 +DBGMCU_IDCODE_REV_ID_11655360 +DBGMCU_IDCODE_REV_ID_12655360 +DBGMCU_IDCODE_REV_ID_13655360 +DBGMCU_IDCODE_REV_ID_14655360 +DBGMCU_IDCODE_REV_ID_15655360 +DBGMCU_IDCODE_REV_ID_2655360 +DBGMCU_IDCODE_REV_ID_3655360 +DBGMCU_IDCODE_REV_ID_4655360 +DBGMCU_IDCODE_REV_ID_5655360 +DBGMCU_IDCODE_REV_ID_6655360 +DBGMCU_IDCODE_REV_ID_7655360 +DBGMCU_IDCODE_REV_ID_8655360 +DBGMCU_IDCODE_REV_ID_9655360 +DMA1655360 +DMA1_BASE655360 +DMA1_Channel1655360 +DMA1_Channel1_BASE655360 +DMA1_Channel2655360 +DMA1_Channel2_BASE655360 +DMA1_Channel3655360 +DMA1_Channel3_BASE655360 +DMA1_Channel4655360 +DMA1_Channel4_5_6_7_IRQHandler655360 +DMA1_Channel4_5_6_7_IRQn655360 +DMA1_Channel4_BASE655360 +DMA1_Channel5655360 +DMA1_Channel5_BASE655360 +DMA1_Channel6655360 +DMA1_Channel6_BASE655360 +DMA1_Channel7655360 +DMA1_Channel7_BASE655360 +DMA_CCR_CIRC655360 +DMA_CCR_DIR655360 +DMA_CCR_EN655360 +DMA_CCR_HTIE655360 +DMA_CCR_MEM2MEM655360 +DMA_CCR_MINC655360 +DMA_CCR_MSIZE655360 +DMA_CCR_MSIZE_0655360 +DMA_CCR_MSIZE_1655360 +DMA_CCR_PINC655360 +DMA_CCR_PL655360 +DMA_CCR_PL_0655360 +DMA_CCR_PL_1655360 +DMA_CCR_PSIZE655360 +DMA_CCR_PSIZE_0655360 +DMA_CCR_PSIZE_1655360 +DMA_CCR_TCIE655360 +DMA_CCR_TEIE655360 +DMA_CMAR_MA655360 +DMA_CNDTR_NDT655360 +DMA_CPAR_PA655360 +DMA_IFCR_CGIF1655360 +DMA_IFCR_CGIF2655360 +DMA_IFCR_CGIF3655360 +DMA_IFCR_CGIF4655360 +DMA_IFCR_CGIF5655360 +DMA_IFCR_CGIF6655360 +DMA_IFCR_CGIF7655360 +DMA_IFCR_CHTIF1655360 +DMA_IFCR_CHTIF2655360 +DMA_IFCR_CHTIF3655360 +DMA_IFCR_CHTIF4655360 +DMA_IFCR_CHTIF5655360 +DMA_IFCR_CHTIF6655360 +DMA_IFCR_CHTIF7655360 +DMA_IFCR_CTCIF1655360 +DMA_IFCR_CTCIF2655360 +DMA_IFCR_CTCIF3655360 +DMA_IFCR_CTCIF4655360 +DMA_IFCR_CTCIF5655360 +DMA_IFCR_CTCIF6655360 +DMA_IFCR_CTCIF7655360 +DMA_IFCR_CTEIF1655360 +DMA_IFCR_CTEIF2655360 +DMA_IFCR_CTEIF3655360 +DMA_IFCR_CTEIF4655360 +DMA_IFCR_CTEIF5655360 +DMA_IFCR_CTEIF6655360 +DMA_IFCR_CTEIF7655360 +DMA_ISR_GIF1655360 +DMA_ISR_GIF2655360 +DMA_ISR_GIF3655360 +DMA_ISR_GIF4655360 +DMA_ISR_GIF5655360 +DMA_ISR_GIF6655360 +DMA_ISR_GIF7655360 +DMA_ISR_HTIF1655360 +DMA_ISR_HTIF2655360 +DMA_ISR_HTIF3655360 +DMA_ISR_HTIF4655360 +DMA_ISR_HTIF5655360 +DMA_ISR_HTIF6655360 +DMA_ISR_HTIF7655360 +DMA_ISR_TCIF1655360 +DMA_ISR_TCIF2655360 +DMA_ISR_TCIF3655360 +DMA_ISR_TCIF4655360 +DMA_ISR_TCIF5655360 +DMA_ISR_TCIF6655360 +DMA_ISR_TCIF7655360 +DMA_ISR_TEIF1655360 +DMA_ISR_TEIF2655360 +DMA_ISR_TEIF3655360 +DMA_ISR_TEIF4655360 +DMA_ISR_TEIF5655360 +DMA_ISR_TEIF6655360 +DMA_ISR_TEIF7655360 +EBUG655360 +EXTI655360 +EXTI_BASE655360 +EXTI_EMR_MR0655360 +EXTI_EMR_MR1655360 +EXTI_EMR_MR10655360 +EXTI_EMR_MR11655360 +EXTI_EMR_MR12655360 +EXTI_EMR_MR13655360 +EXTI_EMR_MR14655360 +EXTI_EMR_MR15655360 +EXTI_EMR_MR16655360 +EXTI_EMR_MR17655360 +EXTI_EMR_MR19655360 +EXTI_EMR_MR2655360 +EXTI_EMR_MR21655360 +EXTI_EMR_MR22655360 +EXTI_EMR_MR23655360 +EXTI_EMR_MR25655360 +EXTI_EMR_MR27655360 +EXTI_EMR_MR3655360 +EXTI_EMR_MR4655360 +EXTI_EMR_MR5655360 +EXTI_EMR_MR6655360 +EXTI_EMR_MR7655360 +EXTI_EMR_MR8655360 +EXTI_EMR_MR9655360 +EXTI_FTSR_TR0655360 +EXTI_FTSR_TR1655360 +EXTI_FTSR_TR10655360 +EXTI_FTSR_TR11655360 +EXTI_FTSR_TR12655360 +EXTI_FTSR_TR13655360 +EXTI_FTSR_TR14655360 +EXTI_FTSR_TR15655360 +EXTI_FTSR_TR16655360 +EXTI_FTSR_TR17655360 +EXTI_FTSR_TR19655360 +EXTI_FTSR_TR2655360 +EXTI_FTSR_TR3655360 +EXTI_FTSR_TR4655360 +EXTI_FTSR_TR5655360 +EXTI_FTSR_TR6655360 +EXTI_FTSR_TR7655360 +EXTI_FTSR_TR8655360 +EXTI_FTSR_TR9655360 +EXTI_IMR_MR0655360 +EXTI_IMR_MR1655360 +EXTI_IMR_MR10655360 +EXTI_IMR_MR11655360 +EXTI_IMR_MR12655360 +EXTI_IMR_MR13655360 +EXTI_IMR_MR14655360 +EXTI_IMR_MR15655360 +EXTI_IMR_MR16655360 +EXTI_IMR_MR17655360 +EXTI_IMR_MR19655360 +EXTI_IMR_MR2655360 +EXTI_IMR_MR21655360 +EXTI_IMR_MR22655360 +EXTI_IMR_MR23655360 +EXTI_IMR_MR25655360 +EXTI_IMR_MR27655360 +EXTI_IMR_MR3655360 +EXTI_IMR_MR4655360 +EXTI_IMR_MR5655360 +EXTI_IMR_MR6655360 +EXTI_IMR_MR7655360 +EXTI_IMR_MR8655360 +EXTI_IMR_MR9655360 +EXTI_PR_PR0655360 +EXTI_PR_PR1655360 +EXTI_PR_PR10655360 +EXTI_PR_PR11655360 +EXTI_PR_PR12655360 +EXTI_PR_PR13655360 +EXTI_PR_PR14655360 +EXTI_PR_PR15655360 +EXTI_PR_PR16655360 +EXTI_PR_PR17655360 +EXTI_PR_PR19655360 +EXTI_PR_PR2655360 +EXTI_PR_PR3655360 +EXTI_PR_PR4655360 +EXTI_PR_PR5655360 +EXTI_PR_PR6655360 +EXTI_PR_PR7655360 +EXTI_PR_PR8655360 +EXTI_PR_PR9655360 +EXTI_RTSR_TR0655360 +EXTI_RTSR_TR1655360 +EXTI_RTSR_TR10655360 +EXTI_RTSR_TR11655360 +EXTI_RTSR_TR12655360 +EXTI_RTSR_TR13655360 +EXTI_RTSR_TR14655360 +EXTI_RTSR_TR15655360 +EXTI_RTSR_TR16655360 +EXTI_RTSR_TR17655360 +EXTI_RTSR_TR19655360 +EXTI_RTSR_TR2655360 +EXTI_RTSR_TR3655360 +EXTI_RTSR_TR4655360 +EXTI_RTSR_TR5655360 +EXTI_RTSR_TR6655360 +EXTI_RTSR_TR7655360 +EXTI_RTSR_TR8655360 +EXTI_RTSR_TR9655360 +EXTI_SWIER_SWIER0655360 +EXTI_SWIER_SWIER1655360 +EXTI_SWIER_SWIER10655360 +EXTI_SWIER_SWIER11655360 +EXTI_SWIER_SWIER12655360 +EXTI_SWIER_SWIER13655360 +EXTI_SWIER_SWIER14655360 +EXTI_SWIER_SWIER15655360 +EXTI_SWIER_SWIER16655360 +EXTI_SWIER_SWIER17655360 +EXTI_SWIER_SWIER19655360 +EXTI_SWIER_SWIER2655360 +EXTI_SWIER_SWIER3655360 +EXTI_SWIER_SWIER4655360 +EXTI_SWIER_SWIER5655360 +EXTI_SWIER_SWIER6655360 +EXTI_SWIER_SWIER7655360 +EXTI_SWIER_SWIER8655360 +EXTI_SWIER_SWIER9655360 +FLASH655360 +FLASH_ACR_LATENCY655360 +FLASH_ACR_PRFTBE655360 +FLASH_ACR_PRFTBS655360 +FLASH_AR_FAR655360 +FLASH_BASE655360 +FLASH_CR_EOPIE655360 +FLASH_CR_ERRIE655360 +FLASH_CR_LOCK655360 +FLASH_CR_MER655360 +FLASH_CR_OBL_LAUNCH655360 +FLASH_CR_OPTER655360 +FLASH_CR_OPTPG655360 +FLASH_CR_OPTWRE655360 +FLASH_CR_PER655360 +FLASH_CR_PG655360 +FLASH_CR_STRT655360 +FLASH_FKEY1655360 +FLASH_FKEY2655360 +FLASH_KEYR_FKEYR655360 +FLASH_OBR_BOOT1655360 +FLASH_OBR_IWDG_SW655360 +FLASH_OBR_OPTERR655360 +FLASH_OBR_RDPRT1655360 +FLASH_OBR_RDPRT2655360 +FLASH_OBR_USER655360 +FLASH_OBR_VDDA_ANALOG655360 +FLASH_OBR_VDDA_MONITOR655360 +FLASH_OBR_nBOOT1655360 +FLASH_OBR_nRST_STDBY655360 +FLASH_OBR_nRST_STOP655360 +FLASH_OPTKEY1655360 +FLASH_OPTKEY2655360 +FLASH_OPTKEYR_OPTKEYR655360 +FLASH_R_BASE655360 +FLASH_SR_BSY655360 +FLASH_SR_EOP655360 +FLASH_SR_PGERR655360 +FLASH_SR_WRPERR655360 +FLASH_SR_WRPRTERR655360 +FLASH_WRPR_WRP655360 +FORMUSART131072(X)0 +GPIOA655360 +GPIOA_BASE655360 +GPIOB655360 +GPIOB_BASE655360 +GPIOC655360 +GPIOC_BASE655360 +GPIOF655360 +GPIOF_BASE655360 +GPIO_AFRH_AFRH0655360 +GPIO_AFRH_AFRH1655360 +GPIO_AFRH_AFRH2655360 +GPIO_AFRH_AFRH3655360 +GPIO_AFRH_AFRH4655360 +GPIO_AFRH_AFRH5655360 +GPIO_AFRH_AFRH6655360 +GPIO_AFRH_AFRH7655360 +GPIO_AFRL_AFRL0655360 +GPIO_AFRL_AFRL1655360 +GPIO_AFRL_AFRL2655360 +GPIO_AFRL_AFRL3655360 +GPIO_AFRL_AFRL4655360 +GPIO_AFRL_AFRL5655360 +GPIO_AFRL_AFRL6655360 +GPIO_AFRL_AFRL7655360 +GPIO_BRR_BR_0655360 +GPIO_BRR_BR_1655360 +GPIO_BRR_BR_10655360 +GPIO_BRR_BR_11655360 +GPIO_BRR_BR_12655360 +GPIO_BRR_BR_13655360 +GPIO_BRR_BR_14655360 +GPIO_BRR_BR_15655360 +GPIO_BRR_BR_2655360 +GPIO_BRR_BR_3655360 +GPIO_BRR_BR_4655360 +GPIO_BRR_BR_5655360 +GPIO_BRR_BR_6655360 +GPIO_BRR_BR_7655360 +GPIO_BRR_BR_8655360 +GPIO_BRR_BR_9655360 +GPIO_BSRR_BR_0655360 +GPIO_BSRR_BR_1655360 +GPIO_BSRR_BR_10655360 +GPIO_BSRR_BR_11655360 +GPIO_BSRR_BR_12655360 +GPIO_BSRR_BR_13655360 +GPIO_BSRR_BR_14655360 +GPIO_BSRR_BR_15655360 +GPIO_BSRR_BR_2655360 +GPIO_BSRR_BR_3655360 +GPIO_BSRR_BR_4655360 +GPIO_BSRR_BR_5655360 +GPIO_BSRR_BR_6655360 +GPIO_BSRR_BR_7655360 +GPIO_BSRR_BR_8655360 +GPIO_BSRR_BR_9655360 +GPIO_BSRR_BS_0655360 +GPIO_BSRR_BS_1655360 +GPIO_BSRR_BS_10655360 +GPIO_BSRR_BS_11655360 +GPIO_BSRR_BS_12655360 +GPIO_BSRR_BS_13655360 +GPIO_BSRR_BS_14655360 +GPIO_BSRR_BS_15655360 +GPIO_BSRR_BS_2655360 +GPIO_BSRR_BS_3655360 +GPIO_BSRR_BS_4655360 +GPIO_BSRR_BS_5655360 +GPIO_BSRR_BS_6655360 +GPIO_BSRR_BS_7655360 +GPIO_BSRR_BS_8655360 +GPIO_BSRR_BS_9655360 +GPIO_IDR_0655360 +GPIO_IDR_1655360 +GPIO_IDR_10655360 +GPIO_IDR_11655360 +GPIO_IDR_12655360 +GPIO_IDR_13655360 +GPIO_IDR_14655360 +GPIO_IDR_15655360 +GPIO_IDR_2655360 +GPIO_IDR_3655360 +GPIO_IDR_4655360 +GPIO_IDR_5655360 +GPIO_IDR_6655360 +GPIO_IDR_7655360 +GPIO_IDR_8655360 +GPIO_IDR_9655360 +GPIO_LCKR_LCK0655360 +GPIO_LCKR_LCK1655360 +GPIO_LCKR_LCK10655360 +GPIO_LCKR_LCK11655360 +GPIO_LCKR_LCK12655360 +GPIO_LCKR_LCK13655360 +GPIO_LCKR_LCK14655360 +GPIO_LCKR_LCK15655360 +GPIO_LCKR_LCK2655360 +GPIO_LCKR_LCK3655360 +GPIO_LCKR_LCK4655360 +GPIO_LCKR_LCK5655360 +GPIO_LCKR_LCK6655360 +GPIO_LCKR_LCK7655360 +GPIO_LCKR_LCK8655360 +GPIO_LCKR_LCK9655360 +GPIO_LCKR_LCKK655360 +GPIO_MODER_MODER0655360 +GPIO_MODER_MODER0_0655360 +GPIO_MODER_MODER0_1655360 +GPIO_MODER_MODER0_AF655360 +GPIO_MODER_MODER0_AI655360 +GPIO_MODER_MODER0_O655360 +GPIO_MODER_MODER1655360 +GPIO_MODER_MODER10655360 +GPIO_MODER_MODER10_0655360 +GPIO_MODER_MODER10_1655360 +GPIO_MODER_MODER10_AF655360 +GPIO_MODER_MODER10_AI655360 +GPIO_MODER_MODER10_O655360 +GPIO_MODER_MODER11655360 +GPIO_MODER_MODER11_0655360 +GPIO_MODER_MODER11_1655360 +GPIO_MODER_MODER11_AF655360 +GPIO_MODER_MODER11_AI655360 +GPIO_MODER_MODER11_O655360 +GPIO_MODER_MODER12655360 +GPIO_MODER_MODER12_0655360 +GPIO_MODER_MODER12_1655360 +GPIO_MODER_MODER12_AF655360 +GPIO_MODER_MODER12_AI655360 +GPIO_MODER_MODER12_O655360 +GPIO_MODER_MODER13655360 +GPIO_MODER_MODER13_0655360 +GPIO_MODER_MODER13_1655360 +GPIO_MODER_MODER13_AF655360 +GPIO_MODER_MODER13_AI655360 +GPIO_MODER_MODER13_O655360 +GPIO_MODER_MODER14655360 +GPIO_MODER_MODER14_0655360 +GPIO_MODER_MODER14_1655360 +GPIO_MODER_MODER14_AF655360 +GPIO_MODER_MODER14_AI655360 +GPIO_MODER_MODER14_O655360 +GPIO_MODER_MODER15655360 +GPIO_MODER_MODER15_0655360 +GPIO_MODER_MODER15_1655360 +GPIO_MODER_MODER15_AF655360 +GPIO_MODER_MODER15_AI655360 +GPIO_MODER_MODER15_O655360 +GPIO_MODER_MODER1_0655360 +GPIO_MODER_MODER1_1655360 +GPIO_MODER_MODER1_AF655360 +GPIO_MODER_MODER1_AI655360 +GPIO_MODER_MODER1_O655360 +GPIO_MODER_MODER2655360 +GPIO_MODER_MODER2_0655360 +GPIO_MODER_MODER2_1655360 +GPIO_MODER_MODER2_AF655360 +GPIO_MODER_MODER2_AI655360 +GPIO_MODER_MODER2_O655360 +GPIO_MODER_MODER3655360 +GPIO_MODER_MODER3_0655360 +GPIO_MODER_MODER3_1655360 +GPIO_MODER_MODER3_AF655360 +GPIO_MODER_MODER3_AI655360 +GPIO_MODER_MODER3_O655360 +GPIO_MODER_MODER4655360 +GPIO_MODER_MODER4_0655360 +GPIO_MODER_MODER4_1655360 +GPIO_MODER_MODER4_AF655360 +GPIO_MODER_MODER4_AI655360 +GPIO_MODER_MODER4_O655360 +GPIO_MODER_MODER5655360 +GPIO_MODER_MODER5_0655360 +GPIO_MODER_MODER5_1655360 +GPIO_MODER_MODER5_AF655360 +GPIO_MODER_MODER5_AI655360 +GPIO_MODER_MODER5_O655360 +GPIO_MODER_MODER6655360 +GPIO_MODER_MODER6_0655360 +GPIO_MODER_MODER6_1655360 +GPIO_MODER_MODER6_AF655360 +GPIO_MODER_MODER6_AI655360 +GPIO_MODER_MODER6_O655360 +GPIO_MODER_MODER7655360 +GPIO_MODER_MODER7_0655360 +GPIO_MODER_MODER7_1655360 +GPIO_MODER_MODER7_AF655360 +GPIO_MODER_MODER7_AI655360 +GPIO_MODER_MODER7_O655360 +GPIO_MODER_MODER8655360 +GPIO_MODER_MODER8_0655360 +GPIO_MODER_MODER8_1655360 +GPIO_MODER_MODER8_AF655360 +GPIO_MODER_MODER8_AI655360 +GPIO_MODER_MODER8_O655360 +GPIO_MODER_MODER9655360 +GPIO_MODER_MODER9_0655360 +GPIO_MODER_MODER9_1655360 +GPIO_MODER_MODER9_AF655360 +GPIO_MODER_MODER9_AI655360 +GPIO_MODER_MODER9_O655360 +GPIO_ODR_0655360 +GPIO_ODR_1655360 +GPIO_ODR_10655360 +GPIO_ODR_11655360 +GPIO_ODR_12655360 +GPIO_ODR_13655360 +GPIO_ODR_14655360 +GPIO_ODR_15655360 +GPIO_ODR_2655360 +GPIO_ODR_3655360 +GPIO_ODR_4655360 +GPIO_ODR_5655360 +GPIO_ODR_6655360 +GPIO_ODR_7655360 +GPIO_ODR_8655360 +GPIO_ODR_9655360 +GPIO_OSPEEDER_OSPEEDR0655360 +GPIO_OSPEEDER_OSPEEDR0_0655360 +GPIO_OSPEEDER_OSPEEDR0_1655360 +GPIO_OSPEEDER_OSPEEDR1655360 +GPIO_OSPEEDER_OSPEEDR10655360 +GPIO_OSPEEDER_OSPEEDR10_0655360 +GPIO_OSPEEDER_OSPEEDR10_1655360 +GPIO_OSPEEDER_OSPEEDR11655360 +GPIO_OSPEEDER_OSPEEDR11_0655360 +GPIO_OSPEEDER_OSPEEDR11_1655360 +GPIO_OSPEEDER_OSPEEDR12655360 +GPIO_OSPEEDER_OSPEEDR12_0655360 +GPIO_OSPEEDER_OSPEEDR12_1655360 +GPIO_OSPEEDER_OSPEEDR13655360 +GPIO_OSPEEDER_OSPEEDR13_0655360 +GPIO_OSPEEDER_OSPEEDR13_1655360 +GPIO_OSPEEDER_OSPEEDR14655360 +GPIO_OSPEEDER_OSPEEDR14_0655360 +GPIO_OSPEEDER_OSPEEDR14_1655360 +GPIO_OSPEEDER_OSPEEDR15655360 +GPIO_OSPEEDER_OSPEEDR15_0655360 +GPIO_OSPEEDER_OSPEEDR15_1655360 +GPIO_OSPEEDER_OSPEEDR1_0655360 +GPIO_OSPEEDER_OSPEEDR1_1655360 +GPIO_OSPEEDER_OSPEEDR2655360 +GPIO_OSPEEDER_OSPEEDR2_0655360 +GPIO_OSPEEDER_OSPEEDR2_1655360 +GPIO_OSPEEDER_OSPEEDR3655360 +GPIO_OSPEEDER_OSPEEDR3_0655360 +GPIO_OSPEEDER_OSPEEDR3_1655360 +GPIO_OSPEEDER_OSPEEDR4655360 +GPIO_OSPEEDER_OSPEEDR4_0655360 +GPIO_OSPEEDER_OSPEEDR4_1655360 +GPIO_OSPEEDER_OSPEEDR5655360 +GPIO_OSPEEDER_OSPEEDR5_0655360 +GPIO_OSPEEDER_OSPEEDR5_1655360 +GPIO_OSPEEDER_OSPEEDR6655360 +GPIO_OSPEEDER_OSPEEDR6_0655360 +GPIO_OSPEEDER_OSPEEDR6_1655360 +GPIO_OSPEEDER_OSPEEDR7655360 +GPIO_OSPEEDER_OSPEEDR7_0655360 +GPIO_OSPEEDER_OSPEEDR7_1655360 +GPIO_OSPEEDER_OSPEEDR8655360 +GPIO_OSPEEDER_OSPEEDR8_0655360 +GPIO_OSPEEDER_OSPEEDR8_1655360 +GPIO_OSPEEDER_OSPEEDR9655360 +GPIO_OSPEEDER_OSPEEDR9_0655360 +GPIO_OSPEEDER_OSPEEDR9_1655360 +GPIO_OSPEEDR_OSPEEDR0655360 +GPIO_OSPEEDR_OSPEEDR0_0655360 +GPIO_OSPEEDR_OSPEEDR0_1655360 +GPIO_OSPEEDR_OSPEEDR1655360 +GPIO_OSPEEDR_OSPEEDR10655360 +GPIO_OSPEEDR_OSPEEDR10_0655360 +GPIO_OSPEEDR_OSPEEDR10_1655360 +GPIO_OSPEEDR_OSPEEDR11655360 +GPIO_OSPEEDR_OSPEEDR11_0655360 +GPIO_OSPEEDR_OSPEEDR11_1655360 +GPIO_OSPEEDR_OSPEEDR12655360 +GPIO_OSPEEDR_OSPEEDR12_0655360 +GPIO_OSPEEDR_OSPEEDR12_1655360 +GPIO_OSPEEDR_OSPEEDR13655360 +GPIO_OSPEEDR_OSPEEDR13_0655360 +GPIO_OSPEEDR_OSPEEDR13_1655360 +GPIO_OSPEEDR_OSPEEDR14655360 +GPIO_OSPEEDR_OSPEEDR14_0655360 +GPIO_OSPEEDR_OSPEEDR14_1655360 +GPIO_OSPEEDR_OSPEEDR15655360 +GPIO_OSPEEDR_OSPEEDR15_0655360 +GPIO_OSPEEDR_OSPEEDR15_1655360 +GPIO_OSPEEDR_OSPEEDR1_0655360 +GPIO_OSPEEDR_OSPEEDR1_1655360 +GPIO_OSPEEDR_OSPEEDR2655360 +GPIO_OSPEEDR_OSPEEDR2_0655360 +GPIO_OSPEEDR_OSPEEDR2_1655360 +GPIO_OSPEEDR_OSPEEDR3655360 +GPIO_OSPEEDR_OSPEEDR3_0655360 +GPIO_OSPEEDR_OSPEEDR3_1655360 +GPIO_OSPEEDR_OSPEEDR4655360 +GPIO_OSPEEDR_OSPEEDR4_0655360 +GPIO_OSPEEDR_OSPEEDR4_1655360 +GPIO_OSPEEDR_OSPEEDR5655360 +GPIO_OSPEEDR_OSPEEDR5_0655360 +GPIO_OSPEEDR_OSPEEDR5_1655360 +GPIO_OSPEEDR_OSPEEDR6655360 +GPIO_OSPEEDR_OSPEEDR6_0655360 +GPIO_OSPEEDR_OSPEEDR6_1655360 +GPIO_OSPEEDR_OSPEEDR7655360 +GPIO_OSPEEDR_OSPEEDR7_0655360 +GPIO_OSPEEDR_OSPEEDR7_1655360 +GPIO_OSPEEDR_OSPEEDR8655360 +GPIO_OSPEEDR_OSPEEDR8_0655360 +GPIO_OSPEEDR_OSPEEDR8_1655360 +GPIO_OSPEEDR_OSPEEDR9655360 +GPIO_OSPEEDR_OSPEEDR9_0655360 +GPIO_OSPEEDR_OSPEEDR9_1655360 +GPIO_OTYPER_OT_0655360 +GPIO_OTYPER_OT_1655360 +GPIO_OTYPER_OT_10655360 +GPIO_OTYPER_OT_11655360 +GPIO_OTYPER_OT_12655360 +GPIO_OTYPER_OT_13655360 +GPIO_OTYPER_OT_14655360 +GPIO_OTYPER_OT_15655360 +GPIO_OTYPER_OT_2655360 +GPIO_OTYPER_OT_3655360 +GPIO_OTYPER_OT_4655360 +GPIO_OTYPER_OT_5655360 +GPIO_OTYPER_OT_6655360 +GPIO_OTYPER_OT_7655360 +GPIO_OTYPER_OT_8655360 +GPIO_OTYPER_OT_9655360 +GPIO_PUPDR_PUPDR0655360 +GPIO_PUPDR_PUPDR0_0655360 +GPIO_PUPDR_PUPDR0_1655360 +GPIO_PUPDR_PUPDR1655360 +GPIO_PUPDR_PUPDR10655360 +GPIO_PUPDR_PUPDR10_0655360 +GPIO_PUPDR_PUPDR10_1655360 +GPIO_PUPDR_PUPDR11655360 +GPIO_PUPDR_PUPDR11_0655360 +GPIO_PUPDR_PUPDR11_1655360 +GPIO_PUPDR_PUPDR12655360 +GPIO_PUPDR_PUPDR12_0655360 +GPIO_PUPDR_PUPDR12_1655360 +GPIO_PUPDR_PUPDR13655360 +GPIO_PUPDR_PUPDR13_0655360 +GPIO_PUPDR_PUPDR13_1655360 +GPIO_PUPDR_PUPDR14655360 +GPIO_PUPDR_PUPDR14_0655360 +GPIO_PUPDR_PUPDR14_1655360 +GPIO_PUPDR_PUPDR15655360 +GPIO_PUPDR_PUPDR15_0655360 +GPIO_PUPDR_PUPDR15_1655360 +GPIO_PUPDR_PUPDR1_0655360 +GPIO_PUPDR_PUPDR1_1655360 +GPIO_PUPDR_PUPDR2655360 +GPIO_PUPDR_PUPDR2_0655360 +GPIO_PUPDR_PUPDR2_1655360 +GPIO_PUPDR_PUPDR3655360 +GPIO_PUPDR_PUPDR3_0655360 +GPIO_PUPDR_PUPDR3_1655360 +GPIO_PUPDR_PUPDR4655360 +GPIO_PUPDR_PUPDR4_0655360 +GPIO_PUPDR_PUPDR4_1655360 +GPIO_PUPDR_PUPDR5655360 +GPIO_PUPDR_PUPDR5_0655360 +GPIO_PUPDR_PUPDR5_1655360 +GPIO_PUPDR_PUPDR6655360 +GPIO_PUPDR_PUPDR6_0655360 +GPIO_PUPDR_PUPDR6_1655360 +GPIO_PUPDR_PUPDR7655360 +GPIO_PUPDR_PUPDR7_0655360 +GPIO_PUPDR_PUPDR7_1655360 +GPIO_PUPDR_PUPDR8655360 +GPIO_PUPDR_PUPDR8_0655360 +GPIO_PUPDR_PUPDR8_1655360 +GPIO_PUPDR_PUPDR9655360 +GPIO_PUPDR_PUPDR9_0655360 +GPIO_PUPDR_PUPDR9_1655360 +I2C1655360 +I2C1_BASE655360 +I2C_CR1_ADDRIE655360 +I2C_CR1_ALERTEN655360 +I2C_CR1_ANFOFF655360 +I2C_CR1_DFN655360 +I2C_CR1_ERRIE655360 +I2C_CR1_GCEN655360 +I2C_CR1_NACKIE655360 +I2C_CR1_NOSTRETCH655360 +I2C_CR1_PE655360 +I2C_CR1_PECEN655360 +I2C_CR1_RXDMAEN655360 +I2C_CR1_RXIE655360 +I2C_CR1_SBC655360 +I2C_CR1_SMBDEN655360 +I2C_CR1_SMBHEN655360 +I2C_CR1_STOPIE655360 +I2C_CR1_SWRST655360 +I2C_CR1_TCIE655360 +I2C_CR1_TXDMAEN655360 +I2C_CR1_TXIE655360 +I2C_CR1_WUPEN655360 +I2C_CR2_ADD10655360 +I2C_CR2_AUTOEND655360 +I2C_CR2_HEAD10R655360 +I2C_CR2_NACK655360 +I2C_CR2_NBYTES655360 +I2C_CR2_PECBYTE655360 +I2C_CR2_RD_WRN655360 +I2C_CR2_RELOAD655360 +I2C_CR2_SADD655360 +I2C_CR2_START655360 +I2C_CR2_STOP655360 +I2C_ICR_ADDRCF655360 +I2C_ICR_ALERTCF655360 +I2C_ICR_ARLOCF655360 +I2C_ICR_BERRCF655360 +I2C_ICR_NACKCF655360 +I2C_ICR_OVRCF655360 +I2C_ICR_PECCF655360 +I2C_ICR_STOPCF655360 +I2C_ICR_TIMOUTCF655360 +I2C_ISR_ADDCODE655360 +I2C_ISR_ADDR655360 +I2C_ISR_ALERT655360 +I2C_ISR_ARLO655360 +I2C_ISR_BERR655360 +I2C_ISR_BUSY655360 +I2C_ISR_DIR655360 +I2C_ISR_NACKF655360 +I2C_ISR_OVR655360 +I2C_ISR_PECERR655360 +I2C_ISR_RXNE655360 +I2C_ISR_STOPF655360 +I2C_ISR_TC655360 +I2C_ISR_TCR655360 +I2C_ISR_TIMEOUT655360 +I2C_ISR_TXE655360 +I2C_ISR_TXIS655360 +I2C_OAR1_OA1655360 +I2C_OAR1_OA1EN655360 +I2C_OAR1_OA1MODE655360 +I2C_OAR2_OA2655360 +I2C_OAR2_OA2EN655360 +I2C_OAR2_OA2MSK655360 +I2C_PECR_PEC655360 +I2C_RXDR_RXDATA655360 +I2C_TIMEOUTR_TEXTEN655360 +I2C_TIMEOUTR_TIDLE655360 +I2C_TIMEOUTR_TIMEOUTA655360 +I2C_TIMEOUTR_TIMEOUTB655360 +I2C_TIMEOUTR_TIMOUTEN655360 +I2C_TIMINGR_PRESC655360 +I2C_TIMINGR_SCLDEL655360 +I2C_TIMINGR_SCLH655360 +I2C_TIMINGR_SCLL655360 +I2C_TIMINGR_SDADEL655360 +I2C_TXDR_TXDATA655360 +INT16_C131072(c)0 +INT16_MAX655360 +INT16_MIN655360 +INT16_WIDTH655360 +INT32_C131072(c)0 +INT32_MAX655360 +INT32_MIN655360 +INT32_WIDTH655360 +INT64_C131072(c)0 +INT64_MAX655360 +INT64_MIN655360 +INT64_WIDTH655360 +INT8_C131072(c)0 +INT8_MAX655360 +INT8_MIN655360 +INT8_WIDTH655360 +INTMAX_C131072(c)0 +INTMAX_MAX655360 +INTMAX_MIN655360 +INTMAX_WIDTH655360 +INTPTR_MAX655360 +INTPTR_MIN655360 +INTPTR_WIDTH655360 +INT_FAST16_MAX655360 +INT_FAST16_MIN655360 +INT_FAST16_WIDTH655360 +INT_FAST32_MAX655360 +INT_FAST32_MIN655360 +INT_FAST32_WIDTH655360 +INT_FAST64_MAX655360 +INT_FAST64_MIN655360 +INT_FAST64_WIDTH655360 +INT_FAST8_MAX655360 +INT_FAST8_MIN655360 +INT_FAST8_WIDTH655360 +INT_LEAST16_MAX655360 +INT_LEAST16_MIN655360 +INT_LEAST16_WIDTH655360 +INT_LEAST32_MAX655360 +INT_LEAST32_MIN655360 +INT_LEAST32_WIDTH655360 +INT_LEAST64_MAX655360 +INT_LEAST64_MIN655360 +INT_LEAST64_WIDTH655360 +INT_LEAST8_MAX655360 +INT_LEAST8_MIN655360 +INT_LEAST8_WIDTH655360 +IS_ADC_ALL_INSTANCE131072(INSTANCE)0 +IS_ADC_COMMON_INSTANCE131072(INSTANCE)0 +IS_CAN_ALL_INSTANCE131072(INSTANCE)0 +IS_CEC_ALL_INSTANCE131072(INSTANCE)0 +IS_CRC_ALL_INSTANCE131072(INSTANCE)0 +IS_DMA_ALL_INSTANCE131072(INSTANCE)0 +IS_FUNCTIONAL_STATE131072(STATE)0 +IS_GPIO_AF_INSTANCE131072(INSTANCE)0 +IS_GPIO_ALL_INSTANCE131072(INSTANCE)0 +IS_GPIO_LOCK_INSTANCE131072(INSTANCE)0 +IS_I2C_ALL_INSTANCE131072(INSTANCE)0 +IS_I2S_ALL_INSTANCE131072(INSTANCE)0 +IS_IRDA_INSTANCE131072(INSTANCE)0 +IS_IWDG_ALL_INSTANCE131072(INSTANCE)0 +IS_RTC_ALL_INSTANCE131072(INSTANCE)0 +IS_SMARTCARD_INSTANCE131072(INSTANCE)0 +IS_SMBUS_ALL_INSTANCE131072(INSTANCE)0 +IS_SPI_ALL_INSTANCE131072(INSTANCE)0 +IS_TIM_32B_COUNTER_INSTANCE131072(INSTANCE)0 +IS_TIM_BKIN2_INSTANCE131072(INSTANCE)0 +IS_TIM_BREAK_INSTANCE131072(INSTANCE)0 +IS_TIM_CC1_INSTANCE131072(INSTANCE)0 +IS_TIM_CC2_INSTANCE131072(INSTANCE)0 +IS_TIM_CC3_INSTANCE131072(INSTANCE)0 +IS_TIM_CC4_INSTANCE131072(INSTANCE)0 +IS_TIM_CC5_INSTANCE131072(INSTANCE)0 +IS_TIM_CC6_INSTANCE131072(INSTANCE)0 +IS_TIM_CCXN_INSTANCE131072(INSTANCE,CHANNEL)0 +IS_TIM_CCX_INSTANCE131072(INSTANCE,CHANNEL)0 +IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE131072(INSTANCE)0 +IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE131072(INSTANCE)0 +IS_TIM_CLOCKSOURCE_ITRX_INSTANCE131072(INSTANCE)0 +IS_TIM_CLOCKSOURCE_TIX_INSTANCE131072(INSTANCE)0 +IS_TIM_CLOCK_DIVISION_INSTANCE131072(INSTANCE)0 +IS_TIM_CLOCK_SELECT_INSTANCE131072(INSTANCE)0 +IS_TIM_COMMUTATION_EVENT_INSTANCE131072(INSTANCE)0 +IS_TIM_COUNTER_MODE_SELECT_INSTANCE131072(INSTANCE)0 +IS_TIM_DMABURST_INSTANCE131072(INSTANCE)0 +IS_TIM_DMA_CC_INSTANCE131072(INSTANCE)0 +IS_TIM_DMA_INSTANCE131072(INSTANCE)0 +IS_TIM_ENCODER_INTERFACE_INSTANCE131072(INSTANCE)0 +IS_TIM_HALL_INTERFACE_INSTANCE131072(INSTANCE)0 +IS_TIM_INSTANCE131072(INSTANCE)0 +IS_TIM_MASTER_INSTANCE131072(INSTANCE)0 +IS_TIM_OCXREF_CLEAR_INSTANCE131072(INSTANCE)0 +IS_TIM_REMAP_INSTANCE131072(INSTANCE)0 +IS_TIM_REPETITION_COUNTER_INSTANCE131072(INSTANCE)0 +IS_TIM_SLAVE_INSTANCE131072(INSTANCE)0 +IS_TIM_SYNCHRO_INSTANCE131072(INSTANCE)0 +IS_TIM_TRGO2_INSTANCE131072(INSTANCE)0 +IS_TIM_XOR_INSTANCE131072(INSTANCE)0 +IS_TSC_ALL_INSTANCE131072(INSTANCE)0 +IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE131072(INSTANCE)0 +IS_UART_DRIVER_ENABLE_INSTANCE131072(INSTANCE)0 +IS_UART_HALFDUPLEX_INSTANCE131072(INSTANCE)0 +IS_UART_HWFLOW_INSTANCE131072(INSTANCE)0 +IS_UART_INSTANCE131072(INSTANCE)0 +IS_UART_LIN_INSTANCE131072(INSTANCE)0 +IS_UART_WAKEUP_INSTANCE131072(INSTANCE)0 +IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE131072(INSTANCE)0 +IS_USART_INSTANCE131072(INSTANCE)0 +IS_USB_ALL_INSTANCE131072(INSTANCE)0 +IS_WWDG_ALL_INSTANCE131072(INSTANCE)0 +IWDG655360 +IWDG_BASE655360 +IWDG_KR_KEY655360 +IWDG_PR_PR655360 +IWDG_PR_PR_0655360 +IWDG_PR_PR_1655360 +IWDG_PR_PR_2655360 +IWDG_REFRESH655360 +IWDG_RLR_RL655360 +IWDG_SR_PVU655360 +IWDG_SR_RVU655360 +IWDG_SR_WVU655360 +IWDG_START655360 +IWDG_WINR_WIN655360 +IWDG_WRITE_ACCESS655360 +LED0_pin655360 +LED0_port655360 +LED1_pin655360 +LED1_port655360 +LED_blink131072(x)0 +LED_off131072(x)0 +LED_on131072(x)0 +LINE_BUSY4anon_enum_00 +MODIFY_REG131072(REG,CLEARMASK,SETMASK)0 +MSG131072(str)0 +NULL655360 +NVIC655360 +NVIC_BASE655360 +OB655360 +OB_BASE655360 +OB_RDP_RDP655360 +OB_RDP_nRDP655360 +OB_USER_USER655360 +OB_USER_nUSER655360 +OB_WRP0_WRP0655360 +OB_WRP0_nWRP0655360 +OB_WRP1_WRP1655360 +OB_WRP1_nWRP1655360 +OB_WRP2_WRP2655360 +OB_WRP2_nWRP2655360 +OB_WRP3_WRP3655360 +OB_WRP3_nWRP3655360 +PERIPH_BASE655360 +PTRDIFF_MAX655360 +PTRDIFF_MIN655360 +PTRDIFF_WIDTH655360 +PVD_IRQHandler655360 +PVD_IRQn655360 +PWR655360 +PWR_BASE655360 +PWR_CR_CSBF655360 +PWR_CR_CWUF655360 +PWR_CR_DBP655360 +PWR_CR_LPDS655360 +PWR_CR_PDDS655360 +PWR_CR_PLS655360 +PWR_CR_PLS_0655360 +PWR_CR_PLS_1655360 +PWR_CR_PLS_2655360 +PWR_CR_PLS_LEV0655360 +PWR_CR_PLS_LEV1655360 +PWR_CR_PLS_LEV2655360 +PWR_CR_PLS_LEV3655360 +PWR_CR_PLS_LEV4655360 +PWR_CR_PLS_LEV5655360 +PWR_CR_PLS_LEV6655360 +PWR_CR_PLS_LEV7655360 +PWR_CR_PVDE655360 +PWR_CSR_EWUP1655360 +PWR_CSR_EWUP2655360 +PWR_CSR_EWUP3655360 +PWR_CSR_EWUP4655360 +PWR_CSR_EWUP5655360 +PWR_CSR_EWUP6655360 +PWR_CSR_EWUP7655360 +PWR_CSR_EWUP8655360 +PWR_CSR_PVDO655360 +PWR_CSR_SBF655360 +PWR_CSR_VREFINTRDYF655360 +PWR_CSR_WUF655360 +RCC655360 +RCC_AHBENR_CRCEN655360 +RCC_AHBENR_DMA1EN655360 +RCC_AHBENR_DMAEN655360 +RCC_AHBENR_FLITFEN655360 +RCC_AHBENR_GPIOAEN655360 +RCC_AHBENR_GPIOBEN655360 +RCC_AHBENR_GPIOCEN655360 +RCC_AHBENR_GPIOFEN655360 +RCC_AHBENR_SRAMEN655360 +RCC_AHBENR_TSCEN655360 +RCC_AHBENR_TSEN655360 +RCC_AHBRSTR_GPIOARST655360 +RCC_AHBRSTR_GPIOBRST655360 +RCC_AHBRSTR_GPIOCRST655360 +RCC_AHBRSTR_GPIOFRST655360 +RCC_AHBRSTR_TSCRST655360 +RCC_AHBRSTR_TSRST655360 +RCC_APB1ENR_CANEN655360 +RCC_APB1ENR_CECEN655360 +RCC_APB1ENR_CRSEN655360 +RCC_APB1ENR_DACEN655360 +RCC_APB1ENR_I2C1EN655360 +RCC_APB1ENR_I2C2EN655360 +RCC_APB1ENR_PWREN655360 +RCC_APB1ENR_SPI2EN655360 +RCC_APB1ENR_TIM14EN655360 +RCC_APB1ENR_TIM2EN655360 +RCC_APB1ENR_TIM3EN655360 +RCC_APB1ENR_USART2EN655360 +RCC_APB1ENR_USART3EN655360 +RCC_APB1ENR_USART4EN655360 +RCC_APB1ENR_USBEN655360 +RCC_APB1ENR_WWDGEN655360 +RCC_APB1RSTR_CANRST655360 +RCC_APB1RSTR_CECRST655360 +RCC_APB1RSTR_CRSRST655360 +RCC_APB1RSTR_DACRST655360 +RCC_APB1RSTR_I2C1RST655360 +RCC_APB1RSTR_I2C2RST655360 +RCC_APB1RSTR_PWRRST655360 +RCC_APB1RSTR_SPI2RST655360 +RCC_APB1RSTR_TIM14RST655360 +RCC_APB1RSTR_TIM2RST655360 +RCC_APB1RSTR_TIM3RST655360 +RCC_APB1RSTR_USART2RST655360 +RCC_APB1RSTR_USART3RST655360 +RCC_APB1RSTR_USART4RST655360 +RCC_APB1RSTR_USBRST655360 +RCC_APB1RSTR_WWDGRST655360 +RCC_APB2ENR_ADC1EN655360 +RCC_APB2ENR_ADCEN655360 +RCC_APB2ENR_DBGMCUEN655360 +RCC_APB2ENR_SPI1EN655360 +RCC_APB2ENR_SYSCFGCOMPEN655360 +RCC_APB2ENR_SYSCFGEN655360 +RCC_APB2ENR_TIM16EN655360 +RCC_APB2ENR_TIM17EN655360 +RCC_APB2ENR_TIM1EN655360 +RCC_APB2ENR_USART1EN655360 +RCC_APB2RSTR_ADC1RST655360 +RCC_APB2RSTR_ADCRST655360 +RCC_APB2RSTR_DBGMCURST655360 +RCC_APB2RSTR_SPI1RST655360 +RCC_APB2RSTR_SYSCFGRST655360 +RCC_APB2RSTR_TIM16RST655360 +RCC_APB2RSTR_TIM17RST655360 +RCC_APB2RSTR_TIM1RST655360 +RCC_APB2RSTR_USART1RST655360 +RCC_BASE655360 +RCC_BDCR_BDRST655360 +RCC_BDCR_LSEBYP655360 +RCC_BDCR_LSEDRV655360 +RCC_BDCR_LSEDRV_0655360 +RCC_BDCR_LSEDRV_1655360 +RCC_BDCR_LSEON655360 +RCC_BDCR_LSERDY655360 +RCC_BDCR_RTCEN655360 +RCC_BDCR_RTCSEL655360 +RCC_BDCR_RTCSEL_0655360 +RCC_BDCR_RTCSEL_1655360 +RCC_BDCR_RTCSEL_HSE655360 +RCC_BDCR_RTCSEL_LSE655360 +RCC_BDCR_RTCSEL_LSI655360 +RCC_BDCR_RTCSEL_NOCLOCK655360 +RCC_CFGR2_PREDIV655360 +RCC_CFGR2_PREDIV_0655360 +RCC_CFGR2_PREDIV_1655360 +RCC_CFGR2_PREDIV_2655360 +RCC_CFGR2_PREDIV_3655360 +RCC_CFGR2_PREDIV_DIV1655360 +RCC_CFGR2_PREDIV_DIV10655360 +RCC_CFGR2_PREDIV_DIV11655360 +RCC_CFGR2_PREDIV_DIV12655360 +RCC_CFGR2_PREDIV_DIV13655360 +RCC_CFGR2_PREDIV_DIV14655360 +RCC_CFGR2_PREDIV_DIV15655360 +RCC_CFGR2_PREDIV_DIV16655360 +RCC_CFGR2_PREDIV_DIV2655360 +RCC_CFGR2_PREDIV_DIV3655360 +RCC_CFGR2_PREDIV_DIV4655360 +RCC_CFGR2_PREDIV_DIV5655360 +RCC_CFGR2_PREDIV_DIV6655360 +RCC_CFGR2_PREDIV_DIV7655360 +RCC_CFGR2_PREDIV_DIV8655360 +RCC_CFGR2_PREDIV_DIV9655360 +RCC_CFGR3_CECSW655360 +RCC_CFGR3_CECSW_HSI_DIV244655360 +RCC_CFGR3_CECSW_LSE655360 +RCC_CFGR3_I2C1SW655360 +RCC_CFGR3_I2C1SW_HSI655360 +RCC_CFGR3_I2C1SW_SYSCLK655360 +RCC_CFGR3_USART1SW655360 +RCC_CFGR3_USART1SW_0655360 +RCC_CFGR3_USART1SW_1655360 +RCC_CFGR3_USART1SW_HSI655360 +RCC_CFGR3_USART1SW_LSE655360 +RCC_CFGR3_USART1SW_PCLK655360 +RCC_CFGR3_USART1SW_SYSCLK655360 +RCC_CFGR3_USART2SW655360 +RCC_CFGR3_USART2SW_0655360 +RCC_CFGR3_USART2SW_1655360 +RCC_CFGR3_USART2SW_HSI655360 +RCC_CFGR3_USART2SW_LSE655360 +RCC_CFGR3_USART2SW_PCLK655360 +RCC_CFGR3_USART2SW_SYSCLK655360 +RCC_CFGR3_USBSW655360 +RCC_CFGR3_USBSW_HSI48655360 +RCC_CFGR3_USBSW_PLLCLK655360 +RCC_CFGR_ADCPRE655360 +RCC_CFGR_ADCPRE_DIV2655360 +RCC_CFGR_ADCPRE_DIV4655360 +RCC_CFGR_HPRE655360 +RCC_CFGR_HPRE_0655360 +RCC_CFGR_HPRE_1655360 +RCC_CFGR_HPRE_2655360 +RCC_CFGR_HPRE_3655360 +RCC_CFGR_HPRE_DIV1655360 +RCC_CFGR_HPRE_DIV128655360 +RCC_CFGR_HPRE_DIV16655360 +RCC_CFGR_HPRE_DIV2655360 +RCC_CFGR_HPRE_DIV256655360 +RCC_CFGR_HPRE_DIV4655360 +RCC_CFGR_HPRE_DIV512655360 +RCC_CFGR_HPRE_DIV64655360 +RCC_CFGR_HPRE_DIV8655360 +RCC_CFGR_MCO655360 +RCC_CFGR_MCOPRE655360 +RCC_CFGR_MCOPRE_DIV1655360 +RCC_CFGR_MCOPRE_DIV128655360 +RCC_CFGR_MCOPRE_DIV16655360 +RCC_CFGR_MCOPRE_DIV2655360 +RCC_CFGR_MCOPRE_DIV32655360 +RCC_CFGR_MCOPRE_DIV4655360 +RCC_CFGR_MCOPRE_DIV64655360 +RCC_CFGR_MCOPRE_DIV8655360 +RCC_CFGR_MCO_0655360 +RCC_CFGR_MCO_1655360 +RCC_CFGR_MCO_2655360 +RCC_CFGR_MCO_3655360 +RCC_CFGR_MCO_HSE655360 +RCC_CFGR_MCO_HSI655360 +RCC_CFGR_MCO_HSI14655360 +RCC_CFGR_MCO_HSI48655360 +RCC_CFGR_MCO_LSE655360 +RCC_CFGR_MCO_LSI655360 +RCC_CFGR_MCO_NOCLOCK655360 +RCC_CFGR_MCO_PLL655360 +RCC_CFGR_MCO_SYSCLK655360 +RCC_CFGR_PLLMUL655360 +RCC_CFGR_PLLMUL10655360 +RCC_CFGR_PLLMUL11655360 +RCC_CFGR_PLLMUL12655360 +RCC_CFGR_PLLMUL13655360 +RCC_CFGR_PLLMUL14655360 +RCC_CFGR_PLLMUL15655360 +RCC_CFGR_PLLMUL16655360 +RCC_CFGR_PLLMUL2655360 +RCC_CFGR_PLLMUL3655360 +RCC_CFGR_PLLMUL4655360 +RCC_CFGR_PLLMUL5655360 +RCC_CFGR_PLLMUL6655360 +RCC_CFGR_PLLMUL7655360 +RCC_CFGR_PLLMUL8655360 +RCC_CFGR_PLLMUL9655360 +RCC_CFGR_PLLMUL_0655360 +RCC_CFGR_PLLMUL_1655360 +RCC_CFGR_PLLMUL_2655360 +RCC_CFGR_PLLMUL_3655360 +RCC_CFGR_PLLNODIV655360 +RCC_CFGR_PLLSRC655360 +RCC_CFGR_PLLSRC_HSE_PREDIV655360 +RCC_CFGR_PLLSRC_HSI48_PREDIV655360 +RCC_CFGR_PLLSRC_HSI_DIV2655360 +RCC_CFGR_PLLSRC_HSI_PREDIV655360 +RCC_CFGR_PLLXTPRE655360 +RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1655360 +RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2655360 +RCC_CFGR_PPRE655360 +RCC_CFGR_PPRE_0655360 +RCC_CFGR_PPRE_1655360 +RCC_CFGR_PPRE_2655360 +RCC_CFGR_PPRE_DIV1655360 +RCC_CFGR_PPRE_DIV16655360 +RCC_CFGR_PPRE_DIV2655360 +RCC_CFGR_PPRE_DIV4655360 +RCC_CFGR_PPRE_DIV8655360 +RCC_CFGR_SW655360 +RCC_CFGR_SWS655360 +RCC_CFGR_SWS_0655360 +RCC_CFGR_SWS_1655360 +RCC_CFGR_SWS_HSE655360 +RCC_CFGR_SWS_HSI655360 +RCC_CFGR_SWS_HSI48655360 +RCC_CFGR_SWS_PLL655360 +RCC_CFGR_SW_0655360 +RCC_CFGR_SW_1655360 +RCC_CFGR_SW_HSE655360 +RCC_CFGR_SW_HSI655360 +RCC_CFGR_SW_HSI48655360 +RCC_CFGR_SW_PLL655360 +RCC_CFGR_USBPRE655360 +RCC_CIR_CSSC655360 +RCC_CIR_CSSF655360 +RCC_CIR_HSERDYC655360 +RCC_CIR_HSERDYF655360 +RCC_CIR_HSERDYIE655360 +RCC_CIR_HSI14RDYC655360 +RCC_CIR_HSI14RDYF655360 +RCC_CIR_HSI14RDYIE655360 +RCC_CIR_HSI48RDYC655360 +RCC_CIR_HSI48RDYF655360 +RCC_CIR_HSI48RDYIE655360 +RCC_CIR_HSIRDYC655360 +RCC_CIR_HSIRDYF655360 +RCC_CIR_HSIRDYIE655360 +RCC_CIR_LSERDYC655360 +RCC_CIR_LSERDYF655360 +RCC_CIR_LSERDYIE655360 +RCC_CIR_LSIRDYC655360 +RCC_CIR_LSIRDYF655360 +RCC_CIR_LSIRDYIE655360 +RCC_CIR_PLLRDYC655360 +RCC_CIR_PLLRDYF655360 +RCC_CIR_PLLRDYIE655360 +RCC_CR2_HSI14CAL655360 +RCC_CR2_HSI14DIS655360 +RCC_CR2_HSI14ON655360 +RCC_CR2_HSI14RDY655360 +RCC_CR2_HSI14TRIM655360 +RCC_CR2_HSI48CAL655360 +RCC_CR2_HSI48ON655360 +RCC_CR2_HSI48RDY655360 +RCC_CR_CSSON655360 +RCC_CR_HSEBYP655360 +RCC_CR_HSEON655360 +RCC_CR_HSERDY655360 +RCC_CR_HSICAL655360 +RCC_CR_HSICAL_0655360 +RCC_CR_HSICAL_1655360 +RCC_CR_HSICAL_2655360 +RCC_CR_HSICAL_3655360 +RCC_CR_HSICAL_4655360 +RCC_CR_HSICAL_5655360 +RCC_CR_HSICAL_6655360 +RCC_CR_HSICAL_7655360 +RCC_CR_HSION655360 +RCC_CR_HSIRDY655360 +RCC_CR_HSITRIM655360 +RCC_CR_HSITRIM_0655360 +RCC_CR_HSITRIM_1655360 +RCC_CR_HSITRIM_2655360 +RCC_CR_HSITRIM_3655360 +RCC_CR_HSITRIM_4655360 +RCC_CR_PLLON655360 +RCC_CR_PLLRDY655360 +RCC_CSR_IWDGRSTF655360 +RCC_CSR_LPWRRSTF655360 +RCC_CSR_LSION655360 +RCC_CSR_LSIRDY655360 +RCC_CSR_OBL655360 +RCC_CSR_OBLRSTF655360 +RCC_CSR_PINRSTF655360 +RCC_CSR_PORRSTF655360 +RCC_CSR_RMVF655360 +RCC_CSR_SFTRSTF655360 +RCC_CSR_V18PWRRSTF655360 +RCC_CSR_WWDGRSTF655360 +RCC_IRQHandler655360 +RCC_IRQn655360 +READ_BIT131072(REG,BIT)0 +READ_CAN_INV_ADDR131072()0 +READ_REG131072(REG)0 +RTC655360 +RTC_ALRMAR_DT655360 +RTC_ALRMAR_DT_0655360 +RTC_ALRMAR_DT_1655360 +RTC_ALRMAR_DU655360 +RTC_ALRMAR_DU_0655360 +RTC_ALRMAR_DU_1655360 +RTC_ALRMAR_DU_2655360 +RTC_ALRMAR_DU_3655360 +RTC_ALRMAR_HT655360 +RTC_ALRMAR_HT_0655360 +RTC_ALRMAR_HT_1655360 +RTC_ALRMAR_HU655360 +RTC_ALRMAR_HU_0655360 +RTC_ALRMAR_HU_1655360 +RTC_ALRMAR_HU_2655360 +RTC_ALRMAR_HU_3655360 +RTC_ALRMAR_MNT655360 +RTC_ALRMAR_MNT_0655360 +RTC_ALRMAR_MNT_1655360 +RTC_ALRMAR_MNT_2655360 +RTC_ALRMAR_MNU655360 +RTC_ALRMAR_MNU_0655360 +RTC_ALRMAR_MNU_1655360 +RTC_ALRMAR_MNU_2655360 +RTC_ALRMAR_MNU_3655360 +RTC_ALRMAR_MSK1655360 +RTC_ALRMAR_MSK2655360 +RTC_ALRMAR_MSK3655360 +RTC_ALRMAR_MSK4655360 +RTC_ALRMAR_PM655360 +RTC_ALRMAR_ST655360 +RTC_ALRMAR_ST_0655360 +RTC_ALRMAR_ST_1655360 +RTC_ALRMAR_ST_2655360 +RTC_ALRMAR_SU655360 +RTC_ALRMAR_SU_0655360 +RTC_ALRMAR_SU_1655360 +RTC_ALRMAR_SU_2655360 +RTC_ALRMAR_SU_3655360 +RTC_ALRMAR_WDSEL655360 +RTC_ALRMASSR_MASKSS655360 +RTC_ALRMASSR_MASKSS_0655360 +RTC_ALRMASSR_MASKSS_1655360 +RTC_ALRMASSR_MASKSS_2655360 +RTC_ALRMASSR_MASKSS_3655360 +RTC_ALRMASSR_SS655360 +RTC_BASE655360 +RTC_BKP0R655360 +RTC_BKP1R655360 +RTC_BKP2R655360 +RTC_BKP3R655360 +RTC_BKP4R655360 +RTC_BKP_NUMBER655360 +RTC_CALR_CALM655360 +RTC_CALR_CALM_0655360 +RTC_CALR_CALM_1655360 +RTC_CALR_CALM_2655360 +RTC_CALR_CALM_3655360 +RTC_CALR_CALM_4655360 +RTC_CALR_CALM_5655360 +RTC_CALR_CALM_6655360 +RTC_CALR_CALM_7655360 +RTC_CALR_CALM_8655360 +RTC_CALR_CALP655360 +RTC_CALR_CALW16655360 +RTC_CALR_CALW8655360 +RTC_CR_ADD1H655360 +RTC_CR_ALRAE655360 +RTC_CR_ALRAIE655360 +RTC_CR_BCK655360 +RTC_CR_BYPSHAD655360 +RTC_CR_COE655360 +RTC_CR_COSEL655360 +RTC_CR_FMT655360 +RTC_CR_OSEL655360 +RTC_CR_OSEL_0655360 +RTC_CR_OSEL_1655360 +RTC_CR_POL655360 +RTC_CR_REFCKON655360 +RTC_CR_SUB1H655360 +RTC_CR_TSE655360 +RTC_CR_TSEDGE655360 +RTC_CR_TSIE655360 +RTC_DR_DT655360 +RTC_DR_DT_0655360 +RTC_DR_DT_1655360 +RTC_DR_DU655360 +RTC_DR_DU_0655360 +RTC_DR_DU_1655360 +RTC_DR_DU_2655360 +RTC_DR_DU_3655360 +RTC_DR_MT655360 +RTC_DR_MU655360 +RTC_DR_MU_0655360 +RTC_DR_MU_1655360 +RTC_DR_MU_2655360 +RTC_DR_MU_3655360 +RTC_DR_WDU655360 +RTC_DR_WDU_0655360 +RTC_DR_WDU_1655360 +RTC_DR_WDU_2655360 +RTC_DR_YT655360 +RTC_DR_YT_0655360 +RTC_DR_YT_1655360 +RTC_DR_YT_2655360 +RTC_DR_YT_3655360 +RTC_DR_YU655360 +RTC_DR_YU_0655360 +RTC_DR_YU_1655360 +RTC_DR_YU_2655360 +RTC_DR_YU_3655360 +RTC_ISR_ALRAF655360 +RTC_ISR_ALRAWF655360 +RTC_ISR_INIT655360 +RTC_ISR_INITF655360 +RTC_ISR_INITS655360 +RTC_ISR_RECALPF655360 +RTC_ISR_RSF655360 +RTC_ISR_SHPF655360 +RTC_ISR_TAMP1F655360 +RTC_ISR_TAMP2F655360 +RTC_ISR_TSF655360 +RTC_ISR_TSOVF655360 +RTC_PRER_PREDIV_A655360 +RTC_PRER_PREDIV_S655360 +RTC_SHIFTR_ADD1S655360 +RTC_SHIFTR_SUBFS655360 +RTC_SSR_SS655360 +RTC_TAFCR_ALARMOUTTYPE655360 +RTC_TAFCR_TAMP1E655360 +RTC_TAFCR_TAMP1TRG655360 +RTC_TAFCR_TAMP2E655360 +RTC_TAFCR_TAMP2TRG655360 +RTC_TAFCR_TAMPFLT655360 +RTC_TAFCR_TAMPFLT_0655360 +RTC_TAFCR_TAMPFLT_1655360 +RTC_TAFCR_TAMPFREQ655360 +RTC_TAFCR_TAMPFREQ_0655360 +RTC_TAFCR_TAMPFREQ_1655360 +RTC_TAFCR_TAMPFREQ_2655360 +RTC_TAFCR_TAMPIE655360 +RTC_TAFCR_TAMPPRCH655360 +RTC_TAFCR_TAMPPRCH_0655360 +RTC_TAFCR_TAMPPRCH_1655360 +RTC_TAFCR_TAMPPUDIS655360 +RTC_TAFCR_TAMPTS655360 +RTC_TR_HT655360 +RTC_TR_HT_0655360 +RTC_TR_HT_1655360 +RTC_TR_HU655360 +RTC_TR_HU_0655360 +RTC_TR_HU_1655360 +RTC_TR_HU_2655360 +RTC_TR_HU_3655360 +RTC_TR_MNT655360 +RTC_TR_MNT_0655360 +RTC_TR_MNT_1655360 +RTC_TR_MNT_2655360 +RTC_TR_MNU655360 +RTC_TR_MNU_0655360 +RTC_TR_MNU_1655360 +RTC_TR_MNU_2655360 +RTC_TR_MNU_3655360 +RTC_TR_PM655360 +RTC_TR_ST655360 +RTC_TR_ST_0655360 +RTC_TR_ST_1655360 +RTC_TR_ST_2655360 +RTC_TR_SU655360 +RTC_TR_SU_0655360 +RTC_TR_SU_1655360 +RTC_TR_SU_2655360 +RTC_TR_SU_3655360 +RTC_TSDR_DT655360 +RTC_TSDR_DT_0655360 +RTC_TSDR_DT_1655360 +RTC_TSDR_DU655360 +RTC_TSDR_DU_0655360 +RTC_TSDR_DU_1655360 +RTC_TSDR_DU_2655360 +RTC_TSDR_DU_3655360 +RTC_TSDR_MT655360 +RTC_TSDR_MU655360 +RTC_TSDR_MU_0655360 +RTC_TSDR_MU_1655360 +RTC_TSDR_MU_2655360 +RTC_TSDR_MU_3655360 +RTC_TSDR_WDU655360 +RTC_TSDR_WDU_0655360 +RTC_TSDR_WDU_1655360 +RTC_TSDR_WDU_2655360 +RTC_TSSSR_SS655360 +RTC_TSTR_HT655360 +RTC_TSTR_HT_0655360 +RTC_TSTR_HT_1655360 +RTC_TSTR_HU655360 +RTC_TSTR_HU_0655360 +RTC_TSTR_HU_1655360 +RTC_TSTR_HU_2655360 +RTC_TSTR_HU_3655360 +RTC_TSTR_MNT655360 +RTC_TSTR_MNT_0655360 +RTC_TSTR_MNT_1655360 +RTC_TSTR_MNT_2655360 +RTC_TSTR_MNU655360 +RTC_TSTR_MNU_0655360 +RTC_TSTR_MNU_1655360 +RTC_TSTR_MNU_2655360 +RTC_TSTR_MNU_3655360 +RTC_TSTR_PM655360 +RTC_TSTR_ST655360 +RTC_TSTR_ST_0655360 +RTC_TSTR_ST_1655360 +RTC_TSTR_ST_2655360 +RTC_TSTR_SU655360 +RTC_TSTR_SU_0655360 +RTC_TSTR_SU_1655360 +RTC_TSTR_SU_2655360 +RTC_TSTR_SU_3655360 +RTC_WPR_KEY655360 +SCB655360 +SCB_AIRCR_ENDIANESS_Msk655360 +SCB_AIRCR_ENDIANESS_Pos655360 +SCB_AIRCR_SYSRESETREQ_Msk655360 +SCB_AIRCR_SYSRESETREQ_Pos655360 +SCB_AIRCR_VECTCLRACTIVE_Msk655360 +SCB_AIRCR_VECTCLRACTIVE_Pos655360 +SCB_AIRCR_VECTKEYSTAT_Msk655360 +SCB_AIRCR_VECTKEYSTAT_Pos655360 +SCB_AIRCR_VECTKEY_Msk655360 +SCB_AIRCR_VECTKEY_Pos655360 +SCB_BASE655360 +SCB_CCR_STKALIGN_Msk655360 +SCB_CCR_STKALIGN_Pos655360 +SCB_CCR_UNALIGN_TRP_Msk655360 +SCB_CCR_UNALIGN_TRP_Pos655360 +SCB_CPUID_ARCHITECTURE_Msk655360 +SCB_CPUID_ARCHITECTURE_Pos655360 +SCB_CPUID_IMPLEMENTER_Msk655360 +SCB_CPUID_IMPLEMENTER_Pos655360 +SCB_CPUID_PARTNO_Msk655360 +SCB_CPUID_PARTNO_Pos655360 +SCB_CPUID_REVISION_Msk655360 +SCB_CPUID_REVISION_Pos655360 +SCB_CPUID_VARIANT_Msk655360 +SCB_CPUID_VARIANT_Pos655360 +SCB_ICSR_ISRPENDING_Msk655360 +SCB_ICSR_ISRPENDING_Pos655360 +SCB_ICSR_ISRPREEMPT_Msk655360 +SCB_ICSR_ISRPREEMPT_Pos655360 +SCB_ICSR_NMIPENDSET_Msk655360 +SCB_ICSR_NMIPENDSET_Pos655360 +SCB_ICSR_PENDSTCLR_Msk655360 +SCB_ICSR_PENDSTCLR_Pos655360 +SCB_ICSR_PENDSTSET_Msk655360 +SCB_ICSR_PENDSTSET_Pos655360 +SCB_ICSR_PENDSVCLR_Msk655360 +SCB_ICSR_PENDSVCLR_Pos655360 +SCB_ICSR_PENDSVSET_Msk655360 +SCB_ICSR_PENDSVSET_Pos655360 +SCB_ICSR_VECTACTIVE_Msk655360 +SCB_ICSR_VECTACTIVE_Pos655360 +SCB_ICSR_VECTPENDING_Msk655360 +SCB_ICSR_VECTPENDING_Pos655360 +SCB_SCR_SEVONPEND_Msk655360 +SCB_SCR_SEVONPEND_Pos655360 +SCB_SCR_SLEEPDEEP_Msk655360 +SCB_SCR_SLEEPDEEP_Pos655360 +SCB_SCR_SLEEPONEXIT_Msk655360 +SCB_SCR_SLEEPONEXIT_Pos655360 +SCB_SHCSR_SVCALLPENDED_Msk655360 +SCB_SHCSR_SVCALLPENDED_Pos655360 +SCS_BASE655360 +SEND131072(str)0 +SET_BIT131072(REG,BIT)0 +SIG_ATOMIC_MAX655360 +SIG_ATOMIC_MIN655360 +SIG_ATOMIC_WIDTH655360 +SIZE_MAX655360 +SIZE_WIDTH655360 +SPI1655360 +SPI1_BASE655360 +SPI2655360 +SPI2_BASE655360 +SPI_CR1_BIDIMODE655360 +SPI_CR1_BIDIOE655360 +SPI_CR1_BR655360 +SPI_CR1_BR_0655360 +SPI_CR1_BR_1655360 +SPI_CR1_BR_2655360 +SPI_CR1_CPHA655360 +SPI_CR1_CPOL655360 +SPI_CR1_CRCEN655360 +SPI_CR1_CRCL655360 +SPI_CR1_CRCNEXT655360 +SPI_CR1_LSBFIRST655360 +SPI_CR1_MSTR655360 +SPI_CR1_RXONLY655360 +SPI_CR1_SPE655360 +SPI_CR1_SSI655360 +SPI_CR1_SSM655360 +SPI_CR2_DS655360 +SPI_CR2_DS_0655360 +SPI_CR2_DS_1655360 +SPI_CR2_DS_2655360 +SPI_CR2_DS_3655360 +SPI_CR2_ERRIE655360 +SPI_CR2_FRF655360 +SPI_CR2_FRXTH655360 +SPI_CR2_LDMARX655360 +SPI_CR2_LDMATX655360 +SPI_CR2_NSSP655360 +SPI_CR2_RXDMAEN655360 +SPI_CR2_RXNEIE655360 +SPI_CR2_SSOE655360 +SPI_CR2_TXDMAEN655360 +SPI_CR2_TXEIE655360 +SPI_CRCPR_CRCPOLY655360 +SPI_DR_DR655360 +SPI_I2SCFGR_CHLEN655360 +SPI_I2SCFGR_CKPOL655360 +SPI_I2SCFGR_DATLEN655360 +SPI_I2SCFGR_DATLEN_0655360 +SPI_I2SCFGR_DATLEN_1655360 +SPI_I2SCFGR_I2SCFG655360 +SPI_I2SCFGR_I2SCFG_0655360 +SPI_I2SCFGR_I2SCFG_1655360 +SPI_I2SCFGR_I2SE655360 +SPI_I2SCFGR_I2SMOD655360 +SPI_I2SCFGR_I2SSTD655360 +SPI_I2SCFGR_I2SSTD_0655360 +SPI_I2SCFGR_I2SSTD_1655360 +SPI_I2SCFGR_PCMSYNC655360 +SPI_I2SPR_I2SDIV655360 +SPI_I2SPR_MCKOE655360 +SPI_I2SPR_ODD655360 +SPI_RXCRCR_RXCRC655360 +SPI_SR_BSY655360 +SPI_SR_CHSIDE655360 +SPI_SR_CRCERR655360 +SPI_SR_FRE655360 +SPI_SR_FRLVL655360 +SPI_SR_FRLVL_0655360 +SPI_SR_FRLVL_1655360 +SPI_SR_FTLVL655360 +SPI_SR_FTLVL_0655360 +SPI_SR_FTLVL_1655360 +SPI_SR_MODF655360 +SPI_SR_OVR655360 +SPI_SR_RXNE655360 +SPI_SR_TXE655360 +SPI_SR_UDR655360 +SPI_TXCRCR_TXCRC655360 +SRAM_BASE655360 +STM32F0655360 +STM32F042x6655360 +STR131072(s)0 +STR_HELPER131072(s)0 +STR_TOO_LONG4anon_enum_00 +SYSCFG655360 +SYSCFG_BASE655360 +SYSCFG_CFGR1_ADC_DMA_RMP655360 +SYSCFG_CFGR1_DMA_RMP655360 +SYSCFG_CFGR1_I2C_FMP_I2C1655360 +SYSCFG_CFGR1_I2C_FMP_I2C2655360 +SYSCFG_CFGR1_I2C_FMP_PA10655360 +SYSCFG_CFGR1_I2C_FMP_PA9655360 +SYSCFG_CFGR1_I2C_FMP_PB6655360 +SYSCFG_CFGR1_I2C_FMP_PB7655360 +SYSCFG_CFGR1_I2C_FMP_PB8655360 +SYSCFG_CFGR1_I2C_FMP_PB9655360 +SYSCFG_CFGR1_MEM_MODE655360 +SYSCFG_CFGR1_MEM_MODE_0655360 +SYSCFG_CFGR1_MEM_MODE_1655360 +SYSCFG_CFGR1_PA11_PA12_RMP655360 +SYSCFG_CFGR1_TIM16_DMA_RMP655360 +SYSCFG_CFGR1_TIM17_DMA_RMP655360 +SYSCFG_CFGR1_USART1RX_DMA_RMP655360 +SYSCFG_CFGR1_USART1TX_DMA_RMP655360 +SYSCFG_CFGR2_LOCKUP_LOCK655360 +SYSCFG_CFGR2_PVD_LOCK655360 +SYSCFG_CFGR2_SRAM_PARITY_LOCK655360 +SYSCFG_CFGR2_SRAM_PE655360 +SYSCFG_CFGR2_SRAM_PEF655360 +SYSCFG_EXTICR1_EXTI0655360 +SYSCFG_EXTICR1_EXTI0_PA655360 +SYSCFG_EXTICR1_EXTI0_PB655360 +SYSCFG_EXTICR1_EXTI0_PC655360 +SYSCFG_EXTICR1_EXTI0_PD655360 +SYSCFG_EXTICR1_EXTI0_PE655360 +SYSCFG_EXTICR1_EXTI0_PF655360 +SYSCFG_EXTICR1_EXTI1655360 +SYSCFG_EXTICR1_EXTI1_PA655360 +SYSCFG_EXTICR1_EXTI1_PB655360 +SYSCFG_EXTICR1_EXTI1_PC655360 +SYSCFG_EXTICR1_EXTI1_PD655360 +SYSCFG_EXTICR1_EXTI1_PE655360 +SYSCFG_EXTICR1_EXTI1_PF655360 +SYSCFG_EXTICR1_EXTI2655360 +SYSCFG_EXTICR1_EXTI2_PA655360 +SYSCFG_EXTICR1_EXTI2_PB655360 +SYSCFG_EXTICR1_EXTI2_PC655360 +SYSCFG_EXTICR1_EXTI2_PD655360 +SYSCFG_EXTICR1_EXTI2_PE655360 +SYSCFG_EXTICR1_EXTI2_PF655360 +SYSCFG_EXTICR1_EXTI3655360 +SYSCFG_EXTICR1_EXTI3_PA655360 +SYSCFG_EXTICR1_EXTI3_PB655360 +SYSCFG_EXTICR1_EXTI3_PC655360 +SYSCFG_EXTICR1_EXTI3_PD655360 +SYSCFG_EXTICR1_EXTI3_PE655360 +SYSCFG_EXTICR1_EXTI3_PF655360 +SYSCFG_EXTICR2_EXTI4655360 +SYSCFG_EXTICR2_EXTI4_PA655360 +SYSCFG_EXTICR2_EXTI4_PB655360 +SYSCFG_EXTICR2_EXTI4_PC655360 +SYSCFG_EXTICR2_EXTI4_PD655360 +SYSCFG_EXTICR2_EXTI4_PE655360 +SYSCFG_EXTICR2_EXTI4_PF655360 +SYSCFG_EXTICR2_EXTI5655360 +SYSCFG_EXTICR2_EXTI5_PA655360 +SYSCFG_EXTICR2_EXTI5_PB655360 +SYSCFG_EXTICR2_EXTI5_PC655360 +SYSCFG_EXTICR2_EXTI5_PD655360 +SYSCFG_EXTICR2_EXTI5_PE655360 +SYSCFG_EXTICR2_EXTI5_PF655360 +SYSCFG_EXTICR2_EXTI6655360 +SYSCFG_EXTICR2_EXTI6_PA655360 +SYSCFG_EXTICR2_EXTI6_PB655360 +SYSCFG_EXTICR2_EXTI6_PC655360 +SYSCFG_EXTICR2_EXTI6_PD655360 +SYSCFG_EXTICR2_EXTI6_PE655360 +SYSCFG_EXTICR2_EXTI6_PF655360 +SYSCFG_EXTICR2_EXTI7655360 +SYSCFG_EXTICR2_EXTI7_PA655360 +SYSCFG_EXTICR2_EXTI7_PB655360 +SYSCFG_EXTICR2_EXTI7_PC655360 +SYSCFG_EXTICR2_EXTI7_PD655360 +SYSCFG_EXTICR2_EXTI7_PE655360 +SYSCFG_EXTICR2_EXTI7_PF655360 +SYSCFG_EXTICR3_EXTI10655360 +SYSCFG_EXTICR3_EXTI10_PA655360 +SYSCFG_EXTICR3_EXTI10_PB655360 +SYSCFG_EXTICR3_EXTI10_PC655360 +SYSCFG_EXTICR3_EXTI10_PD655360 +SYSCFG_EXTICR3_EXTI10_PE655360 +SYSCFG_EXTICR3_EXTI10_PF655360 +SYSCFG_EXTICR3_EXTI11655360 +SYSCFG_EXTICR3_EXTI11_PA655360 +SYSCFG_EXTICR3_EXTI11_PB655360 +SYSCFG_EXTICR3_EXTI11_PC655360 +SYSCFG_EXTICR3_EXTI11_PD655360 +SYSCFG_EXTICR3_EXTI11_PE655360 +SYSCFG_EXTICR3_EXTI8655360 +SYSCFG_EXTICR3_EXTI8_PA655360 +SYSCFG_EXTICR3_EXTI8_PB655360 +SYSCFG_EXTICR3_EXTI8_PC655360 +SYSCFG_EXTICR3_EXTI8_PD655360 +SYSCFG_EXTICR3_EXTI8_PE655360 +SYSCFG_EXTICR3_EXTI9655360 +SYSCFG_EXTICR3_EXTI9_PA655360 +SYSCFG_EXTICR3_EXTI9_PB655360 +SYSCFG_EXTICR3_EXTI9_PC655360 +SYSCFG_EXTICR3_EXTI9_PD655360 +SYSCFG_EXTICR3_EXTI9_PE655360 +SYSCFG_EXTICR3_EXTI9_PF655360 +SYSCFG_EXTICR4_EXTI12655360 +SYSCFG_EXTICR4_EXTI12_PA655360 +SYSCFG_EXTICR4_EXTI12_PB655360 +SYSCFG_EXTICR4_EXTI12_PC655360 +SYSCFG_EXTICR4_EXTI12_PD655360 +SYSCFG_EXTICR4_EXTI12_PE655360 +SYSCFG_EXTICR4_EXTI13655360 +SYSCFG_EXTICR4_EXTI13_PA655360 +SYSCFG_EXTICR4_EXTI13_PB655360 +SYSCFG_EXTICR4_EXTI13_PC655360 +SYSCFG_EXTICR4_EXTI13_PD655360 +SYSCFG_EXTICR4_EXTI13_PE655360 +SYSCFG_EXTICR4_EXTI14655360 +SYSCFG_EXTICR4_EXTI14_PA655360 +SYSCFG_EXTICR4_EXTI14_PB655360 +SYSCFG_EXTICR4_EXTI14_PC655360 +SYSCFG_EXTICR4_EXTI14_PD655360 +SYSCFG_EXTICR4_EXTI14_PE655360 +SYSCFG_EXTICR4_EXTI15655360 +SYSCFG_EXTICR4_EXTI15_PA655360 +SYSCFG_EXTICR4_EXTI15_PB655360 +SYSCFG_EXTICR4_EXTI15_PC655360 +SYSCFG_EXTICR4_EXTI15_PD655360 +SYSCFG_EXTICR4_EXTI15_PE655360 +StartHSE16()0inline void +StartHSI4816()0inline void +SysTick655360 +SysTick_BASE655360 +SysTick_CALIB_NOREF_Msk655360 +SysTick_CALIB_NOREF_Pos655360 +SysTick_CALIB_SKEW_Msk655360 +SysTick_CALIB_SKEW_Pos655360 +SysTick_CALIB_TENMS_Msk655360 +SysTick_CALIB_TENMS_Pos655360 +SysTick_CTRL_CLKSOURCE_Msk655360 +SysTick_CTRL_CLKSOURCE_Pos655360 +SysTick_CTRL_COUNTFLAG_Msk655360 +SysTick_CTRL_COUNTFLAG_Pos655360 +SysTick_CTRL_ENABLE_Msk655360 +SysTick_CTRL_ENABLE_Pos655360 +SysTick_CTRL_TICKINT_Msk655360 +SysTick_CTRL_TICKINT_Pos655360 +SysTick_LOAD_RELOAD_Msk655360 +SysTick_LOAD_RELOAD_Pos655360 +SysTick_VAL_CURRENT_Msk655360 +SysTick_VAL_CURRENT_Pos655360 +TARG_ID655360 +TEMP110_CAL_ADDR655360 +TEMP30_CAL_ADDR655360 +TIM1655360 +TIM14655360 +TIM14_BASE655360 +TIM14_OR_TI1_RMP655360 +TIM14_OR_TI1_RMP_0655360 +TIM14_OR_TI1_RMP_1655360 +TIM16655360 +TIM16_BASE655360 +TIM17655360 +TIM17_BASE655360 +TIM1_BASE655360 +TIM2655360 +TIM2_BASE655360 +TIM3655360 +TIM3_BASE655360 +TIMEOUT_MS655360 +TIM_ARR_ARR655360 +TIM_BDTR_AOE655360 +TIM_BDTR_BKE655360 +TIM_BDTR_BKP655360 +TIM_BDTR_DTG655360 +TIM_BDTR_DTG_0655360 +TIM_BDTR_DTG_1655360 +TIM_BDTR_DTG_2655360 +TIM_BDTR_DTG_3655360 +TIM_BDTR_DTG_4655360 +TIM_BDTR_DTG_5655360 +TIM_BDTR_DTG_6655360 +TIM_BDTR_DTG_7655360 +TIM_BDTR_LOCK655360 +TIM_BDTR_LOCK_0655360 +TIM_BDTR_LOCK_1655360 +TIM_BDTR_MOE655360 +TIM_BDTR_OSSI655360 +TIM_BDTR_OSSR655360 +TIM_CCER_CC1E655360 +TIM_CCER_CC1NE655360 +TIM_CCER_CC1NP655360 +TIM_CCER_CC1P655360 +TIM_CCER_CC2E655360 +TIM_CCER_CC2NE655360 +TIM_CCER_CC2NP655360 +TIM_CCER_CC2P655360 +TIM_CCER_CC3E655360 +TIM_CCER_CC3NE655360 +TIM_CCER_CC3NP655360 +TIM_CCER_CC3P655360 +TIM_CCER_CC4E655360 +TIM_CCER_CC4NP655360 +TIM_CCER_CC4P655360 +TIM_CCMR1_CC1S655360 +TIM_CCMR1_CC1S_0655360 +TIM_CCMR1_CC1S_1655360 +TIM_CCMR1_CC2S655360 +TIM_CCMR1_CC2S_0655360 +TIM_CCMR1_CC2S_1655360 +TIM_CCMR1_IC1F655360 +TIM_CCMR1_IC1F_0655360 +TIM_CCMR1_IC1F_1655360 +TIM_CCMR1_IC1F_2655360 +TIM_CCMR1_IC1F_3655360 +TIM_CCMR1_IC1PSC655360 +TIM_CCMR1_IC1PSC_0655360 +TIM_CCMR1_IC1PSC_1655360 +TIM_CCMR1_IC2F655360 +TIM_CCMR1_IC2F_0655360 +TIM_CCMR1_IC2F_1655360 +TIM_CCMR1_IC2F_2655360 +TIM_CCMR1_IC2F_3655360 +TIM_CCMR1_IC2PSC655360 +TIM_CCMR1_IC2PSC_0655360 +TIM_CCMR1_IC2PSC_1655360 +TIM_CCMR1_OC1CE655360 +TIM_CCMR1_OC1FE655360 +TIM_CCMR1_OC1M655360 +TIM_CCMR1_OC1M_0655360 +TIM_CCMR1_OC1M_1655360 +TIM_CCMR1_OC1M_2655360 +TIM_CCMR1_OC1PE655360 +TIM_CCMR1_OC2CE655360 +TIM_CCMR1_OC2FE655360 +TIM_CCMR1_OC2M655360 +TIM_CCMR1_OC2M_0655360 +TIM_CCMR1_OC2M_1655360 +TIM_CCMR1_OC2M_2655360 +TIM_CCMR1_OC2PE655360 +TIM_CCMR2_CC3S655360 +TIM_CCMR2_CC3S_0655360 +TIM_CCMR2_CC3S_1655360 +TIM_CCMR2_CC4S655360 +TIM_CCMR2_CC4S_0655360 +TIM_CCMR2_CC4S_1655360 +TIM_CCMR2_IC3F655360 +TIM_CCMR2_IC3F_0655360 +TIM_CCMR2_IC3F_1655360 +TIM_CCMR2_IC3F_2655360 +TIM_CCMR2_IC3F_3655360 +TIM_CCMR2_IC3PSC655360 +TIM_CCMR2_IC3PSC_0655360 +TIM_CCMR2_IC3PSC_1655360 +TIM_CCMR2_IC4F655360 +TIM_CCMR2_IC4F_0655360 +TIM_CCMR2_IC4F_1655360 +TIM_CCMR2_IC4F_2655360 +TIM_CCMR2_IC4F_3655360 +TIM_CCMR2_IC4PSC655360 +TIM_CCMR2_IC4PSC_0655360 +TIM_CCMR2_IC4PSC_1655360 +TIM_CCMR2_OC3CE655360 +TIM_CCMR2_OC3FE655360 +TIM_CCMR2_OC3M655360 +TIM_CCMR2_OC3M_0655360 +TIM_CCMR2_OC3M_1655360 +TIM_CCMR2_OC3M_2655360 +TIM_CCMR2_OC3PE655360 +TIM_CCMR2_OC4CE655360 +TIM_CCMR2_OC4FE655360 +TIM_CCMR2_OC4M655360 +TIM_CCMR2_OC4M_0655360 +TIM_CCMR2_OC4M_1655360 +TIM_CCMR2_OC4M_2655360 +TIM_CCMR2_OC4PE655360 +TIM_CCR1_CCR1655360 +TIM_CCR2_CCR2655360 +TIM_CCR3_CCR3655360 +TIM_CCR4_CCR4655360 +TIM_CNT_CNT655360 +TIM_CR1_ARPE655360 +TIM_CR1_CEN655360 +TIM_CR1_CKD655360 +TIM_CR1_CKD_0655360 +TIM_CR1_CKD_1655360 +TIM_CR1_CMS655360 +TIM_CR1_CMS_0655360 +TIM_CR1_CMS_1655360 +TIM_CR1_DIR655360 +TIM_CR1_OPM655360 +TIM_CR1_UDIS655360 +TIM_CR1_URS655360 +TIM_CR2_CCDS655360 +TIM_CR2_CCPC655360 +TIM_CR2_CCUS655360 +TIM_CR2_MMS655360 +TIM_CR2_MMS_0655360 +TIM_CR2_MMS_1655360 +TIM_CR2_MMS_2655360 +TIM_CR2_OIS1655360 +TIM_CR2_OIS1N655360 +TIM_CR2_OIS2655360 +TIM_CR2_OIS2N655360 +TIM_CR2_OIS3655360 +TIM_CR2_OIS3N655360 +TIM_CR2_OIS4655360 +TIM_CR2_TI1S655360 +TIM_DCR_DBA655360 +TIM_DCR_DBA_0655360 +TIM_DCR_DBA_1655360 +TIM_DCR_DBA_2655360 +TIM_DCR_DBA_3655360 +TIM_DCR_DBA_4655360 +TIM_DCR_DBL655360 +TIM_DCR_DBL_0655360 +TIM_DCR_DBL_1655360 +TIM_DCR_DBL_2655360 +TIM_DCR_DBL_3655360 +TIM_DCR_DBL_4655360 +TIM_DIER_BIE655360 +TIM_DIER_CC1DE655360 +TIM_DIER_CC1IE655360 +TIM_DIER_CC2DE655360 +TIM_DIER_CC2IE655360 +TIM_DIER_CC3DE655360 +TIM_DIER_CC3IE655360 +TIM_DIER_CC4DE655360 +TIM_DIER_CC4IE655360 +TIM_DIER_COMDE655360 +TIM_DIER_COMIE655360 +TIM_DIER_TDE655360 +TIM_DIER_TIE655360 +TIM_DIER_UDE655360 +TIM_DIER_UIE655360 +TIM_DMAR_DMAB655360 +TIM_EGR_BG655360 +TIM_EGR_CC1G655360 +TIM_EGR_CC2G655360 +TIM_EGR_CC3G655360 +TIM_EGR_CC4G655360 +TIM_EGR_COMG655360 +TIM_EGR_TG655360 +TIM_EGR_UG655360 +TIM_PSC_PSC655360 +TIM_RCR_REP655360 +TIM_SMCR_ECE655360 +TIM_SMCR_ETF655360 +TIM_SMCR_ETF_0655360 +TIM_SMCR_ETF_1655360 +TIM_SMCR_ETF_2655360 +TIM_SMCR_ETF_3655360 +TIM_SMCR_ETP655360 +TIM_SMCR_ETPS655360 +TIM_SMCR_ETPS_0655360 +TIM_SMCR_ETPS_1655360 +TIM_SMCR_MSM655360 +TIM_SMCR_OCCS655360 +TIM_SMCR_SMS655360 +TIM_SMCR_SMS_0655360 +TIM_SMCR_SMS_1655360 +TIM_SMCR_SMS_2655360 +TIM_SMCR_TS655360 +TIM_SMCR_TS_0655360 +TIM_SMCR_TS_1655360 +TIM_SMCR_TS_2655360 +TIM_SR_BIF655360 +TIM_SR_CC1IF655360 +TIM_SR_CC1OF655360 +TIM_SR_CC2IF655360 +TIM_SR_CC2OF655360 +TIM_SR_CC3IF655360 +TIM_SR_CC3OF655360 +TIM_SR_CC4IF655360 +TIM_SR_CC4OF655360 +TIM_SR_COMIF655360 +TIM_SR_TIF655360 +TIM_SR_UIF655360 +TRUE_INLINE655360 +TSC655360 +TSC_BASE655360 +TSC_CR_AM655360 +TSC_CR_CTPH655360 +TSC_CR_CTPH_0655360 +TSC_CR_CTPH_1655360 +TSC_CR_CTPH_2655360 +TSC_CR_CTPH_3655360 +TSC_CR_CTPL655360 +TSC_CR_CTPL_0655360 +TSC_CR_CTPL_1655360 +TSC_CR_CTPL_2655360 +TSC_CR_CTPL_3655360 +TSC_CR_IODEF655360 +TSC_CR_MCV655360 +TSC_CR_MCV_0655360 +TSC_CR_MCV_1655360 +TSC_CR_MCV_2655360 +TSC_CR_PGPSC655360 +TSC_CR_PGPSC_0655360 +TSC_CR_PGPSC_1655360 +TSC_CR_PGPSC_2655360 +TSC_CR_SSD655360 +TSC_CR_SSD_0655360 +TSC_CR_SSD_1655360 +TSC_CR_SSD_2655360 +TSC_CR_SSD_3655360 +TSC_CR_SSD_4655360 +TSC_CR_SSD_5655360 +TSC_CR_SSD_6655360 +TSC_CR_SSE655360 +TSC_CR_SSPSC655360 +TSC_CR_START655360 +TSC_CR_SYNCPOL655360 +TSC_CR_TSCE655360 +TSC_ICR_EOAIC655360 +TSC_ICR_MCEIC655360 +TSC_IER_EOAIE655360 +TSC_IER_MCEIE655360 +TSC_IOASCR_G1_IO1655360 +TSC_IOASCR_G1_IO2655360 +TSC_IOASCR_G1_IO3655360 +TSC_IOASCR_G1_IO4655360 +TSC_IOASCR_G2_IO1655360 +TSC_IOASCR_G2_IO2655360 +TSC_IOASCR_G2_IO3655360 +TSC_IOASCR_G2_IO4655360 +TSC_IOASCR_G3_IO1655360 +TSC_IOASCR_G3_IO2655360 +TSC_IOASCR_G3_IO3655360 +TSC_IOASCR_G3_IO4655360 +TSC_IOASCR_G4_IO1655360 +TSC_IOASCR_G4_IO2655360 +TSC_IOASCR_G4_IO3655360 +TSC_IOASCR_G4_IO4655360 +TSC_IOASCR_G5_IO1655360 +TSC_IOASCR_G5_IO2655360 +TSC_IOASCR_G5_IO3655360 +TSC_IOASCR_G5_IO4655360 +TSC_IOASCR_G6_IO1655360 +TSC_IOASCR_G6_IO2655360 +TSC_IOASCR_G6_IO3655360 +TSC_IOASCR_G6_IO4655360 +TSC_IOASCR_G7_IO1655360 +TSC_IOASCR_G7_IO2655360 +TSC_IOASCR_G7_IO3655360 +TSC_IOASCR_G7_IO4655360 +TSC_IOASCR_G8_IO1655360 +TSC_IOASCR_G8_IO2655360 +TSC_IOASCR_G8_IO3655360 +TSC_IOASCR_G8_IO4655360 +TSC_IOCCR_G1_IO1655360 +TSC_IOCCR_G1_IO2655360 +TSC_IOCCR_G1_IO3655360 +TSC_IOCCR_G1_IO4655360 +TSC_IOCCR_G2_IO1655360 +TSC_IOCCR_G2_IO2655360 +TSC_IOCCR_G2_IO3655360 +TSC_IOCCR_G2_IO4655360 +TSC_IOCCR_G3_IO1655360 +TSC_IOCCR_G3_IO2655360 +TSC_IOCCR_G3_IO3655360 +TSC_IOCCR_G3_IO4655360 +TSC_IOCCR_G4_IO1655360 +TSC_IOCCR_G4_IO2655360 +TSC_IOCCR_G4_IO3655360 +TSC_IOCCR_G4_IO4655360 +TSC_IOCCR_G5_IO1655360 +TSC_IOCCR_G5_IO2655360 +TSC_IOCCR_G5_IO3655360 +TSC_IOCCR_G5_IO4655360 +TSC_IOCCR_G6_IO1655360 +TSC_IOCCR_G6_IO2655360 +TSC_IOCCR_G6_IO3655360 +TSC_IOCCR_G6_IO4655360 +TSC_IOCCR_G7_IO1655360 +TSC_IOCCR_G7_IO2655360 +TSC_IOCCR_G7_IO3655360 +TSC_IOCCR_G7_IO4655360 +TSC_IOCCR_G8_IO1655360 +TSC_IOCCR_G8_IO2655360 +TSC_IOCCR_G8_IO3655360 +TSC_IOCCR_G8_IO4655360 +TSC_IOGCSR_G1E655360 +TSC_IOGCSR_G1S655360 +TSC_IOGCSR_G2E655360 +TSC_IOGCSR_G2S655360 +TSC_IOGCSR_G3E655360 +TSC_IOGCSR_G3S655360 +TSC_IOGCSR_G4E655360 +TSC_IOGCSR_G4S655360 +TSC_IOGCSR_G5E655360 +TSC_IOGCSR_G5S655360 +TSC_IOGCSR_G6E655360 +TSC_IOGCSR_G6S655360 +TSC_IOGCSR_G7E655360 +TSC_IOGCSR_G7S655360 +TSC_IOGCSR_G8E655360 +TSC_IOGCSR_G8S655360 +TSC_IOGXCR_CNT655360 +TSC_IOHCR_G1_IO1655360 +TSC_IOHCR_G1_IO2655360 +TSC_IOHCR_G1_IO3655360 +TSC_IOHCR_G1_IO4655360 +TSC_IOHCR_G2_IO1655360 +TSC_IOHCR_G2_IO2655360 +TSC_IOHCR_G2_IO3655360 +TSC_IOHCR_G2_IO4655360 +TSC_IOHCR_G3_IO1655360 +TSC_IOHCR_G3_IO2655360 +TSC_IOHCR_G3_IO3655360 +TSC_IOHCR_G3_IO4655360 +TSC_IOHCR_G4_IO1655360 +TSC_IOHCR_G4_IO2655360 +TSC_IOHCR_G4_IO3655360 +TSC_IOHCR_G4_IO4655360 +TSC_IOHCR_G5_IO1655360 +TSC_IOHCR_G5_IO2655360 +TSC_IOHCR_G5_IO3655360 +TSC_IOHCR_G5_IO4655360 +TSC_IOHCR_G6_IO1655360 +TSC_IOHCR_G6_IO2655360 +TSC_IOHCR_G6_IO3655360 +TSC_IOHCR_G6_IO4655360 +TSC_IOHCR_G7_IO1655360 +TSC_IOHCR_G7_IO2655360 +TSC_IOHCR_G7_IO3655360 +TSC_IOHCR_G7_IO4655360 +TSC_IOHCR_G8_IO1655360 +TSC_IOHCR_G8_IO2655360 +TSC_IOHCR_G8_IO3655360 +TSC_IOHCR_G8_IO4655360 +TSC_IOSCR_G1_IO1655360 +TSC_IOSCR_G1_IO2655360 +TSC_IOSCR_G1_IO3655360 +TSC_IOSCR_G1_IO4655360 +TSC_IOSCR_G2_IO1655360 +TSC_IOSCR_G2_IO2655360 +TSC_IOSCR_G2_IO3655360 +TSC_IOSCR_G2_IO4655360 +TSC_IOSCR_G3_IO1655360 +TSC_IOSCR_G3_IO2655360 +TSC_IOSCR_G3_IO3655360 +TSC_IOSCR_G3_IO4655360 +TSC_IOSCR_G4_IO1655360 +TSC_IOSCR_G4_IO2655360 +TSC_IOSCR_G4_IO3655360 +TSC_IOSCR_G4_IO4655360 +TSC_IOSCR_G5_IO1655360 +TSC_IOSCR_G5_IO2655360 +TSC_IOSCR_G5_IO3655360 +TSC_IOSCR_G5_IO4655360 +TSC_IOSCR_G6_IO1655360 +TSC_IOSCR_G6_IO2655360 +TSC_IOSCR_G6_IO3655360 +TSC_IOSCR_G6_IO4655360 +TSC_IOSCR_G7_IO1655360 +TSC_IOSCR_G7_IO2655360 +TSC_IOSCR_G7_IO3655360 +TSC_IOSCR_G7_IO4655360 +TSC_IOSCR_G8_IO1655360 +TSC_IOSCR_G8_IO2655360 +TSC_IOSCR_G8_IO3655360 +TSC_IOSCR_G8_IO4655360 +TSC_ISR_EOAF655360 +TSC_ISR_MCEF655360 +TXstatus40960anon_enum_0 +Tms163840volatile uint32_t +Tms327680volatile uint32_t +UARTBUFSZ655360 +UINT16_C131072(c)0 +UINT16_MAX655360 +UINT16_WIDTH655360 +UINT32_C131072(c)0 +UINT32_MAX655360 +UINT32_WIDTH655360 +UINT64_C131072(c)0 +UINT64_MAX655360 +UINT64_WIDTH655360 +UINT8_C131072(c)0 +UINT8_MAX655360 +UINT8_WIDTH655360 +UINTMAX_C131072(c)0 +UINTMAX_MAX655360 +UINTMAX_WIDTH655360 +UINTPTR_MAX655360 +UINTPTR_WIDTH655360 +UINT_FAST16_MAX655360 +UINT_FAST16_WIDTH655360 +UINT_FAST32_MAX655360 +UINT_FAST32_WIDTH655360 +UINT_FAST64_MAX655360 +UINT_FAST64_WIDTH655360 +UINT_FAST8_MAX655360 +UINT_FAST8_WIDTH655360 +UINT_LEAST16_MAX655360 +UINT_LEAST16_WIDTH655360 +UINT_LEAST32_MAX655360 +UINT_LEAST32_WIDTH655360 +UINT_LEAST64_MAX655360 +UINT_LEAST64_WIDTH655360 +UINT_LEAST8_MAX655360 +UINT_LEAST8_WIDTH655360 +USART1655360 +USART1_BASE655360 +USART2655360 +USART2_BASE655360 +USARTNUM655360 +USARTX655360 +USART_BRR_DIV_FRACTION655360 +USART_BRR_DIV_MANTISSA655360 +USART_CR1_CMIE655360 +USART_CR1_DEAT655360 +USART_CR1_DEAT_0655360 +USART_CR1_DEAT_1655360 +USART_CR1_DEAT_2655360 +USART_CR1_DEAT_3655360 +USART_CR1_DEAT_4655360 +USART_CR1_DEDT655360 +USART_CR1_DEDT_0655360 +USART_CR1_DEDT_1655360 +USART_CR1_DEDT_2655360 +USART_CR1_DEDT_3655360 +USART_CR1_DEDT_4655360 +USART_CR1_EOBIE655360 +USART_CR1_IDLEIE655360 +USART_CR1_M655360 +USART_CR1_M0655360 +USART_CR1_M1655360 +USART_CR1_MME655360 +USART_CR1_OVER8655360 +USART_CR1_PCE655360 +USART_CR1_PEIE655360 +USART_CR1_PS655360 +USART_CR1_RE655360 +USART_CR1_RTOIE655360 +USART_CR1_RXNEIE655360 +USART_CR1_TCIE655360 +USART_CR1_TE655360 +USART_CR1_TXEIE655360 +USART_CR1_UE655360 +USART_CR1_UESM655360 +USART_CR1_WAKE655360 +USART_CR2_ABREN655360 +USART_CR2_ABRMODE655360 +USART_CR2_ABRMODE_0655360 +USART_CR2_ABRMODE_1655360 +USART_CR2_ADD655360 +USART_CR2_ADDM7655360 +USART_CR2_ADD_SHIFT655360 +USART_CR2_ADD_VAL131072(x)0 +USART_CR2_CLKEN655360 +USART_CR2_CPHA655360 +USART_CR2_CPOL655360 +USART_CR2_DATAINV655360 +USART_CR2_LBCL655360 +USART_CR2_LBDIE655360 +USART_CR2_LBDL655360 +USART_CR2_LINEN655360 +USART_CR2_MSBFIRST655360 +USART_CR2_RTOEN655360 +USART_CR2_RXINV655360 +USART_CR2_STOP655360 +USART_CR2_STOP_0655360 +USART_CR2_STOP_1655360 +USART_CR2_SWAP655360 +USART_CR2_TXINV655360 +USART_CR3_CTSE655360 +USART_CR3_CTSIE655360 +USART_CR3_DDRE655360 +USART_CR3_DEM655360 +USART_CR3_DEP655360 +USART_CR3_DMAR655360 +USART_CR3_DMAT655360 +USART_CR3_EIE655360 +USART_CR3_HDSEL655360 +USART_CR3_IREN655360 +USART_CR3_IRLP655360 +USART_CR3_NACK655360 +USART_CR3_ONEBIT655360 +USART_CR3_OVRDIS655360 +USART_CR3_RTSE655360 +USART_CR3_SCARCNT655360 +USART_CR3_SCARCNT_0655360 +USART_CR3_SCARCNT_1655360 +USART_CR3_SCARCNT_2655360 +USART_CR3_SCEN655360 +USART_CR3_WUFIE655360 +USART_CR3_WUS655360 +USART_CR3_WUS_0655360 +USART_CR3_WUS_1655360 +USART_GTPR_GT655360 +USART_GTPR_PSC655360 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+can_send_broadcast16()0void +can_send_broadcast1024()0void +can_send_dummy16()0void +can_send_dummy1024()0void +can_status163840CAN_status +cec_can_isr16()0void +data64anon_struct_10uint8_t +datalen163840int +dlen163840int +dma1_channel2_3_isr16()0void +first_free_idx163840uint8_t +first_nonfree_idx163840int8_t +getCANID16()0uint16_t +getCANID1024()0uint16_t +gpio_setup16(void)0void +gpio_setup1024(void)0void +iwdg_setup16()0void +last_err_code163840uint32_t +length64anon_struct_10uint8_t +linerdy163840volatile int +linerdy327680volatile int +linux655360 +main16(void)0int +messages163840CAN_message +newline16()0void +newline1024()0void +nop131072()0 +pin_clear131072(gpioport,gpios)0 +pin_read131072(gpioport,gpios)0 +pin_set131072(gpioport,gpios)0 +pin_toggle131072(gpioport,gpios)0 +pin_write131072(gpioport,gpios)0 +printu16(uint32_t val)0void +printu1024(uint32_t val)0void +printuhex16(uint32_t val)0void +printuhex1024(uint32_t val)0void +rbuf163840char +rbufno163840int +readCANID16()0void +readCANID1024()0void +recvdata163840char * +strdupa131072(s)0 +strndupa131072(s,n)0 +sys_tick_handler16(void)0void +sysreset16(void)0inline void +tbuf163840char +txrdy163840int +txrdy327680int +unix655360 +usart1_isr16()0void +usart_getline16(char **line)0int +usart_getline1024(char **line)0int +usart_putchar16(const char ch)0void +usart_putchar1024(const char ch)0void +usart_send16(const char *str, int len)0TXstatus +usart_send1024(const char *str, int len)0TXstatus +usart_send_blocking16(const char *str, int len)0TXstatus +usart_send_blocking1024(const char *str, int len)0TXstatus +usart_setup16()0void +usart_setup1024()0void +usartovr131072()0 +usartrx131072()0 diff --git a/F0-nolib/usbcdc/hardware.c b/F0-nolib/usbcdc/hardware.c new file mode 100644 index 0000000..60cb1b5 --- /dev/null +++ b/F0-nolib/usbcdc/hardware.c @@ -0,0 +1,43 @@ +/* + * geany_encoding=koi8-r + * hardware.c - hardware-dependent macros & functions + * + * Copyright 2018 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ + +#include "hardware.h" +#include "usart.h" + +void gpio_setup(void){ + // here we turn on clocking for all periph. + RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN | RCC_AHBENR_DMAEN; + // Set LEDS (PC13/14) as output + GPIOC->MODER = (GPIOC->MODER & ~(GPIO_MODER_MODER13 | GPIO_MODER_MODER14) + ) | + GPIO_MODER_MODER13_O | GPIO_MODER_MODER14_O; + // PB14(0), PB15(1), PA8(2) - CAN address, pullup inputs + GPIOA->PUPDR = (GPIOA->PUPDR & ~(GPIO_PUPDR_PUPDR8) + ) | + GPIO_PUPDR_PUPDR8_0; + GPIOB->PUPDR = (GPIOB->PUPDR & ~(GPIO_PUPDR_PUPDR14 | GPIO_PUPDR_PUPDR15) + ) | + GPIO_PUPDR_PUPDR14_0 | GPIO_PUPDR_PUPDR15_0; + pin_set(LED0_port, LED0_pin); // clear LEDs + pin_set(LED1_port, LED1_pin); +} diff --git a/F0-nolib/usbcdc/hardware.h b/F0-nolib/usbcdc/hardware.h new file mode 100644 index 0000000..56f152e --- /dev/null +++ b/F0-nolib/usbcdc/hardware.h @@ -0,0 +1,54 @@ +/* + * geany_encoding=koi8-r + * hardware.h + * + * Copyright 2018 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ +#pragma once +#ifndef __HARDWARE_H__ +#define __HARDWARE_H__ + +#include "stm32f0.h" + +#define CONCAT(a,b) a ## b +#define STR_HELPER(s) #s +#define STR(s) STR_HELPER(s) + +#define FORMUSART(X) CONCAT(USART, X) +#define USARTX FORMUSART(USARTNUM) + +// LEDS: 0 - PC13, 1 - PC14 +// LED0 +#define LED0_port GPIOC +#define LED0_pin (1<<13) +// LED1 +#define LED1_port GPIOC +#define LED1_pin (1<<14) + +#define LED_blink(x) pin_toggle(x ## _port, x ## _pin) +#define LED_on(x) pin_clear(x ## _port, x ## _pin) +#define LED_off(x) pin_set(x ## _port, x ## _pin) + + +// CAN address - PB14(0), PB15(1), PA8(2) +#define READ_CAN_INV_ADDR() (((GPIOA->IDR & (1<<8))>>6)|((GPIOB->IDR & (3<<14))>>14)) + +void gpio_setup(void); + +#endif // __HARDWARE_H__ diff --git a/F0-nolib/usbcdc/ld/stm32f042k.ld b/F0-nolib/usbcdc/ld/stm32f042k.ld new file mode 100644 index 0000000..e747253 --- /dev/null +++ b/F0-nolib/usbcdc/ld/stm32f042k.ld @@ -0,0 +1,12 @@ +/* Linker script for STM32F042x6, 32K flash, 6K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K +} + +/* Include the common ld script. */ +INCLUDE stm32f0.ld + diff --git a/F0-nolib/usbcdc/main.c b/F0-nolib/usbcdc/main.c new file mode 100644 index 0000000..32a3059 --- /dev/null +++ b/F0-nolib/usbcdc/main.c @@ -0,0 +1,157 @@ +/* + * main.c + * + * Copyright 2017 Edward V. Emelianoff + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include "hardware.h" +#include "usart.h" +#include "can.h" +#include "usb.h" +#include "usb_lib.h" + +volatile uint32_t Tms = 0; + +/* Called when systick fires */ +void sys_tick_handler(void){ + ++Tms; +} + +void iwdg_setup(){ + /* Enable the peripheral clock RTC */ + /* (1) Enable the LSI (40kHz) */ + /* (2) Wait while it is not ready */ + RCC->CSR |= RCC_CSR_LSION; /* (1) */ + while((RCC->CSR & RCC_CSR_LSIRDY) != RCC_CSR_LSIRDY); /* (2) */ + /* Configure IWDG */ + /* (1) Activate IWDG (not needed if done in option bytes) */ + /* (2) Enable write access to IWDG registers */ + /* (3) Set prescaler by 64 (1.6ms for each tick) */ + /* (4) Set reload value to have a rollover each 2s */ + /* (5) Check if flags are reset */ + /* (6) Refresh counter */ + IWDG->KR = IWDG_START; /* (1) */ + IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */ + IWDG->PR = IWDG_PR_PR_1; /* (3) */ + IWDG->RLR = 1250; /* (4) */ + while(IWDG->SR); /* (5) */ + IWDG->KR = IWDG_REFRESH; /* (6) */ +} + +int main(void){ + uint32_t lastT = 0; + uint8_t ctr, len; + CAN_message *can_mesg; + int L; + char *txt; + sysreset(); + SysTick_Config(6000, 1); + gpio_setup(); + usart_setup(); + //iwdg_setup(); + readCANID(); + CAN_setup(); + + SEND("Greetings! My address is "); + printuhex(getCANID()); + newline(); + + if(RCC->CSR & RCC_CSR_IWDGRSTF){ // watchdog reset occured + SEND("WDGRESET=1\n"); + } + if(RCC->CSR & RCC_CSR_SFTRSTF){ // software reset occured + SEND("SOFTRESET=1\n"); + } + RCC->CSR |= RCC_CSR_RMVF; // remove reset flags + + USB_setup(); + + while (1){ + IWDG->KR = IWDG_REFRESH; // refresh watchdog + if(lastT > Tms || Tms - lastT > 499){ + LED_blink(LED0); + lastT = Tms; + } + can_proc(); + usb_proc(); + if(CAN_get_status() == CAN_FIFO_OVERRUN){ + SEND("CAN bus fifo overrun occured!\n"); + } + can_mesg = CAN_messagebuf_pop(); + if(can_mesg){ // new data in buff + len = can_mesg->length; + SEND("got message, len: "); usart_putchar('0' + len); + SEND(", data: "); + for(ctr = 0; ctr < len; ++ctr){ + printuhex(can_mesg->data[ctr]); + usart_putchar(' '); + } + newline(); + } + if(usartrx()){ // usart1 received data, store in in buffer + L = usart_getline(&txt); + char _1st = txt[0]; + if(L == 2 && txt[1] == '\n'){ + L = 0; + switch(_1st){ + case 'B': + can_send_broadcast(); + break; + case 'C': + can_send_dummy(); + break; + case 'G': + SEND("Can address: "); + printuhex(getCANID()); + newline(); + break; + case 'R': + SEND("Soft reset\n"); + NVIC_SystemReset(); + break; + case 'S': + CAN_reinit(); + SEND("Can address: "); + printuhex(getCANID()); + newline(); + break; + case 'W': + SEND("Wait for reboot\n"); + while(1){nop();}; + break; + default: // help + SEND( + "'B' - send broadcast dummy byte\n" + "'C' - send dummy byte over CAN\n" + "'G' - get CAN address\n" + "'R' - software reset\n" + "'S' - reinit CAN (with new address)\n" + "'W' - test watchdog\n" + ); + break; + } + } + } + if(L){ // text waits for sending + while(LINE_BUSY == usart_send(txt, L)); + L = 0; + } + } + return 0; +} + diff --git a/F0-nolib/usbcdc/usart.c b/F0-nolib/usbcdc/usart.c new file mode 100644 index 0000000..b00dbf7 --- /dev/null +++ b/F0-nolib/usbcdc/usart.c @@ -0,0 +1,252 @@ +/*us + * usart.c + * + * Copyright 2017 Edward V. Emelianoff + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#include "stm32f0.h" +#include "hardware.h" +#include "usart.h" +#include + +extern volatile uint32_t Tms; +static int datalen[2] = {0,0}; // received data line length (including '\n') + +volatile int linerdy = 0, // received data ready + dlen = 0, // length of data (including '\n') in current buffer + bufovr = 0, // input buffer overfull + txrdy = 1 // transmission done +; + + +int rbufno = 0; // current rbuf number +static char rbuf[UARTBUFSZ][2], tbuf[UARTBUFSZ]; // receive & transmit buffers +static char *recvdata = NULL; + +/** + * return length of received data (without trailing zero + */ +int usart_getline(char **line){ + if(bufovr){ + bufovr = 0; + linerdy = 0; + return 0; + } + *line = recvdata; + linerdy = 0; + return dlen; +} + +TXstatus usart_send(const char *str, int len){ + if(!txrdy) return LINE_BUSY; + if(len > UARTBUFSZ) return STR_TOO_LONG; + txrdy = 0; + memcpy(tbuf, str, len); +#if USARTNUM == 2 + DMA1_Channel4->CCR &= ~DMA_CCR_EN; + DMA1_Channel4->CNDTR = len; + DMA1_Channel4->CCR |= DMA_CCR_EN; // start transmission +#elif USARTNUM == 1 + DMA1_Channel2->CCR &= ~DMA_CCR_EN; + DMA1_Channel2->CNDTR = len; + DMA1_Channel2->CCR |= DMA_CCR_EN; +#else +#error "Not implemented" +#endif + return ALL_OK; +} + +TXstatus usart_send_blocking(const char *str, int len){ + while(!txrdy); + int i; + bufovr = 0; + for(i = 0; i < len; ++i){ + USARTX->TDR = *str++; + while(!(USARTX->ISR & USART_ISR_TXE)); + } + return ALL_OK; +} + +void usart_putchar(const char ch){ + while(!txrdy); + USARTX->TDR = ch; + while(!(USARTX->ISR & USART_ISR_TXE)); +} + +void newline(){ + while(!txrdy); + USARTX->TDR = '\n'; + while(!(USARTX->ISR & USART_ISR_TXE)); +} + + +void usart_setup(){ +// Nucleo's USART2 connected to VCP proxy of st-link +#if USARTNUM == 2 + // setup pins: PA2 (Tx - AF1), PA15 (Rx - AF1) + // AF mode (AF1) + GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER2|GPIO_MODER_MODER15))\ + | (GPIO_MODER_MODER2_AF | GPIO_MODER_MODER15_AF); + GPIOA->AFR[0] = (GPIOA->AFR[0] &~GPIO_AFRH_AFRH2) | 1 << (2 * 4); // PA2 + GPIOA->AFR[1] = (GPIOA->AFR[1] &~GPIO_AFRH_AFRH7) | 1 << (7 * 4); // PA15 + // DMA: Tx - Ch4 + DMA1_Channel4->CPAR = (uint32_t) &USART2->TDR; // periph + DMA1_Channel4->CMAR = (uint32_t) tbuf; // mem + DMA1_Channel4->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq + // Tx CNDTR set @ each transmission due to data size + NVIC_SetPriority(DMA1_Channel4_5_IRQn, 3); + NVIC_EnableIRQ(DMA1_Channel4_5_IRQn); + NVIC_SetPriority(USART2_IRQn, 0); + // setup usart2 + RCC->APB1ENR |= RCC_APB1ENR_USART2EN; // clock + // oversampling by16, 115200bps (fck=48mHz) + //USART2_BRR = 0x1a1; // 48000000 / 115200 + USART2->BRR = 480000 / 1152; + USART2->CR3 = USART_CR3_DMAT; // enable DMA Tx + USART2->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; // 1start,8data,nstop; enable Rx,Tx,USART + while(!(USART2->ISR & USART_ISR_TC)); // polling idle frame Transmission + USART2->ICR |= USART_ICR_TCCF; // clear TC flag + USART2->CR1 |= USART_CR1_RXNEIE; + NVIC_EnableIRQ(USART2_IRQn); +// USART1 of main board +#elif USARTNUM == 1 + // PA9 - Tx, PA10 - Rx (AF1) + GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODER9 | GPIO_MODER_MODER10))\ + | (GPIO_MODER_MODER9_AF | GPIO_MODER_MODER10_AF); + GPIOA->AFR[1] = (GPIOA->AFR[1] & ~(GPIO_AFRH_AFRH1 | GPIO_AFRH_AFRH2)) | + 1 << (1 * 4) | 1 << (2 * 4); // PA9, PA10 + // USART1 Tx DMA - Channel2 (default value in SYSCFG_CFGR1) + DMA1_Channel2->CPAR = (uint32_t) &USART1->TDR; // periph + DMA1_Channel2->CMAR = (uint32_t) tbuf; // mem + DMA1_Channel2->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq + // Tx CNDTR set @ each transmission due to data size + NVIC_SetPriority(DMA1_Channel2_3_IRQn, 3); + NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); + NVIC_SetPriority(USART1_IRQn, 0); + // setup usart1 + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; + USART1->BRR = 480000 / 1152; + USART1->CR3 = USART_CR3_DMAT; // enable DMA Tx + USART1->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; // 1start,8data,nstop; enable Rx,Tx,USART + while(!(USART1->ISR & USART_ISR_TC)); // polling idle frame Transmission + USART1->ICR |= USART_ICR_TCCF; // clear TC flag + USART1->CR1 |= USART_CR1_RXNEIE; + NVIC_EnableIRQ(USART1_IRQn); +#else +#error "Not implemented" +#endif +} + +#if USARTNUM == 2 +void usart2_isr(){ +// USART1 +#elif USARTNUM == 1 +void usart1_isr(){ +#else +#error "Not implemented" +#endif + #ifdef CHECK_TMOUT + static uint32_t tmout = 0; + #endif + if(USARTX->ISR & USART_ISR_RXNE){ // RX not emty - receive next char + #ifdef CHECK_TMOUT + if(tmout && Tms >= tmout){ // set overflow flag + bufovr = 1; + datalen[rbufno] = 0; + } + tmout = Tms + TIMEOUT_MS; + if(!tmout) tmout = 1; // prevent 0 + #endif + // read RDR clears flag + uint8_t rb = USARTX->RDR; + if(datalen[rbufno] < UARTBUFSZ){ // put next char into buf + rbuf[rbufno][datalen[rbufno]++] = rb; + if(rb == '\n'){ // got newline - line ready + linerdy = 1; + dlen = datalen[rbufno]; + recvdata = rbuf[rbufno]; + // prepare other buffer + rbufno = !rbufno; + datalen[rbufno] = 0; + #ifdef CHECK_TMOUT + // clear timeout at line end + tmout = 0; + #endif + } + }else{ // buffer overrun + bufovr = 1; + datalen[rbufno] = 0; + #ifdef CHECK_TMOUT + tmout = 0; + #endif + } + } +} + +// print 32bit unsigned int +void printu(uint32_t val){ + char bufa[11], bufb[10]; + int l = 0, bpos = 0; + if(!val){ + bufa[0] = '0'; + l = 1; + }else{ + while(val){ + bufb[l++] = val % 10 + '0'; + val /= 10; + } + int i; + bpos += l; + for(i = 0; i < l; ++i){ + bufa[--bpos] = bufb[i]; + } + } + while(LINE_BUSY == usart_send_blocking(bufa, l+bpos)); +} + +// print 32bit unsigned int as hex +void printuhex(uint32_t val){ + SEND("0x"); + uint8_t *ptr = (uint8_t*)&val + 3; + int i, j; + for(i = 0; i < 4; ++i, --ptr){ + for(j = 1; j > -1; --j){ + uint8_t half = (*ptr >> (4*j)) & 0x0f; + if(half < 10) usart_putchar(half + '0'); + else usart_putchar(half - 10 + 'a'); + } + } +} + +#if USARTNUM == 2 +void dma1_channel4_5_isr(){ + if(DMA1->ISR & DMA_ISR_TCIF4){ // Tx + DMA1->IFCR |= DMA_IFCR_CTCIF4; // clear TC flag + txrdy = 1; + } +} +// USART1 +#elif USARTNUM == 1 +void dma1_channel2_3_isr(){ + if(DMA1->ISR & DMA_ISR_TCIF2){ // Tx + DMA1->IFCR |= DMA_IFCR_CTCIF2; // clear TC flag + txrdy = 1; + } +} +#else +#error "Not implemented" +#endif diff --git a/F0-nolib/usbcdc/usart.h b/F0-nolib/usbcdc/usart.h new file mode 100644 index 0000000..46d0553 --- /dev/null +++ b/F0-nolib/usbcdc/usart.h @@ -0,0 +1,63 @@ +/* + * usart.h + * + * Copyright 2017 Edward V. Emelianoff + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#pragma once +#ifndef __USART_H__ +#define __USART_H__ + +#include "hardware.h" + +// input and output buffers size +#define UARTBUFSZ (64) +// timeout between data bytes +#ifndef TIMEOUT_MS +#define TIMEOUT_MS (1500) +#endif + +// macro for static strings +#define SEND(str) do{}while(LINE_BUSY == usart_send_blocking(str, sizeof(str)-1)) + +#ifdef EBUG +#define MSG(str) do{SEND(__FILE__ " (L" STR(__LINE__) "): " str);}while(0) +#else +#define MSG(str) +#endif + +typedef enum{ + ALL_OK, + LINE_BUSY, + STR_TOO_LONG +} TXstatus; + +#define usartrx() (linerdy) +#define usartovr() (bufovr) + +extern volatile int linerdy, bufovr, txrdy; + +void usart_setup(); +int usart_getline(char **line); +TXstatus usart_send(const char *str, int len); +TXstatus usart_send_blocking(const char *str, int len); +void newline(); +void usart_putchar(const char ch); +void printu(uint32_t val); +void printuhex(uint32_t val); + +#endif // __USART_H__ diff --git a/F0-nolib/usbcdc/usb.c b/F0-nolib/usbcdc/usb.c new file mode 100644 index 0000000..8ecce6e --- /dev/null +++ b/F0-nolib/usbcdc/usb.c @@ -0,0 +1,144 @@ +/* + * geany_encoding=koi8-r + * usb.c + * + * Copyright 2018 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ + +#include "usb.h" +#include "usb_lib.h" +#ifdef EBUG +#include "usart.h" +#endif + + +static uint8_t buffer[64]; +static uint8_t len, rcvflag = 0; + +static uint16_t EP1_Handler(ep_t ep){ + MSG("EP1 "); + if (ep.rx_flag){ //Пришли новые данные + MSG("read"); + EP_Read(1, buffer); + EP_WriteIRQ(1, buffer, ep.rx_cnt); + ep.status = SET_VALID_TX(ep.status); //TX + ep.status = KEEP_STAT_RX(ep.status); //RX оставляем в NAK + } else + if (ep.tx_flag){ //Данные успешно переданы + MSG("write"); + ep.status = SET_VALID_RX(ep.status); //RX в VALID + ep.status = SET_STALL_TX(ep.status); //TX в STALL + } + MSG("; end\n"); + return ep.status; +} + +// write handler +static uint16_t EP2_Handler(ep_t ep){ + MSG("EP2 "); + if (ep.rx_flag){ //Пришли новые данные + MSG("read"); + #ifdef EBUG + printu(ep.rx_cnt); + #endif + if(ep.rx_cnt > 2){ + len = ep.rx_cnt; + rcvflag = 1; + EP_Read(2, buffer); + } + //EP_WriteIRQ(3, buffer, ep.rx_cnt); + //Так как мы ожидаем новый запрос от хоста, устанавливаем + ep.status = SET_VALID_RX(ep.status); + //ep.status = SET_STALL_TX(ep.status); + //ep.status = SET_VALID_TX(ep.status); //TX + //ep.status = KEEP_STAT_RX(ep.status); //RX оставляем в NAK + } else + if (ep.tx_flag){ //Данные успешно переданы + MSG("write"); + ep.status = SET_VALID_RX(ep.status); //RX в VALID + ep.status = SET_STALL_TX(ep.status); //TX в STALL + } + MSG("; end\n"); + return ep.status; +} + +// read handler +static uint16_t EP3_Handler(ep_t ep){ + MSG("EP3 "); + if (ep.rx_flag){ //Пришли новые данные + MSG("read"); + EP_Read(3, buffer); + ep.status = SET_VALID_TX(ep.status); //TX + ep.status = KEEP_STAT_RX(ep.status); //RX оставляем в NAK + } else + if (ep.tx_flag){ //Данные успешно переданы + MSG("write"); + ep.status = SET_VALID_RX(ep.status); //RX в VALID + ep.status = SET_STALL_TX(ep.status); //TX в STALL + } + MSG("; end\n"); + return ep.status; +} + +void USB_setup(){ + RCC->APB1ENR |= RCC_APB1ENR_CRSEN | RCC_APB1ENR_USBEN; // enable CRS (hsi48 sync) & USB + RCC->CFGR3 &= ~RCC_CFGR3_USBSW; // reset USB + RCC->CR2 |= RCC_CR2_HSI48ON; // turn ON HSI48 + while(!(RCC->CR2 & RCC_CR2_HSI48RDY)); + FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; + CRS->CFGR &= ~CRS_CFGR_SYNCSRC; + CRS->CFGR |= CRS_CFGR_SYNCSRC_1; // USB SOF selected as sync source + CRS->CR |= CRS_CR_AUTOTRIMEN; // enable auto trim + CRS->CR |= CRS_CR_CEN; // enable freq counter & block CRS->CFGR as read-only + RCC->CFGR |= RCC_CFGR_SW; + //Разрешаем прерывания по RESET и CTRM + USB -> CNTR = USB_CNTR_RESETM | USB_CNTR_CTRM; + //Сбрасываем флаги + USB -> ISTR = 0; + //Включаем подтяжку на D+ + USB -> BCDR |= USB_BCDR_DPPU; + NVIC_EnableIRQ(USB_IRQn); +} + +void usb_proc(){ + static int8_t usbON = 0; + if(USB_GetState() == USB_CONFIGURE_STATE){ // USB configured - activate other endpoints + if(!usbON){ // endpoints not activated + MSG("Configured; activate other endpoints\n"); + // make new BULK endpoint + // Buffer have 1024 bytes, but last 256 we use for CAN bus + // first free is 64; 768 - CAN data + // free: 64 128 192 256 320 384 448 512 576 640 704 + // (first 192 free bytes are for EP0) + EP_Init(1, EP_TYPE_INTERRUPT, 256, 320, EP1_Handler); + EP_Init(2, EP_TYPE_BULK, 384, 448, EP2_Handler); + EP_Init(3, EP_TYPE_BULK, 512, 576, EP3_Handler); + usbON = 1; + }else{ + if(rcvflag){ + EP_Write(3, buffer, len); + MSG("read: "); + if(len > 2) while(LINE_BUSY == usart_send((char*)&buffer[2], len-2)); + rcvflag = 0; + } + } + }else{ + usbON = 0; + } +} diff --git a/F0-nolib/usbcdc/usb.h b/F0-nolib/usbcdc/usb.h new file mode 100644 index 0000000..e52aeec --- /dev/null +++ b/F0-nolib/usbcdc/usb.h @@ -0,0 +1,32 @@ +/* + * geany_encoding=koi8-r + * usb.h + * + * Copyright 2018 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + * + */ +#pragma once +#ifndef __USB_H__ +#define __USB_H__ + +#include "hardware.h" + +void USB_setup(); +void usb_proc(); + +#endif // __USB_H__ diff --git a/F0-nolib/usbcdc/usb_defs.h b/F0-nolib/usbcdc/usb_defs.h new file mode 100644 index 0000000..975d79d --- /dev/null +++ b/F0-nolib/usbcdc/usb_defs.h @@ -0,0 +1,69 @@ +#pragma once +#ifndef __USB_DEFS_H__ +#define __USB_DEFS_H__ + +#include + +#define USB_BTABLE_BASE 0x40006000 +#undef USB_BTABLE +#define USB_BTABLE ((USB_BtableDef *)(USB_BTABLE_BASE)) +#define USB_ISTR_EPID 0x0000000F +#define USB_FNR_LSOF_0 0x00000800 +#define USB_FNR_lSOF_1 0x00001000 +#define USB_LPMCSR_BESL_0 0x00000010 +#define USB_LPMCSR_BESL_1 0x00000020 +#define USB_LPMCSR_BESL_2 0x00000040 +#define USB_LPMCSR_BESL_3 0x00000080 +#define USB_EPnR_CTR_RX 0x00008000 +#define USB_EPnR_DTOG_RX 0x00004000 +#define USB_EPnR_STAT_RX 0x00003000 +#define USB_EPnR_STAT_RX_0 0x00001000 +#define USB_EPnR_STAT_RX_1 0x00002000 +#define USB_EPnR_SETUP 0x00000800 +#define USB_EPnR_EP_TYPE 0x00000600 +#define USB_EPnR_EP_TYPE_0 0x00000200 +#define USB_EPnR_EP_TYPE_1 0x00000400 +#define USB_EPnR_EP_KIND 0x00000100 +#define USB_EPnR_CTR_TX 0x00000080 +#define USB_EPnR_DTOG_TX 0x00000040 +#define USB_EPnR_STAT_TX 0x00000030 +#define USB_EPnR_STAT_TX_0 0x00000010 +#define USB_EPnR_STAT_TX_1 0x00000020 +#define USB_EPnR_EA 0x0000000F +#define USB_COUNTn_RX_BLSIZE 0x00008000 +#define USB_COUNTn_NUM_BLOCK 0x00007C00 +#define USB_COUNTn_RX 0x0000003F + +#define USB_TypeDef USB_TypeDef_custom + +typedef struct{ + __IO uint32_t EPnR[8]; + __IO uint32_t RESERVED1; + __IO uint32_t RESERVED2; + __IO uint32_t RESERVED3; + __IO uint32_t RESERVED4; + __IO uint32_t RESERVED5; + __IO uint32_t RESERVED6; + __IO uint32_t RESERVED7; + __IO uint32_t RESERVED8; + __IO uint32_t CNTR; + __IO uint32_t ISTR; + __IO uint32_t FNR; + __IO uint32_t DADDR; + __IO uint32_t BTABLE; + __IO uint32_t LPMCSR; + __IO uint32_t BCDR; +} USB_TypeDef; + +typedef struct{ + __IO uint16_t USB_ADDR_TX; + __IO uint16_t USB_COUNT_TX; + __IO uint16_t USB_ADDR_RX; + __IO uint16_t USB_COUNT_RX; +} USB_EPDATA_TypeDef; + +typedef struct{ + __IO USB_EPDATA_TypeDef EP[8]; +} USB_BtableDef; + +#endif // __USB_DEFS_H__ diff --git a/F0-nolib/usbcdc/usb_lib.c b/F0-nolib/usbcdc/usb_lib.c new file mode 100644 index 0000000..8f3e3c0 --- /dev/null +++ b/F0-nolib/usbcdc/usb_lib.c @@ -0,0 +1,499 @@ +#include +#include +#include "usb_lib.h" +#ifdef EBUG +#include // memcpy +#include "usart.h" +#endif + +#define DEVICE_DESCRIPTOR_SIZE_BYTE (18) +#define DEVICE_QALIFIER_SIZE_BYTE (10) +#define STRING_LANG_DESCRIPTOR_SIZE_BYTE (4) + +const uint8_t USB_DeviceDescriptor[] = { + DEVICE_DESCRIPTOR_SIZE_BYTE, // bLength + 0x01, // bDescriptorType - USB_DEVICE_DESC_TYPE + 0x00, // bcdUSB_L + 0x02, // bcdUSB_H + 0x00, // bDeviceClass - USB_COMM + 0x00, // bDeviceSubClass + 0x00, // bDeviceProtocol + 0x40, // bMaxPacketSize + 0x7b, // idVendor_L PL2303: VID=0x067b, PID=0x2303 + 0x06, // idVendor_H + 0x03, // idProduct_L + 0x23, // idProduct_H + 0x00, // bcdDevice_Ver_L + 0x01, // bcdDevice_Ver_H + 0x01, // iManufacturer + 0x02, // iProduct + 0x00, // iSerialNumber + 0x01 // bNumConfigurations +}; + +const uint8_t USB_DeviceQualifierDescriptor[] = { + DEVICE_QALIFIER_SIZE_BYTE, //bLength + 0x06, // bDescriptorType + 0x00, // bcdUSB_L + 0x02, // bcdUSB_H + 0x00, // bDeviceClass + 0x00, // bDeviceSubClass + 0x00, // bDeviceProtocol + 0x40, // bMaxPacketSize0 + 0x01, // bNumConfigurations + 0x00 // Reserved +}; + +#if 0 +const uint8_t USB_ConfigDescriptor[] = { + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + 0x02, /* bDescriptorType: Configuration */ + 39, /* wTotalLength:no of returned bytes */ + 0x00, + 0x02, /* bNumInterfaces: 2 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0x80, /* bmAttributes - Bus powered */ + 0x32, /* MaxPower 100 mA */ + + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: Interface */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints: One endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Union Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x06, /* bDescriptorSubtype: Union func desc */ + 0x00, /* bMasterInterface: Communication class interface */ + 0x01, /* bSlaveInterface0: Data Class Interface */ + + /*Endpoint 2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + 0x05, /* bDescriptorType: Endpoint */ + 0x81, /* bEndpointAddress IN1 */ + 0x03, /* bmAttributes: Interrupt */ + 0x08, /* wMaxPacketSize LO: */ + 0x00, /* wMaxPacketSize HI: */ + 0x10, /* bInterval: */ + /*---------------------------------------------------------------------------*/ + + /*Data class interface descriptor*/ + 0x09, /* bLength: Endpoint Descriptor size */ + 0x04, /* bDescriptorType: */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints: Two endpoints used */ + 0x0A, /* bInterfaceClass: CDC */ + 0x02, /* bInterfaceSubClass: */ + 0x00, /* bInterfaceProtocol: */ + 0x00, /* iInterface: */ + + /*Endpoint IN2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + 0x05, /* bDescriptorType: Endpoint */ + 0x82, /* bEndpointAddress IN2 */ + 0x02, /* bmAttributes: Bulk */ + 64, /* wMaxPacketSize: */ + 0x00, + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint OUT3 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + 0x05, /* bDescriptorType: Endpoint */ + 0x03, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 64, /* wMaxPacketSize: */ + 0, + 0x00 /* bInterval: ignore for Bulk transfer */ +}; +#endif + +const uint8_t USB_ConfigDescriptor[] = { + /*Configuration Descriptor*/ + 0x09, /* bLength: Configuration Descriptor size */ + 0x02, /* bDescriptorType: Configuration */ + 53, /* wTotalLength:no of returned bytes */ + 0x00, + 0x01, /* bNumInterfaces: 1 interface */ + 0x01, /* bConfigurationValue: Configuration value */ + 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ + 0x80, /* bmAttributes - Bus powered */ + 0x32, /* MaxPower 100 mA */ + + /*---------------------------------------------------------------------------*/ + + /*Interface Descriptor */ + 0x09, /* bLength: Interface Descriptor size */ + 0x04, /* bDescriptorType: Interface */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x03, /* bNumEndpoints: 3 endpoints used */ + 0x02, /* bInterfaceClass: Communication Interface Class */ + 0x02, /* bInterfaceSubClass: Abstract Control Model */ + 0x01, /* bInterfaceProtocol: Common AT commands */ + 0x00, /* iInterface: */ + + /*Header Functional Descriptor*/ + 0x05, /* bLength: Endpoint Descriptor size */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x00, /* bDescriptorSubtype: Header Func Desc */ + 0x10, /* bcdCDC: spec release number */ + 0x01, + + /*Call Management Functional Descriptor*/ + 0x05, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x01, /* bDescriptorSubtype: Call Management Func Desc */ + 0x00, /* bmCapabilities: D0+D1 */ + 0x01, /* bDataInterface: 1 */ + + /*ACM Functional Descriptor*/ + 0x04, /* bFunctionLength */ + 0x24, /* bDescriptorType: CS_INTERFACE */ + 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ + 0x02, /* bmCapabilities */ + + /*Endpoint 1 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + 0x05, /* bDescriptorType: Endpoint */ + 0x81, /* bEndpointAddress IN1 */ + 0x03, /* bmAttributes: Interrupt */ + 64, /* wMaxPacketSize LO: */ + 0x00, /* wMaxPacketSize HI: */ + 0x10, /* bInterval: */ + /*---------------------------------------------------------------------------*/ + + /*Endpoint IN3 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + 0x05, /* bDescriptorType: Endpoint */ + 0x83, /* bEndpointAddress IN3 */ + 0x02, /* bmAttributes: Bulk */ + 64, /* wMaxPacketSize: */ + 0x00, + 0x00, /* bInterval: ignore for Bulk transfer */ + + /*Endpoint OUT2 Descriptor*/ + 0x07, /* bLength: Endpoint Descriptor size */ + 0x05, /* bDescriptorType: Endpoint */ + 0x02, /* bEndpointAddress */ + 0x02, /* bmAttributes: Bulk */ + 64, /* wMaxPacketSize: */ + 0x00, + 0x00 /* bInterval: ignore for Bulk transfer */ +}; + +const uint8_t USB_StringLangDescriptor[] = { + STRING_LANG_DESCRIPTOR_SIZE_BYTE, //bLength + 0x03, //bDescriptorType + 0x09, //wLANGID_L + 0x04 //wLANGID_H +}; + +//~ typedef struct{ + //~ uint8_t bLength; + //~ uint8_t bDescriptorType; + //~ uint16_t bString[]; +//~ } StringDescriptor; + +#define _USB_STRING_(name, str) \ +const struct name \ +{ \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + wchar_t bString[(sizeof(str) - 2) / 2]; \ + \ +} \ +name = {sizeof(name), 0x03, str}; + +_USB_STRING_(USB_StringSerialDescriptor, L"0.01") +_USB_STRING_(USB_StringManufacturingDescriptor, L"Russia, SAO RAS") +_USB_STRING_(USB_StringProdDescriptor, L"TSYS01 sensors controller") + +usb_dev_t USB_Dev; +ep_t endpoints[MAX_ENDPOINTS]; + +/* +bmRequestType: 76543210 +7 direction: 0 - host->device, 1 - device->host +65 type: 0 - standard, 1 - class, 2 - vendor +4..0 getter: 0 - device, 1 - interface, 2 - endpoint, 3 - other +*/ +/** + * Endpoint0 (control) handler + * @param ep - endpoint state + * @return data written to EP0R + */ +uint16_t Enumerate_Handler(ep_t ep){ + config_pack_t *packet = (config_pack_t *)ep.rx_buf; + uint16_t status = 0; // bus powered + void wr0(const uint8_t *buf, uint16_t size){ + if(packet->wLength < size) size = packet->wLength; + EP_WriteIRQ(0, buf, size); + } + if ((ep.rx_flag) && (ep.setup_flag)){ + if (packet -> bmRequestType == 0x80){ // get device properties + switch(packet->bRequest){ + case GET_DESCRIPTOR: + switch(packet->wValue){ + case DEVICE_DESCRIPTOR: + wr0(USB_DeviceDescriptor, sizeof(USB_DeviceDescriptor)); + break; + case CONFIGURATION_DESCRIPTOR: + wr0(USB_ConfigDescriptor, sizeof(USB_ConfigDescriptor)); + break; + case STRING_LANG_DESCRIPTOR: + wr0(USB_StringLangDescriptor, STRING_LANG_DESCRIPTOR_SIZE_BYTE); + break; + case STRING_MAN_DESCRIPTOR: + wr0((const uint8_t *)&USB_StringManufacturingDescriptor, USB_StringManufacturingDescriptor.bLength); + break; + case STRING_PROD_DESCRIPTOR: + wr0((const uint8_t *)&USB_StringProdDescriptor, USB_StringProdDescriptor.bLength); + break; + case STRING_SN_DESCRIPTOR: + wr0((const uint8_t *)&USB_StringSerialDescriptor, USB_StringSerialDescriptor.bLength); + break; + case DEVICE_QALIFIER_DESCRIPTOR: + wr0(USB_DeviceQualifierDescriptor, DEVICE_QALIFIER_SIZE_BYTE); + break; + default: + MSG("val"); + printuhex(packet->wValue); + newline(); + } + break; + case GET_STATUS: + EP_WriteIRQ(0, (uint8_t *)&status, 2); // send status: Bus Powered + break; + default: + MSG("req"); + printuhex(packet->bRequest); + newline(); + } + // , + ep.status = SET_NAK_RX(ep.status); + ep.status = SET_VALID_TX(ep.status); + }else if(packet->bmRequestType == 0x00){ // set device properties + switch(packet->bRequest){ + case SET_ADDRESS: + // DADDR , + // + USB_Dev.USB_Addr = packet -> wValue; + break; + case SET_CONFIGURATION: + // "" + USB_Dev.USB_Status = USB_CONFIGURE_STATE; + break; + default: + MSG("req"); + printuhex(packet->bRequest); + newline(); + } + // + EP_WriteIRQ(0, (uint8_t *)0, 0); + // , + ep.status = SET_NAK_RX(ep.status); + ep.status = SET_VALID_TX(ep.status); + }else if(packet -> bmRequestType == 0x02){ + if (packet->bRequest == CLEAR_FEATURE){ + // + EP_WriteIRQ(0, (uint8_t *)0, 0); + // , + ep.status = SET_NAK_RX(ep.status); + ep.status = SET_VALID_TX(ep.status); + }else{ + MSG("req"); + printuhex(packet->bRequest); + newline(); + } + } + } else + if (ep.rx_flag){ // + // + // DTOG + ep.status = CLEAR_DTOG_RX(ep.status); + ep.status = CLEAR_DTOG_TX(ep.status); + // , + ep.status = SET_VALID_RX(ep.status); + ep.status = SET_STALL_TX(ep.status); + } else + if (ep.tx_flag){ // + // + if ((USB -> DADDR & USB_DADDR_ADD) != USB_Dev.USB_Addr){ + // + USB -> DADDR = USB_DADDR_EF | USB_Dev.USB_Addr; + // "" + USB_Dev.USB_Status = USB_ADRESSED_STATE; + } + // , DTOG + ep.status = CLEAR_DTOG_RX(ep.status); + ep.status = CLEAR_DTOG_TX(ep.status); + // , ( ) + // Rx Tx VALID + ep.status = SET_VALID_RX(ep.status); + ep.status = SET_VALID_TX(ep.status); + } + // ep.status EPnR + // + return ep.status; +} + +/* + * + * number - (0...7) + * type - (EP_TYPE_BULK, EP_TYPE_CONTROL, EP_TYPE_ISO, EP_TYPE_INTERRUPT) + * addr_tx - USB + * addr_rx - USB + * - 64 + * uint16_t (*func)(ep_t *ep) - () + */ +void EP_Init(uint8_t number, uint8_t type, uint16_t addr_tx, uint16_t addr_rx, uint16_t (*func)(ep_t ep)){ + USB -> EPnR[number] = (type << 9) | (number & USB_EPnR_EA); + USB -> EPnR[number] ^= USB_EPnR_STAT_RX | USB_EPnR_STAT_TX_1; + USB_BTABLE -> EP[number].USB_ADDR_TX = addr_tx; + USB_BTABLE -> EP[number].USB_COUNT_TX = 0; + USB_BTABLE -> EP[number].USB_ADDR_RX = addr_rx; + USB_BTABLE -> EP[number].USB_COUNT_RX = 0x8400; // buffer size (64 bytes): Table127 of RM: BL_SIZE=1, NUM_BLOCK=1 + endpoints[number].func = func; + endpoints[number].tx_buf = (uint16_t *)(USB_BTABLE_BASE + addr_tx); + endpoints[number].rx_buf = (uint8_t *)(USB_BTABLE_BASE + addr_rx); +} + +// USB +void usb_isr(){ + uint8_t n; + if (USB -> ISTR & USB_ISTR_RESET){ + // Reinit registers + USB -> CNTR = USB_CNTR_RESETM | USB_CNTR_CTRM; + USB -> ISTR = 0; + // Endpoint 0 - CONTROL (128 bytes for TX and 64 for RX) + EP_Init(0, EP_TYPE_CONTROL, 64, 192, Enumerate_Handler); + // + USB -> DADDR = USB_DADDR_EF; + // DEFAULT ( ) + USB_Dev.USB_Status = USB_DEFAULT_STATE; + } + if (USB -> ISTR & USB_ISTR_CTR){ + // , + n = USB -> ISTR & USB_ISTR_EPID; + // + endpoints[n].rx_cnt = USB_BTABLE -> EP[n].USB_COUNT_RX; + // EPnR + endpoints[n].status = USB -> EPnR[n]; + // + endpoints[n].rx_flag = 0; + endpoints[n].tx_flag = 0; + endpoints[n].setup_flag = 0; + // + if (endpoints[n].status & USB_EPnR_CTR_RX) endpoints[n].rx_flag = 1; + if (endpoints[n].status & USB_EPnR_SETUP) endpoints[n].setup_flag = 1; + if (endpoints[n].status & USB_EPnR_CTR_TX) endpoints[n].tx_flag = 1; + // - + // EPnR + endpoints[n].status = endpoints[n].func(endpoints[n]); + // DTOG + endpoints[n].status = KEEP_DTOG_TX(endpoints[n].status); + endpoints[n].status = KEEP_DTOG_RX(endpoints[n].status); + // + endpoints[n].status = CLEAR_CTR_RX(endpoints[n].status); + endpoints[n].status = CLEAR_CTR_TX(endpoints[n].status); + USB -> EPnR[n] = endpoints[n].status; + } +} +/* + * ( ) + * number - + * *buf - + * size - + */ +void EP_WriteIRQ(uint8_t number, const uint8_t *buf, uint16_t size){ + uint8_t i; +/* + * + * - USB/CAN SRAM 8- + * 16-, + * 2, , 2 + 1 + */ + uint16_t temp = (size & 0x0001) ? (size + 1) / 2 : size / 2; + uint16_t *buf16 = (uint16_t *)buf; + for (i = 0; i < temp; i++){ + endpoints[number].tx_buf[i] = buf16[i]; + } + // + USB_BTABLE -> EP[number].USB_COUNT_TX = size; +} +/* + * ( ) + * number - + * *buf - + * size - + */ +void EP_Write(uint8_t number, const uint8_t *buf, uint16_t size){ + uint8_t i; + uint16_t status = USB -> EPnR[number]; +/* + * + * - USB/CAN SRAM 8- + * 16-, + * 2, , 2 + 1 + */ + uint16_t temp = (size & 0x0001) ? (size + 1) / 2 : size / 2; + uint16_t *buf16 = (uint16_t *)buf; + for (i = 0; i < temp; i++){ + endpoints[number].tx_buf[i] = buf16[i]; + } + // + USB_BTABLE -> EP[number].USB_COUNT_TX = size; + + status = SET_NAK_RX(status); //RX NAK + status = SET_VALID_TX(status); //TX VALID + status = KEEP_DTOG_TX(status); + status = KEEP_DTOG_RX(status); + USB -> EPnR[number] = status; +} + +/* + * + * number - + * *buf - + */ +void EP_Read(uint8_t number, uint8_t *buf){ + uint16_t i; + for (i = 0; i < endpoints[number].rx_cnt; i++){ + buf[i] = endpoints[number].rx_buf[i]; + } +} +// USB +uint8_t USB_GetState(){ + return USB_Dev.USB_Status; +} diff --git a/F0-nolib/usbcdc/usb_lib.h b/F0-nolib/usbcdc/usb_lib.h new file mode 100644 index 0000000..eb45e85 --- /dev/null +++ b/F0-nolib/usbcdc/usb_lib.h @@ -0,0 +1,130 @@ +#pragma once +#ifndef __USB_LIB_H__ +#define __USB_LIB_H__ + +#include "usb_defs.h" + +// +#define MAX_ENDPOINTS 2 +// bRequest, standard; for bmRequestType == 0x80 +#define GET_STATUS 0x00 +#define GET_DESCRIPTOR 0x06 +#define GET_CONFIGURATION 0x08 // +// for bmRequestType == 0 +#define CLEAR_FEATURE 0x01 +#define SET_FEATURE 0x03 // +#define SET_ADDRESS 0x05 +#define SET_DESCRIPTOR 0x07 // +#define SET_CONFIGURATION 0x09 +// for bmRequestType == 0x81, 1 or 0xB2 +#define GET_INTERFACE 0x0A // +#define SET_INTERFACE 0x0B // +#define SYNC_FRAME 0x0C // + +// Class-Specific Control Requests +#define SEND_ENCAPSULATED_COMMAND 0x00 +#define GET_ENCAPSULATED_RESPONSE 0x01 +#define SET_COMM_FEATURE 0x02 +#define GET_COMM_FEATURE 0x03 +#define CLEAR_COMM_FEATURE 0x04 +#define SET_LINE_CODING 0x20 +#define GET_LINE_CODING 0x21 +#define SET_CONTROL_LINE_STATE 0x22 +#define SEND_BREAK 0x23 + +/* Line Coding Structure from CDC spec 6.2.13 +struct usb_cdc_line_coding { + __le32 dwDTERate; + __u8 bCharFormat; +#define USB_CDC_1_STOP_BITS 0 +#define USB_CDC_1_5_STOP_BITS 1 +#define USB_CDC_2_STOP_BITS 2 + + __u8 bParityType; +#define USB_CDC_NO_PARITY 0 +#define USB_CDC_ODD_PARITY 1 +#define USB_CDC_EVEN_PARITY 2 +#define USB_CDC_MARK_PARITY 3 +#define USB_CDC_SPACE_PARITY 4 + + __u8 bDataBits; +} __attribute__ ((packed)); +*/ + +// wValue +#define DEVICE_DESCRIPTOR 0x100 +#define CONFIGURATION_DESCRIPTOR 0x200 +#define STRING_LANG_DESCRIPTOR 0x300 +#define STRING_MAN_DESCRIPTOR 0x301 +#define STRING_PROD_DESCRIPTOR 0x302 +#define STRING_SN_DESCRIPTOR 0x303 +#define DEVICE_QALIFIER_DESCRIPTOR 0x600 +// / EPnR +#define CLEAR_DTOG_RX(R) (R & USB_EPnR_DTOG_RX) ? R : (R & (~USB_EPnR_DTOG_RX)) +#define SET_DTOG_RX(R) (R & USB_EPnR_DTOG_RX) ? (R & (~USB_EPnR_DTOG_RX)) : R +#define TOGGLE_DTOG_RX(R) (R | USB_EPnR_DTOG_RX) +#define KEEP_DTOG_RX(R) (R & (~USB_EPnR_DTOG_RX)) +#define CLEAR_DTOG_TX(R) (R & USB_EPnR_DTOG_TX) ? R : (R & (~USB_EPnR_DTOG_TX)) +#define SET_DTOG_TX(R) (R & USB_EPnR_DTOG_TX) ? (R & (~USB_EPnR_DTOG_TX)) : R +#define TOGGLE_DTOG_TX(R) (R | USB_EPnR_DTOG_TX) +#define KEEP_DTOG_TX(R) (R & (~USB_EPnR_DTOG_TX)) +#define SET_VALID_RX(R) ((R & USB_EPnR_STAT_RX) ^ USB_EPnR_STAT_RX) | (R & (~USB_EPnR_STAT_RX)) +#define SET_NAK_RX(R) ((R & USB_EPnR_STAT_RX) ^ USB_EPnR_STAT_RX_1) | (R & (~USB_EPnR_STAT_RX)) +#define SET_STALL_RX(R) ((R & USB_EPnR_STAT_RX) ^ USB_EPnR_STAT_RX_0) | (R & (~USB_EPnR_STAT_RX)) +#define KEEP_STAT_RX(R) (R & (~USB_EPnR_STAT_RX)) +#define SET_VALID_TX(R) ((R & USB_EPnR_STAT_TX) ^ USB_EPnR_STAT_TX) | (R & (~USB_EPnR_STAT_TX)) +#define SET_NAK_TX(R) ((R & USB_EPnR_STAT_TX) ^ USB_EPnR_STAT_TX_1) | (R & (~USB_EPnR_STAT_TX)) +#define SET_STALL_TX(R) ((R & USB_EPnR_STAT_TX) ^ USB_EPnR_STAT_TX_0) | (R & (~USB_EPnR_STAT_TX)) +#define KEEP_STAT_TX(R) (R & (~USB_EPnR_STAT_TX)) +#define CLEAR_CTR_RX(R) (R & (~USB_EPnR_CTR_RX)) +#define CLEAR_CTR_TX(R) (R & (~USB_EPnR_CTR_TX)) +#define CLEAR_CTR_RX_TX(R) (R & (~(USB_EPnR_CTR_TX | USB_EPnR_CTR_RX))) +// USB +#define USB_DEFAULT_STATE 0 +#define USB_ADRESSED_STATE 1 +#define USB_CONFIGURE_STATE 2 +// +#define EP_TYPE_BULK 0x00 +#define EP_TYPE_CONTROL 0x01 +#define EP_TYPE_ISO 0x02 +#define EP_TYPE_INTERRUPT 0x03 + +// +typedef struct { + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} config_pack_t; +// +typedef struct __ep_t{ + uint16_t *tx_buf; + uint8_t *rx_buf; + uint16_t (*func)(); + uint16_t status; + unsigned rx_cnt : 10; + unsigned tx_flag : 1; + unsigned rx_flag : 1; + unsigned setup_flag : 1; +} ep_t; +// USB +typedef struct { + uint8_t USB_Status; + uint16_t USB_Addr; +} usb_dev_t; + +// USB +void USB_Init(); +// USB +uint8_t USB_GetState(); +// +void EP_Init(uint8_t number, uint8_t type, uint16_t addr_tx, uint16_t addr_rx, uint16_t (*func)(ep_t ep)); +// +void EP_WriteIRQ(uint8_t number, const uint8_t *buf, uint16_t size); +// +void EP_Write(uint8_t number, const uint8_t *buf, uint16_t size); +// +void EP_Read(uint8_t number, uint8_t *buf); + +#endif // __USB_LIB_H__ diff --git a/F0-nolib/usbcdc/usbcan.bin b/F0-nolib/usbcdc/usbcan.bin new file mode 100755 index 0000000000000000000000000000000000000000..a2d4e713b05577c554b3efe4bdd81244dd8a9b5c GIT binary patch literal 8660 zcmcgR3v?6Lm2dR1WZ7U@!XS-5nHf1?up#n~pF=We%-GflVr&|WO*bRkG9!K#wgJ&( zPlg0GCT@0(ozsF%8V;e|hNP*FTBq3*8W-9ov}q&Rc-P=Gak8gT(k87MnivE2?0sX| zkWbS+XU|!kbM@}K_rCk?z3;yJ-jk3GQIiXhaRT5I0Q40fEHlH#_@2b+F?ifRg5m## z%se zcapv!CYN8-Uy#y?^u#3Yf+#zBiEgj#7=`aZ*#M8s8kRtF5qMdyD9Qyzxv3x>DsSKe z{pr$Zdsaq=3tgU@@nYzzA!WENqtSdiWDqhX@>B2H&R5wrnc7E@6WoBq$@CHp>^x+q z(?c1ohwbJvxYHpD8Ty>(l7e#X$}q}xM1-I|7eyW&OU#wR53En4a}W`GXoAR@2nWbm z(@w<7Ku_I-er&anE|Ic^DFmwq7)MCX?jlI`G_i>-c3asD>07o({D~HB62`2A+;O z!3>F5Q}`@__;YOk11gWg+Hr=pNw zTM-Kzh;lj+dXj`JgS=2)QIzKaC$tDPLW}c7c|%bi0{kX`7U<@5WTXI20t7OUF$3CP z0MFTPUZ0ZvJg;LbG&FYzHI~xiola6{vx4vXO%u{_z+{!kc~2f=q|LSkrZvxGPjFm zDNP0{nsoL{ zq+T~{rdsTg2MI3Hnx0^~wBLS13T!zby)1Q>Sp*yV(m_hRc1}mP+OIrl;;yv*IclWO zA24y}_mKMchR5Quzuiw3{KdZd31l1q9Iwm0_aYSQA2L{n@6Xt0ele6N=!j?ya%@F& z>hSJfQ~e#--FjgFo#4e%mmE8HzwyJ!r?Y!JLx}a4@xS9w@N)lSXj^HC)Css1jT&;| z8q)*~F?gHCwCW$Zt__(%<8hwj%S$=AfghmBknA`@q_Vw)z?v#dtd)b^9ja!HknJU6 z^4U)QIFIN4ugE)5ynZt^2ItKykWX5|RBrAcut9k&dbb@py7Y-*mo&Kb*PGsLCkngt zy`io--L6kY&F2PqJeCk_L0tdT-0aWt9PZP0KNU))DG0|d1y_e1{OE(E!8UC3OjGMs zYFdSsQpR6XoQ|)vRw0wMdaUZ0YL%OV^iX^13|EKedMqlvOr=lPsvT^aTB|bI^-!xa zxgUhyj;_o^Mh`$9*rdFHP#fSPK%hSh9qN0L$o62nUYs*+1N9lpvf`GdsZ>bl*!zlR z8S~}<)cCKnwzy>pam#dl0o5{V+_LLa*vr3f8Nnn9ri!e9NzhPaKpEelOzRztz7PBH zCO|gWX$IH{wqyHu0XX{|pNZwG>MYZ-q=z%(7N1qAq=%qrq>R(b4*tp!8g=Qr<`59w zpG@KC&V%UAi~Dd|mA@6;l(-Ma{(%nz{4uced4QStUIKgopxu$>PS;2LNt{d%d96D- zIBSFK*ti3qnlfG8a70tRBgu6$oJyw&Y2|h?P1qt4>=sd`YosH3f@7&IqFo|5JA6|s zajT`PB{-4ALrju@D+pq0p^6;eWr3aERF9N06g1@OCuQQ>gNE)A1Ids&$`qRG~VgrE#QdCg%$SKpRtOh}HmY z!=y!(>vVLXUW8~oOX(!x$PN4?3ffn#ggkp`lE}FhejRGe?)bXT-ZOhv3^o|q1?ogVy$$zPs7%Vr1V_5h9#jr zqqeouv(Tncwc?fSk8oG&$sOOr^ajNAh_yQ&=V}|Cahvl~Vf?9zTKL9b0zD_0EmD`( z#MO#2W0$IQCRkZgJfb5d6RfP3u9aXc$P%ltOfu6^AxKu%n0q5KKzF*23P;PUMeX*) zgmg{1DT&k8BS*KW1wWMWdv2iEu}Ks=bsfcicD>zWSEIZUqB0Riu^$4pVG70ePwp4$ zw)dih;e(zeRf1I|_5gJhs1JFPRcf(Hl^r|Wb-In)A&2Uf@gGhh2hqJ(*n8h`ey^}^ z!!drJ&;!uRSMz(_#Bov-_;l&GD`7<7|HhKns8n0{YCiWl)Ih_L`6f;a3XIlnyiF73(9>Vto=TUJ#kZqw8u1g z^TQ~Qh@6gUkI|s%gsSPOXco=#DE1%FI~SS8e+2l|@QYC{Xv+N{q7AxAMnh@2+L626 zy=bWBY5o*lQjTILK?;TcIeLm-0lnkU`#8KWI)^TXUKjLm^kWk!b{f{^rJMe!GamOt zD({u6_x)R*J43i4Vr(k9#A8c{$f zyc^wGqKkj5ucs72WWF`FK{&>5@MNfdC8{1&^EDEzJ9u!{O%Af4*RVZYCX{)O^JPN$ zdYn&&g>_OEONOiYDt=V@wq#gl9dT8J(Bn1V=E>y2kiLsF4Tf}Gqakf~$y`l$N%Clj z=q@phhETT>n$G>98#wv`PX_Dw^k7}6$F&x2-|kU?-Me5<8FBR;qZQzKrfTFUZp+l@*C=~U8hnhH^)E8rxOjO#=D#&nH4Xq@kLDE0i@G#fdfcm z<_Zp&xxWSz6GB0YE|qHu;B98iof53?{@*- ziX!H6^y34T1n`kU%vcnG&4@-u8-NTx9s^&raQD&W5D|hQ1Nb~@1K$Gu_Vu~Jhja5r zY@T%0>OWprYe78b1jIb$24c?K|DUKj<3(GFyDs!CdqS=yJlCBYNDUr$5n(3^oKxVO zKn|0~8ko+(S5+;4g^2$#iWYtp#W6h_k0*}v2;iNLQN7)-a~Rx55-t8D)}rf5v2q5c zhdblwMOF^Z4_Q4o;a!Sg4BXw?)jr@wLb2P{Ztm}NZ44K>i{LGcU&86yBu=5NV)gb8 z?x(A8MU@@P+`T${-V<=%=Lv8Is3%S;oCKO|QaS}aQo5&zf%Z-RooZIHzTs+F}fEWLGM=9SK3z9S7ubOgpuo{k07z~RqCA@86D-`sr3362uWOncY(0L zW3QoEd!v0C8-pT!sej3m~K5wVR2b`R~Lp$!+ep%1Q1d;V9fty5Tf530*q7 zA0pr-{YJQLlU`-KR>5~;JSS+U@O-ii6T#e2*d}q-Z&{D}bD_e|3D?9=yb<-anFICZ zIXLr_3FOEXtAtV5jVLUS-6y2`G4|-#dZE`}XIK#Sco>?39eq|ESLUvmwW#bii`K<0 zN>yYgWf3O~59~IZyVl(ayZfkXYxv&vY}}3~Refs&8(7i=mb^US;+=v; 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+ +$(BIN): $(ELF) + @printf " OBJCOPY $(BIN)\n" + $(OBJCOPY) -Obinary $(ELF) $(BIN) + +$(HEX): $(ELF) + @printf " OBJCOPY $(HEX)\n" + $(OBJCOPY) -Oihex $(ELF) $(HEX) + +$(LIST): $(ELF) + @printf " OBJDUMP $(LIST)\n" + $(OBJDUMP) -S $(ELF) > $(LIST) + +$(ELF): $(OBJDIR) $(OBJS) $(LDSCRIPT) $(LIB_DIR)/lib$(LIBNAME).a + @printf " LD $(ELF)\n" + $(LD) $(LDFLAGS) $(ARCH_FLAGS) $(OBJS) $(LDLIBS) -o $(ELF) + +clean: + @printf " CLEAN\n" + $(RM) $(OBJS) $(OBJDIR)/*.d $(ELF) $(HEX) $(LIST) $(OBJDIR)/*.map + $(RMDIR) $(OBJDIR) + +flash: $(BIN) + @printf " FLASH $(BIN)\n" + $(STFLASH) write $(BIN) 0x8000000 + +boot: $(BIN) + @printf " LOAD $(BIN) through bootloader\n" + $(STBOOT) -b$(BOOTSPEED) $(BOOTPORT) -w $(BIN) + +.PHONY: clean elf hex list flash boot + +#-include $(OBJS:.o=.d) diff --git a/F1/2.8TFT/README b/F1/2.8TFT/README new file mode 100644 index 0000000..717ea64 --- /dev/null +++ b/F1/2.8TFT/README @@ -0,0 +1,5 @@ +Template of USB-CDC + +written for chinese devboard based on STM32F103R8T6 + +Press H for help \ No newline at end of file diff --git a/F1/2.8TFT/cdcacm.c b/F1/2.8TFT/cdcacm.c new file mode 100644 index 0000000..e694f69 --- /dev/null +++ b/F1/2.8TFT/cdcacm.c @@ -0,0 +1,310 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * Copyright 2014 Edward V. Emelianov + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include "cdcacm.h" +#include "user_proto.h" +#include "main.h" + +// Buffer for USB Tx +static uint8_t USB_Tx_Buffer[USB_TX_DATA_SIZE]; +static uint8_t USB_Tx_ptr = 0; +// connection flag +uint8_t USB_connected = 0; +static const struct usb_device_descriptor dev = { + .bLength = USB_DT_DEVICE_SIZE, + .bDescriptorType = USB_DT_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = USB_CLASS_CDC, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + .bMaxPacketSize0 = 64, + .idVendor = 0x0483, + .idProduct = 0x5740, + .bcdDevice = 0x0200, + .iManufacturer = 1, + .iProduct = 2, + .iSerialNumber = 3, + .bNumConfigurations = 1, +}; + +uint8_t usbdatabuf[USB_RX_DATA_SIZE]; // buffer for received data +int usbdatalen = 0; // lenght of received data + +/* + * This notification endpoint isn't implemented. According to CDC spec its + * optional, but its absence causes a NULL pointer dereference in Linux + * cdc_acm driver. + */ +static const struct usb_endpoint_descriptor comm_endp[] = {{ + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x83, + .bmAttributes = USB_ENDPOINT_ATTR_INTERRUPT, + .wMaxPacketSize = 16, + .bInterval = 255, +}}; + +static const struct usb_endpoint_descriptor data_endp[] = {{ + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x01, + .bmAttributes = USB_ENDPOINT_ATTR_BULK, + .wMaxPacketSize = 64, + .bInterval = 1, +}, { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0x82, + .bmAttributes = USB_ENDPOINT_ATTR_BULK, + .wMaxPacketSize = 64, + .bInterval = 1, +}}; + +static const struct { + struct usb_cdc_header_descriptor header; + struct usb_cdc_call_management_descriptor call_mgmt; + struct usb_cdc_acm_descriptor acm; + struct usb_cdc_union_descriptor cdc_union; +} __attribute__((packed)) cdcacm_functional_descriptors = { + .header = { + .bFunctionLength = sizeof(struct usb_cdc_header_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_HEADER, + .bcdCDC = 0x0110, + }, + .call_mgmt = { + .bFunctionLength = + sizeof(struct usb_cdc_call_management_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_CALL_MANAGEMENT, + .bmCapabilities = 0, + .bDataInterface = 1, + }, + .acm = { + .bFunctionLength = sizeof(struct usb_cdc_acm_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_ACM, + .bmCapabilities = 0, + }, + .cdc_union = { + .bFunctionLength = sizeof(struct usb_cdc_union_descriptor), + .bDescriptorType = CS_INTERFACE, + .bDescriptorSubtype = USB_CDC_TYPE_UNION, + .bControlInterface = 0, + .bSubordinateInterface0 = 1, + }, +}; + +static const struct usb_interface_descriptor comm_iface[] = {{ + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_CDC, + .bInterfaceSubClass = USB_CDC_SUBCLASS_ACM, + .bInterfaceProtocol = USB_CDC_PROTOCOL_AT, + .iInterface = 0, + + .endpoint = comm_endp, + + .extra = &cdcacm_functional_descriptors, + .extralen = sizeof(cdcacm_functional_descriptors), +}}; + +static const struct usb_interface_descriptor data_iface[] = {{ + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = 1, + .bAlternateSetting = 0, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_DATA, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, + .iInterface = 0, + + .endpoint = data_endp, +}}; + +static const struct usb_interface ifaces[] = {{ + .num_altsetting = 1, + .altsetting = comm_iface, +}, { + .num_altsetting = 1, + .altsetting = data_iface, +}}; + +static const struct usb_config_descriptor config = { + .bLength = USB_DT_CONFIGURATION_SIZE, + .bDescriptorType = USB_DT_CONFIGURATION, + .wTotalLength = 0, + .bNumInterfaces = 2, + .bConfigurationValue = 1, + .iConfiguration = 0, + .bmAttributes = 0x80, + .bMaxPower = 0x32, + + .interface = ifaces, +}; + +static const char *usb_strings[] = { + "Organisation, author", + "device", + "version", +}; + +// default line coding: B115200, 1stop, 8bits, parity none +struct usb_cdc_line_coding linecoding = { + .dwDTERate = 115200, + .bCharFormat = USB_CDC_1_STOP_BITS, + .bParityType = USB_CDC_NO_PARITY, + .bDataBits = 8, +}; + +/* Buffer to be used for control requests. */ +uint8_t usbd_control_buffer[128]; + +/** + * This function runs every time it gets a request for control parameters get/set + * parameter SET_LINE_CODING used to change USART1 parameters: if you want to + * change them, just connect through USB with required parameters + */ +static int cdcacm_control_request(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t **buf, + uint16_t *len, void (**complete)(usbd_device *usbd_dev, struct usb_setup_data *req)){ + (void)complete; + (void)buf; + (void)usbd_dev; + char local_buf[10]; + struct usb_cdc_line_coding lc; + + switch (req->bRequest) { + case SET_CONTROL_LINE_STATE:{ + if(req->wValue){ // terminal is opened + USB_connected = 1; + }else{ // terminal is closed + USB_connected = 0; + } + /* + * This Linux cdc_acm driver requires this to be implemented + * even though it's optional in the CDC spec, and we don't + * advertise it in the ACM functional descriptor. + */ + struct usb_cdc_notification *notif = (void *)local_buf; + /* We echo signals back to host as notification. */ + notif->bmRequestType = 0xA1; + notif->bNotification = USB_CDC_NOTIFY_SERIAL_STATE; + notif->wValue = 0; + notif->wIndex = 0; + notif->wLength = 2; + local_buf[8] = req->wValue & 3; + local_buf[9] = 0; + usbd_ep_write_packet(usbd_dev, 0x83, local_buf, 10); + }break; + case SET_LINE_CODING: + if (!len || (*len != sizeof(struct usb_cdc_line_coding))) + return 0; + memcpy((void *)&lc, (void *)*buf, *len); + // Mark & Space parity don't support by hardware, check it + if(lc.bParityType == USB_CDC_MARK_PARITY || lc.bParityType == USB_CDC_SPACE_PARITY){ + return 0; // error + } + break; + case GET_LINE_CODING: // return linecoding buffer + if(len && *len == sizeof(struct usb_cdc_line_coding)) + memcpy((void *)*buf, (void *)&linecoding, sizeof(struct usb_cdc_line_coding)); + break; + default: + return 0; + } + return 1; +} + +static void cdcacm_data_rx_cb(usbd_device *usbd_dev, uint8_t ep){ + (void)ep; + int len = usbd_ep_read_packet(usbd_dev, 0x01, usbdatabuf + usbdatalen, USB_RX_DATA_SIZE - usbdatalen); + usbdatalen += len; + if(usbdatalen >= USB_RX_DATA_SIZE){ // buffer overflow - drop all its contents + usbdatalen = 0; + } +} + +static void cdcacm_data_tx_cb(usbd_device *usbd_dev, uint8_t ep){ + (void)ep; + (void)usbd_dev; + + usb_send_buffer(); +} + +static void cdcacm_set_config(usbd_device *usbd_dev, uint16_t wValue) +{ + (void)wValue; + (void)usbd_dev; + + usbd_ep_setup(usbd_dev, 0x01, USB_ENDPOINT_ATTR_BULK, USB_RX_DATA_SIZE, cdcacm_data_rx_cb); + usbd_ep_setup(usbd_dev, 0x82, USB_ENDPOINT_ATTR_BULK, USB_TX_DATA_SIZE, cdcacm_data_tx_cb); + usbd_ep_setup(usbd_dev, 0x83, USB_ENDPOINT_ATTR_INTERRUPT, 16, NULL); + + usbd_register_control_callback( + usbd_dev, + USB_REQ_TYPE_CLASS | USB_REQ_TYPE_INTERFACE, + USB_REQ_TYPE_TYPE | USB_REQ_TYPE_RECIPIENT, + cdcacm_control_request); +} + +static usbd_device *current_usb = NULL; + +usbd_device *USB_init(){ + current_usb = usbd_init(&stm32f103_usb_driver, &dev, &config, + usb_strings, 3, usbd_control_buffer, sizeof(usbd_control_buffer)); + if(!current_usb) return NULL; + usbd_register_set_config_callback(current_usb, cdcacm_set_config); + return current_usb; +} + +mutex_t send_block_mutex = MUTEX_UNLOCKED; +/** + * Put byte into USB buffer to send + * @param byte - a byte to put into a buffer + */ +void usb_send(uint8_t byte){ + mutex_lock(&send_block_mutex); + USB_Tx_Buffer[USB_Tx_ptr++] = byte; + mutex_unlock(&send_block_mutex); + if(USB_Tx_ptr == USB_TX_DATA_SIZE){ // buffer can be overflowed - send it! + usb_send_buffer(); + } +} + +/** + * Send all data in buffer over USB + * this function runs when buffer is full or on SysTick + */ +void usb_send_buffer(){ + if(MUTEX_LOCKED == mutex_trylock(&send_block_mutex)) return; + if(USB_Tx_ptr){ + if(current_usb && USB_connected){ + // usbd_ep_write_packet return 0 if previous packet isn't transmit yet + while(USB_Tx_ptr != usbd_ep_write_packet(current_usb, 0x82, USB_Tx_Buffer, USB_Tx_ptr)); + usbd_poll(current_usb); + } + USB_Tx_ptr = 0; + } + mutex_unlock(&send_block_mutex); +} diff --git a/F1/2.8TFT/cdcacm.h b/F1/2.8TFT/cdcacm.h new file mode 100644 index 0000000..977167f --- /dev/null +++ b/F1/2.8TFT/cdcacm.h @@ -0,0 +1,54 @@ +/* + * ccdcacm.h + * + * Copyright 2014 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#pragma once +#ifndef __CCDCACM_H__ +#define __CCDCACM_H__ + +#include + +// commands through EP0 +#define SEND_ENCAPSULATED_COMMAND 0x00 +#define GET_ENCAPSULATED_RESPONSE 0x01 +#define SET_COMM_FEATURE 0x02 +#define GET_COMM_FEATURE 0x03 +#define CLEAR_COMM_FEATURE 0x04 +#define SET_LINE_CODING 0x20 +#define GET_LINE_CODING 0x21 +#define SET_CONTROL_LINE_STATE 0x22 +#define SEND_BREAK 0x23 + +// Size of input/output buffers +#define USB_TX_DATA_SIZE 64 +#define USB_RX_DATA_SIZE 64 + +// USB connection flag +extern uint8_t USB_connected; +extern struct usb_cdc_line_coding linecoding; + +extern uint8_t usbdatabuf[]; +extern int usbdatalen; + +usbd_device *USB_init(); +void usb_send(uint8_t byte); +void usb_send_buffer(); + +#endif // __CCDCACM_H__ diff --git a/F1/2.8TFT/dma_gpio.bin b/F1/2.8TFT/dma_gpio.bin new file mode 100755 index 0000000000000000000000000000000000000000..bd41cee318cb00e5e6b40845265801fe26526c27 GIT binary patch literal 7680 zcmd5hZFCdYmG{kzq>(JgGBO~45RW7S!ZL}1Num-b86YO|8zI*Sx@4ol$yYJm6=m5c40em&WoT~t?`cWAQluXO*{9m@YTF2G( z?dJb`o2zyFf3BN7OQz9f{f&_g#oRk9U;3aTFpCI)*S(gp#u}eneJDuBH%;7>`55M*V z1AG$)d=g84!rW$F?ox>JjjYHH#9wrP`nyYRWyo>6hkPi=I0l?2fAV>plV2cIC)&0+ z>lO{W>X>1n?$)$36N(D0_84)Nh9P4QKj(Tv;{*Y}1_4~9(jm<#9MX7!RausC9nvhq z6PnfcgjQ@LFZMbuXyGH5sxq&{Dx)Uvth8OZdn@ZFo~Khd143!$@AGsk()rd>rCk1D zbZ_LTt^2;sW*ice0Rb{Z;11i8kopX5gS>q#j^7fpw2;1to9Qzzv$R@5pc*b&+5}mM znU@iDnIAsceakDc(ongw zD`s0}-tz6(ENPCkc*_o_M=5S~<4TlY+8MZ*=0gtjFLlxo0#`+tZAqRD*YCDuhRn@*nfi+XM_`EID`ZF+T5U@ENC6*;hnpc~Lto<2mkcNq2{>dfMCIB?A^}>4o2|&BGPZ=Z zjkUPtBC6{ilwDdOmrqL$#Vce1aaymCQU5&^GM($oZMB4LIks3)(&m-*+y^?K4+@fw zYr1p1C6YmZE5W&K7{4Z@ zyKoF@Bro$LoZlzMP!?r5rxrHLAib)ZuSZ%XDo*r@uL16d9}CvaNz4vHqE2Q zEFU8oJ-1Wm77x{B(~%lMB8$QKd|b~xtbe~Qmu?@Sb}ktssEzs$)qi&t@TH+}qB3fb z&c|%iQ3TX?#;&0&jo#owi^}xtEbSxXn|)~U)YRp<8=E2xqiHUL<3_n~lIo-5qif(# zuoy7~p(&AZ+GTvM|^~KuV;b!^;H!Fvm zDWABI>nt72Q!{qSA)!CQ!q2{F26gkep4)Q?oM@>G>MzIi+=G|&+}x?okOS-QX?kw9 zuIIj?lRdVRVd`<&dQ_L9ZkW!qu1kieth)d zZL5#ph%J~)VLG$ln<~!oyhr1U8K;8!E>2RZswr?E z(imS&M$c`YVw{K2#^NjkdhXvRov8EVWI_7lNdct|Q%Q~T)=o=OJ;(BTv`fhGk$S3& z%6L3~JS9lNVr-*7AK!LH&pkS&=iZ$nd%&}8WXnqi)cxY*rZbhwF9ZG*%-wiqF|Mft z;~9Re9V|*j9OcUPz~pfn zPbi&Fw2#Q>k&DOMM+7W=jBN@Jf)T&w7A>dh z_|Vb|`_T8Sc)nfG46SH~Y;0X6^GOeY2*8L{2s9SdVA+6u+7h-_yJA-fJCVMowS8n; zqg^g;EtAt-#jR}Stu-#qE|U7k17m6IJy@XxRKirq)cOKO_a)Uy$IVUaN5mf$#-o2`

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Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include "dmagpio.h" +#include "user_proto.h" + +int transfer_complete = 0; +static uint16_t gpiobuff[128] = {0}; + +void dmagpio_init(){ + // init TIM2 & DMA1ch2 (TIM2UP) + rcc_periph_clock_enable(RCC_TIM2); + rcc_periph_clock_enable(RCC_DMA1); + timer_reset(TIM2); + // timer have frequency of 1MHz + timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); + // 72MHz div 18 = 4MHz + TIM2_PSC = 0; // prescaler is (div - 1) + TIM2_ARR = 1; // 36MHz (6.25) + TIM2_DIER = TIM_DIER_UDE;// | TIM_DIER_UIE; + dma_channel_reset(DMA1, DMA_CHANNEL2); + // mem2mem, medium prio, 8bits, memory increment, read from mem, transfer complete en + DMA1_CCR2 = DMA_CCR_PL_MEDIUM | DMA_CCR_MSIZE_16BIT | + DMA_CCR_PSIZE_16BIT | DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE | DMA_CCR_TEIE ; + nvic_enable_irq(NVIC_DMA1_CHANNEL2_IRQ); + // target address: + DMA1_CPAR2 = DMAGPIO_TARGADDR; + DMA1_CMAR2 = (uint32_t) gpiobuff; +} + +void dmagpio_transfer(uint8_t *databuf, uint32_t length){ + while(DMA1_CCR2 & DMA_CCR_EN); + transfer_complete = 0; + DMA1_IFCR = 0xff00; // clear all flags for ch2 + // buffer length + DMA1_CNDTR2 = length; + uint32_t i; + for(i = 0; i < length; ++i) gpiobuff[i] = databuf[i]; + TIM2_CR1 |= TIM_CR1_CEN; // run timer + DMA1_CCR2 |= DMA_CCR_EN; +} + +void dma1_channel2_isr(){ + if(DMA1_ISR & DMA_ISR_TCIF2){ + transfer_complete = 1; + // stop timer & turn off DMA + TIM2_CR1 &= ~TIM_CR1_CEN; + DMA1_CCR2 &= ~DMA_CCR_EN; + DMA1_IFCR = DMA_IFCR_CTCIF2; // clear flag + }else if(DMA1_ISR & DMA_ISR_TEIF2){ + P("Error\n"); + DMA1_IFCR = DMA_IFCR_CTEIF2; + TIM2_CR1 &= ~TIM_CR1_CEN; + DMA1_CCR2 &= ~DMA_CCR_EN; + } +} diff --git a/F1/2.8TFT/dmagpio.h b/F1/2.8TFT/dmagpio.h new file mode 100644 index 0000000..5ee0605 --- /dev/null +++ b/F1/2.8TFT/dmagpio.h @@ -0,0 +1,32 @@ +/* + * dmagpio.h + * + * Copyright 2016 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#pragma once +#ifndef __DMAGPIO_H__ +#define __DMAGPIO_H__ + +#include "main.h" +#include "hardware_ini.h" + +void dmagpio_init(); +void dmagpio_transfer(uint8_t *databuf, uint32_t length); +extern int transfer_complete; + +#endif // __DMAGPIO_H__ diff --git a/F1/2.8TFT/hardware_ini.c b/F1/2.8TFT/hardware_ini.c new file mode 100644 index 0000000..9503608 --- /dev/null +++ b/F1/2.8TFT/hardware_ini.c @@ -0,0 +1,72 @@ +/* + * hardware_ini.c - functions for HW initialisation + * + * Copyright 2014 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +/* + * All hardware-dependent initialisation & definition should be placed here + * and in hardware_ini.h + * + */ + +#include "main.h" +#include "hardware_ini.h" + +/** + * GPIO initialisaion: clocking + pins setup + */ +void GPIO_init(){ + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | + RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_IOPEEN); + // DMAGPIO + gpio_set_mode(LCD_CONTROL_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, + LCD_CS_PIN | LCD_RD_PIN | LCD_RS_PIN | LCD_WR_PIN | LCD_RST_PIN); + LCD_write(); // set pins as out + /* + // Buttons: pull-up input + gpio_set_mode(BTNS_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, + BTN_S2_PIN | BTN_S3_PIN); + // turn on pull-up + gpio_set(BTNS_PORT, BTN_S2_PIN | BTN_S3_PIN); + // LEDS: opendrain output + gpio_set_mode(LEDS_PORT, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, + LED_D1_PIN | LED_D2_PIN); + // turn off LEDs + gpio_set(LEDS_PORT, LED_D1_PIN | LED_D2_PIN); + */ +/* + // USB_DISC: push-pull + gpio_set_mode(USB_DISC_PORT, GPIO_MODE_OUTPUT_2_MHZ, + GPIO_CNF_OUTPUT_PUSHPULL, USB_DISC_PIN); + // USB_POWER: open drain, externall pull down with R7 (22k) + gpio_set_mode(USB_POWER_PORT, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_FLOAT, USB_POWER_PIN); +*/ +} + +/* + * SysTick used for system timer with period of 1ms + */ +void SysTick_init(){ + systick_set_clocksource(STK_CSR_CLKSOURCE_AHB_DIV8); // Systyck: 72/8=9MHz + systick_set_reload(8999); // 9000 pulses: 1kHz + systick_interrupt_enable(); + systick_counter_enable(); +} diff --git a/F1/2.8TFT/hardware_ini.h b/F1/2.8TFT/hardware_ini.h new file mode 100644 index 0000000..91f046c --- /dev/null +++ b/F1/2.8TFT/hardware_ini.h @@ -0,0 +1,95 @@ +/* + * hardware_ini.h + * + * Copyright 2014 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#pragma once +#ifndef __HARDWARE_INI_H__ +#define __HARDWARE_INI_H__ + +/* + * Timers: + * SysTick - system time + */ + + +void GPIO_init(); +void SysTick_init(); + +/* + * DMA to GPIO port & pins (mask) - PA0..PA7 + */ +#define DMAGPIO_PORT GPIOA +#define DMAGPIO_PINS 0xff +#define DMAGPIO_TARGADDR ((uint32_t)&(GPIOA_ODR)) + +#define LCD_write() do{gpio_set_mode(DMAGPIO_PORT, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL, DMAGPIO_PINS);}while(0) +//#define LCD_read() do{gpio_set_mode(DMAGPIO_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, DMAGPIO_PINS);}while(0) +#define LCD_read() do{gpio_set_mode(DMAGPIO_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_PULL_UPDOWN, DMAGPIO_PINS); GPIO_ODR(DMAGPIO_PORT) = 0;}while(0) +// LCD control pins (PB10..PB14) +#define LCD_CONTROL_PORT GPIOB +#define LCD_CS_PIN GPIO12 +#define LCD_RS_PIN GPIO11 +#define LCD_WR_PIN GPIO14 +#define LCD_RD_PIN GPIO13 +#define LCD_RST_PIN GPIO10 + +// macro for control pins manipulation +#define CS_set do{GPIO_BSRR(LCD_CONTROL_PORT) = LCD_CS_PIN;}while(0) +#define RS_set do{GPIO_BSRR(LCD_CONTROL_PORT) = LCD_RS_PIN;}while(0) +#define RD_set do{GPIO_BSRR(LCD_CONTROL_PORT) = LCD_RD_PIN;}while(0) +#define WR_set do{GPIO_BSRR(LCD_CONTROL_PORT) = LCD_WR_PIN;}while(0) +#define CS_clear do{GPIO_BSRR(LCD_CONTROL_PORT) = LCD_CS_PIN << 16;}while(0) +#define RS_clear do{GPIO_BSRR(LCD_CONTROL_PORT) = LCD_RS_PIN << 16;}while(0) +#define RD_clear do{GPIO_BSRR(LCD_CONTROL_PORT) = LCD_RD_PIN << 16;}while(0) +#define WR_clear do{GPIO_BSRR(LCD_CONTROL_PORT) = LCD_WR_PIN << 16;}while(0) +#define RST_set do{GPIO_BSRR(LCD_CONTROL_PORT) = LCD_RST_PIN;}while(0) +#define RST_clear do{GPIO_BSRR(LCD_CONTROL_PORT) = LCD_RST_PIN << 16;}while(0) + +#define LCD_wrbyte(x) do{GPIO_ODR(DMAGPIO_PORT) = x;}while(0) +/* +#define LCD_wrbyte(x) do{GPIO_BSRR(DMAGPIO_PORT) = DMAGPIO_PINS << 16; \ + GPIO_BSRR(DMAGPIO_PORT) = x;}while(0) +*/ +#define LCD_rdbyte() (GPIO_IDR(DMAGPIO_PORT) & DMAGPIO_PINS) + +/* + * USB interface + * connect boot1 jumper to gnd, boot0 to gnd; and reconnect boot0 to +3.3 to boot flash + */ +/* +// USB_DICS (disconnect) - PC11 +#define USB_DISC_PIN GPIO11 +#define USB_DISC_PORT GPIOC +// USB_POWER (high level when USB connected to PC) +#define USB_POWER_PIN GPIO10 +#define USB_POWER_PORT GPIOC +// change signal level on USB diconnect pin +#define usb_disc_high() gpio_set(USB_DISC_PORT, USB_DISC_PIN) +#define usb_disc_low() gpio_clear(USB_DISC_PORT, USB_DISC_PIN) +// in case of n-channel FET on 1.5k pull-up change on/off disconnect means low level +// in case of pnp bipolar transistor or p-channel FET on 1.5k pull-up disconnect means high level +#define usb_disconnect() usb_disc_high() +#define usb_connect() usb_disc_low() +*/ +// my simple devboard have no variants for programmed connection/disconnection of USB +#define usb_disconnect() +#define usb_connect() + +#endif // __HARDWARE_INI_H__ diff --git a/F1/2.8TFT/lcd.c b/F1/2.8TFT/lcd.c new file mode 100644 index 0000000..12fa987 --- /dev/null +++ b/F1/2.8TFT/lcd.c @@ -0,0 +1,433 @@ +/* + * lcd.c + * + * Copyright 2016 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include "main.h" +#include "lcd.h" +#include "hardware_ini.h" +#include "dmagpio.h" +#include "registers.h" + +static uint16_t LCD_id = 0; +#define nop() __asm__("nop") +uint8_t readbyte(){ + RD_clear; + nop(); + uint8_t byte = LCD_rdbyte(); + RD_set; + nop(); + return byte; +} +void writebyte(uint8_t b){ + LCD_wrbyte(b); + WR_clear; + nop(); + WR_set; + nop(); +} +void writereg(uint16_t r){ + LCD_wrbyte(r >> 8); + RS_clear; + WR_clear; + nop(); + WR_set; + LCD_wrbyte(r & 0xff); + nop(); + WR_clear; + nop(); + WR_set; + RS_set; +} + +uint16_t read_reg(uint16_t reg){ + uint32_t dat = 0; + CS_clear; // active + writereg(reg); + LCD_read(); + dat = readbyte() << 8; + dat |= readbyte(); + CS_set; + LCD_write(); // restore dir to out + return dat; +} + +void write_reg(uint16_t reg, uint16_t dat){ + CS_clear; // active + writereg(reg); + RS_set; // data + writebyte(dat >> 8); + writebyte(dat && 0xff); + CS_set; +} + +/* +typedef union{ + uint8_t bytes[4]; + uint32_t word; +}word32; + +void write16_16(uint16_t reg, uint16_t dat){ + CS_clear; // active + RS_clear; // register + LCD_write(); // dir: out + writebyte(reg >> 8); + writebyte(reg && 0xff); + RS_set; // data + writebyte(dat >> 8); + writebyte(dat && 0xff); + CS_set; +} + +void write_reg16_var(uint16_t reg, uint32_t dat, uint8_t len){ + int i; + CS_clear; // active + RS_clear; // register + LCD_write(); // dir: out + writebyte(reg >> 8); + writebyte(reg && 0xff); + RS_set; // data + word32 w; + w.word = dat; + --len; + for(i = len; i > -1; --i){ + writebyte(w.bytes[i]); + } + CS_set; +} + +void write_reg_var(uint8_t reg, uint32_t dat, uint8_t len){ + int i; + CS_clear; // active + RS_clear; // register + LCD_write(); // dir: out + writebyte(reg); + RS_set; // data + word32 w; + w.word = dat; + --len; + for(i = len; i > -1; --i){ + writebyte(w.bytes[i]); + } + CS_set; +} + +uint32_t read_reg_var(uint8_t reg, uint8_t len){ + uint32_t dat = 0; + int i; + CS_clear; // active + RS_clear; // register + LCD_write(); // dir: out + writebyte(reg); + LCD_read(); + RS_set; // data + for(i = 0; i < len; ++i){ + dat <<= 8; + dat = dat | readbyte(); + } + CS_set; + return dat; +} +uint32_t read16_reg_var(uint16_t reg, uint8_t len){ + uint32_t dat = 0; + int i; + CS_clear; // active + RS_clear; // register + LCD_write(); // dir: out + writebyte(reg >> 8); + writebyte(reg & 0xff); + LCD_read(); + RS_set; // data + for(i = 0; i < len; ++i){ + dat <<= 8; + dat = dat | readbyte(); + } + CS_set; + return dat; +} +*/ + +uint16_t LCD_status_read(){ + uint16_t dat; + LCD_read(); + CS_clear; + RS_clear; + dat = readbyte() << 8; + dat |= readbyte(); + RS_set; + CS_set; + LCD_write(); + return dat; +} + +void LCD_reset(){ + CS_set; RS_set; WR_set; RD_set; + LCD_write(); + LCD_wrbyte(0xff); + RST_clear; + Delay(300); + RST_set; + Delay(100); + write_reg(0,1); + Delay(100); +/* CS_clear; RS_clear; + int i; + for(i = 0; i < 4; ++i) writebyte(0); + RS_set; CS_set; +*/ +} + +/** + * read LCD identification + */ +uint16_t LCD_read_id(){ + write_reg(0,0); + LCD_id = read_reg(0); + write_reg(0,1); + /*if(read8_32(0x04) == 0x8000){ + write8_24(HX8357D_SETC, 0xFF8357); + Delay(10); + if(read8_32(0xD0) == 0x990000){ + LCD_id = 0x8357; + return 0x8357; + } + } + if(read8_32(0xD3) == 0x9341){ + LCD_id = 0x9341; + return 0x9341; + }*/ + return LCD_id; +} + +#define TFTLCD_DELAY 0xfff + +static const uint16_t ILI932x_regValues[] = { + ILI932X_START_OSC , 0x0001, // 0x00 + TFTLCD_DELAY , 100, + ILI932X_DISP_CTRL1 , 0x0121, // 0x07 + ILI932X_DRIV_OUT_CTRL , 0x0100, // 0x01 + ILI932X_DRIV_WAV_CTRL , 0x0700, // 0x02 + ILI932X_ENTRY_MOD , 0x0030, // 0x03 + ILI932X_RESIZE_CTRL , 0x0000, // 0x04 + ILI932X_DISP_CTRL2 , 0x0202, // 0x08 + ILI932X_DISP_CTRL3 , 0x0000, // 0x09 + ILI932X_DISP_CTRL4 , 0x0000, // 0x0A + ILI932X_RGB_DISP_IF_CTRL1, 0x0001, // 0x0C + ILI932X_FRM_MARKER_POS , 0x0000, // 0x0D + ILI932X_RGB_DISP_IF_CTRL2, 0x0000, // 0x0F +/* + ILI932X_POW_CTRL1 , 0x0000, // 0x10 + ILI932X_POW_CTRL2 , 0x0007, // 0x11 + ILI932X_POW_CTRL3 , 0x0000, // 0x12 + ILI932X_POW_CTRL4 , 0x0000, // 0x13 + TFTLCD_DELAY , 200, + ILI932X_POW_CTRL1 , 0x1690, // 0x10 + ILI932X_POW_CTRL2 , 0x0227, // 0x11 + TFTLCD_DELAY , 50, + //ILI932X_POW_CTRL3 , 0x001A, // 0x12 + ILI932X_POW_CTRL3 , 0x001D, // 0x12 + TFTLCD_DELAY , 50, + //ILI932X_POW_CTRL4 , 0x1800, // 0x13 + ILI932X_POW_CTRL4 , 0x0800, // 0x13 + //ILI932X_POW_CTRL7 , 0x002A, // 0x29 + ILI932X_POW_CTRL7 , 0x0012, // 0x29 + */ + ILI932X_POW_CTRL1 , 0x16b0, // 0x10 + ILI932X_POW_CTRL2 , 0x0007, // 0x11 + ILI932X_POW_CTRL3 , 0x0138, // 0x12 + ILI932X_POW_CTRL4 , 0x0b00, // 0x13 + ILI932X_POW_CTRL7 , 0x0000, // 0x29 + TFTLCD_DELAY , 200, + ILI932X_FRM_RATE_COL_CTRL, 0x0000, // 0x2B (100Hz) + TFTLCD_DELAY , 50, + ILI932X_GAMMA_CTRL1 , 0x0000, // 0x30 + ILI932X_GAMMA_CTRL2 , 0x0000, // 0x31 + ILI932X_GAMMA_CTRL3 , 0x0000, // 0x32 + ILI932X_GAMMA_CTRL4 , 0x0206, // 0x35 + ILI932X_GAMMA_CTRL5 , 0x0808, // 0x36 + ILI932X_GAMMA_CTRL6 , 0x0007, // 0x37 + ILI932X_GAMMA_CTRL7 , 0x0201, // 0x38 + ILI932X_GAMMA_CTRL8 , 0x0000, // 0x39 + ILI932X_GAMMA_CTRL9 , 0x0000, // 0x3C + ILI932X_GAMMA_CTRL10 , 0x0000, // 0x3D + ILI932X_GRAM_HOR_AD , 0x0000, // 0x20 + ILI932X_GRAM_VER_AD , 0x0000, // 0x21 + ILI932X_HOR_START_AD , 0x0000, // 0x50 + ILI932X_HOR_END_AD , TFTWIDTH-1, // 0x51 + ILI932X_VER_START_AD , 0x0000, // 0x52 + ILI932X_VER_END_AD , TFTHEIGHT-1, // 0x53 + //ILI932X_GATE_SCAN_CTRL1 , 0xA700, // 0x60 + ILI932X_GATE_SCAN_CTRL1 , 0x2700, // 0x60 + //ILI932X_GATE_SCAN_CTRL2 , 0x0003, // 0x61 + ILI932X_GATE_SCAN_CTRL2 , 0x0001, // 0x61 + ILI932X_GATE_SCAN_CTRL3 , 0x0000, // 0x6A + ILI932X_PANEL_IF_CTRL1 , 0x0010, // 0x90 + ILI932X_PANEL_IF_CTRL2 , 0x0000, // 0x92 + ILI932X_PANEL_IF_CTRL3 , 0x0003, // 0x93 + ILI932X_PANEL_IF_CTRL4 , 0x0110, // 0x95 + ILI932X_PANEL_IF_CTRL5 , 0x0000, // 0x97 + ILI932X_PANEL_IF_CTRL6 , 0x0000, // 0x98 + TFTLCD_DELAY , 50, + //ILI932X_DISP_CTRL1 , 0x013b, // 0x07 - 8bit color + ILI932X_DISP_CTRL1 , 0x0133, // 0x07 +}; +/* +static const uint16_t ILI932x_regValues[] = { + ILI932X_START_OSC , 0x0001, // 0x00 + TFTLCD_DELAY , 100, + ILI932X_DRIV_OUT_CTRL , 0x0000, // 0x01 + ILI932X_DRIV_WAV_CTRL , 0x0700, // 0x02 + ILI932X_ENTRY_MOD , 0x1030, // 0x03 + ILI932X_RESIZE_CTRL , 0x0000, // 0x04 + ILI932X_DISP_CTRL2 , 0x0202, // 0x08 + ILI932X_DISP_CTRL3 , 0x0000, // 0x09 + ILI932X_DISP_CTRL4 , 0x0000, // 0x0A + ILI932X_RGB_DISP_IF_CTRL1, 0x0003, // 0x0C + ILI932X_FRM_MARKER_POS , 0x0000, // 0x0D + ILI932X_RGB_DISP_IF_CTRL2, 0x0000, // 0x0F + ILI932X_DISP_CTRL1 , 0x0021, // 0x07 + TFTLCD_DELAY , 10, + ILI932X_POW_CTRL1 , 0x0000, // 0x10 + ILI932X_POW_CTRL2 , 0x0007, // 0x11 + ILI932X_POW_CTRL3 , 0x0000, // 0x12 + ILI932X_POW_CTRL4 , 0x0000, // 0x13 + TFTLCD_DELAY , 100, + ILI932X_POW_CTRL1 , 0x1690, // 0x10 + ILI932X_POW_CTRL2 , 0x0007, // 0x11 + TFTLCD_DELAY , 100, + ILI932X_POW_CTRL3 , 0x0118, // 0x12 + TFTLCD_DELAY , 100, + ILI932X_POW_CTRL4 , 0x0b00, // 0x13 + TFTLCD_DELAY , 100, + ILI932X_POW_CTRL7 , 0x0012, // 0x29 + ILI932X_FRM_RATE_COL_CTRL, 0x000B, // 0x2B + ILI932X_GRAM_HOR_AD , 0x0000, // 0x20 + ILI932X_GRAM_VER_AD , 0x0000, // 0x21 + ILI932X_HOR_START_AD , 0x0000, // 0x50 + ILI932X_HOR_END_AD , TFTWIDTH-1, // 0x51 + ILI932X_VER_START_AD , 0x0000, // 0x52 + ILI932X_VER_END_AD , TFTHEIGHT-1, // 0x53 + ILI932X_GATE_SCAN_CTRL1 , 0x2700, // 0x60 + ILI932X_GATE_SCAN_CTRL2 , 0x0001, // 0x61 + ILI932X_GATE_SCAN_CTRL3 , 0x0000, // 0x6A + ILI932X_PANEL_IF_CTRL1 , 0x0010, // 0x90 + ILI932X_PANEL_IF_CTRL2 , 0x0000, // 0x92 + ILI932X_PANEL_IF_CTRL3 , 0x0001, // 0x93 + ILI932X_PANEL_IF_CTRL4 , 0x0110, // 0x95 + ILI932X_PANEL_IF_CTRL5 , 0x0000, // 0x97 + ILI932X_PANEL_IF_CTRL6 , 0x0000, // 0x98 + ILI932X_DISP_CTRL1 , 0x0133, // 0x07 +};*/ +/* +static const uint16_t ILI932x_regValues[] = { + ILI932X_START_OSC , 0x0001, // 0x00 + TFTLCD_DELAY , 100, + ILI932X_DRIV_OUT_CTRL , 0x0000, // 0x01 + ILI932X_DRIV_WAV_CTRL , 0x0700, // 0x02 + ILI932X_ENTRY_MOD , 0x1030, // 0x03 + ILI932X_RESIZE_CTRL , 0x0000, // 0x04 + ILI932X_DISP_CTRL2 , 0x0202, // 0x08 + ILI932X_DISP_CTRL3 , 0x0000, // 0x09 + ILI932X_DISP_CTRL4 , 0x0000, // 0x0A + ILI932X_RGB_DISP_IF_CTRL1, 0x0003, // 0x0C + ILI932X_FRM_MARKER_POS , 0x0000, // 0x0D + ILI932X_RGB_DISP_IF_CTRL2, 0x0000, // 0x0F + ILI932X_DISP_CTRL1 , 0x0011, // 0x07 + TFTLCD_DELAY , 10, + ILI932X_POW_CTRL1 , 0x0000, // 0x10 + ILI932X_POW_CTRL2 , 0x0007, // 0x11 + ILI932X_POW_CTRL3 , 0x0000, // 0x12 + ILI932X_POW_CTRL4 , 0x0000, // 0x13 + TFTLCD_DELAY , 100, + ILI932X_POW_CTRL1 , 0x1690, // 0x10 + ILI932X_POW_CTRL2 , 0x0007, // 0x11 + TFTLCD_DELAY , 100, + ILI932X_POW_CTRL3 , 0x0118, // 0x12 + TFTLCD_DELAY , 100, + ILI932X_POW_CTRL4 , 0x0b00, // 0x13 + TFTLCD_DELAY , 100, + ILI932X_POW_CTRL7 , 0x0012, // 0x29 + ILI932X_FRM_RATE_COL_CTRL, 0x000B, // 0x2B + ILI932X_GRAM_HOR_AD , 0x0000, // 0x20 + ILI932X_GRAM_VER_AD , 0x0000, // 0x21 + ILI932X_HOR_START_AD , 0x0000, // 0x50 + ILI932X_HOR_END_AD , TFTWIDTH-1, // 0x51 + ILI932X_VER_START_AD , 0x0000, // 0x52 + ILI932X_VER_END_AD , TFTHEIGHT-1, // 0x53 + ILI932X_GATE_SCAN_CTRL1 , 0x2700, // 0x60 + ILI932X_GATE_SCAN_CTRL2 , 0x0001, // 0x61 + ILI932X_GATE_SCAN_CTRL3 , 0x0000, // 0x6A + ILI932X_PANEL_IF_CTRL1 , 0x0010, // 0x90 + ILI932X_PANEL_IF_CTRL2 , 0x0000, // 0x92 + ILI932X_PANEL_IF_CTRL3 , 0x0001, // 0x93 + ILI932X_PANEL_IF_CTRL4 , 0x0110, // 0x95 + ILI932X_PANEL_IF_CTRL5 , 0x0000, // 0x97 + ILI932X_PANEL_IF_CTRL6 , 0x0000, // 0x98 + ILI932X_DISP_CTRL1 , 0x0133, // 0x07 +}; +*/ +/** + * try to init display + * return 0 if failed + */ +uint16_t LCD_init(){ + //if(LCD_id == 0) + LCD_read_id(); + if(LCD_id > 0x931f && LCD_id < 0x932a){ // 932x + // LCD_id = 0x9320; // make it simple! + int i, s = sizeof(ILI932x_regValues)/sizeof(uint16_t); + for(i = 0; i < s;){ + uint16_t a = ILI932x_regValues[i++]; + uint16_t b = ILI932x_regValues[i++]; + if(a == TFTLCD_DELAY) Delay(b); + else write_reg(a, b); + } + uint16_t addr; + for(addr = 0x80; addr < 0x86; ++addr) + write_reg(addr, 0); + Delay(300); + return LCD_id; + } + //LCD_reset(); + return LCD_id; +} + +/** + * put point to current position incrementing coordinates + */ +void putpoint(uint16_t colr){ + int i; + if(LCD_id == 0) return; + LCD_write(); // dir: out + CS_clear; // active + writereg(ILI932X_RW_GRAM); + for(i = 0; i < 500; ++i){ + writebyte(colr >> 8); + writebyte(colr && 0xff); + } + CS_set; + //if(LCD_id == 0x9320){ + //} +} + +void setpix(uint16_t x, uint16_t y, uint16_t colr){ + write_reg(ILI932X_GRAM_HOR_AD, x); + write_reg(ILI932X_GRAM_VER_AD, y); + write_reg(ILI932X_RW_GRAM, colr); +} diff --git a/F1/2.8TFT/lcd.h b/F1/2.8TFT/lcd.h new file mode 100644 index 0000000..7d5b4e4 --- /dev/null +++ b/F1/2.8TFT/lcd.h @@ -0,0 +1,68 @@ +/* + * lcd.h + * + * Copyright 2016 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#pragma once +#ifndef __LCD_H__ +#define __LCD_H__ + +#define TFTWIDTH 240 +#define TFTHEIGHT 320 + +#define DWT_CYCCNT *(volatile uint32_t *)0xE0001004 +#define DWT_CONTROL *(volatile uint32_t *)0xE0001000 +#define SCB_DEMCR *(volatile uint32_t *)0xE000EDFC +// pause for 150ns + +#define pause() do{SCB_DEMCR |= 0x01000000; DWT_CYCCNT = 0; DWT_CONTROL|= 1; \ + while(DWT_CYCCNT < 3);}while(0) + +//#define pause() do{}while(0) + +uint16_t read_reg(uint16_t reg); +void write_reg(uint16_t reg, uint16_t dat); + +/* +uint32_t read_reg_var(uint8_t reg, uint8_t len); +uint32_t read16_reg_var(uint16_t reg, uint8_t len); + +#define write8_32(r,d) do{write_reg_var(r,d,4);}while(0) +#define write8_24(r,d) do{write_reg_var(r,d,3);}while(0) +#define write8_16(r,d) do{write_reg_var(r,d,2);}while(0) +#define write16_32(r,d) do{write_reg16_var(r,d,4);}while(0) +#define write16_24(r,d) do{write_reg16_var(r,d,3);}while(0) +//#define write16_16(r,d) do{write_reg16_var(r,d,2);}while(0) +void write16_16(uint16_t reg, uint16_t dat); +#define read8_32(x) (read_reg_var(x, 4)) +#define read8_16(x) ((uint16_t)(read_reg_var(x, 2))) +#define read16_32(x) (read16_reg_var(x, 4)) +#define read16_16(x) ((uint16_t)(read16_reg_var(x, 2))) +*/ + +uint16_t LCD_status_read(); +uint16_t LCD_read_id(); +void LCD_reset(); +uint16_t LCD_init(); +void putpoint(uint16_t colr); +void setpix(uint16_t x, uint16_t y, uint16_t colr); + + + +#endif // __LCD_H__ diff --git a/F1/2.8TFT/ld/devices.data b/F1/2.8TFT/ld/devices.data new file mode 100644 index 0000000..7f29538 --- /dev/null +++ b/F1/2.8TFT/ld/devices.data @@ -0,0 +1,9 @@ +stm32f103?4* stm32f1 ROM=16K RAM=6K +stm32f103?6* stm32f1 ROM=32K RAM=10K +stm32f103?8* stm32f1 ROM=64K RAM=20K +stm32f103?b* stm32f1 ROM=128K RAM=20K +stm32f103?c* stm32f1 ROM=256K RAM=48K +stm32f103?d* stm32f1 ROM=384K RAM=64K +stm32f103?e* stm32f1 ROM=512K RAM=64K +stm32f103?f* stm32f1 ROM=768K RAM=96K +stm32f103?g* stm32f1 ROM=1024K RAM=96K diff --git a/F1/2.8TFT/ld/stm32f103x4.ld b/F1/2.8TFT/ld/stm32f103x4.ld new file mode 100644 index 0000000..efed65e --- /dev/null +++ b/F1/2.8TFT/ld/stm32f103x4.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for STM32F100x4, 16K flash, 4K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 16K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32f1.ld + diff --git a/F1/2.8TFT/ld/stm32f103x6.ld b/F1/2.8TFT/ld/stm32f103x6.ld new file mode 100644 index 0000000..13f05f9 --- /dev/null +++ b/F1/2.8TFT/ld/stm32f103x6.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for STM32F100x4, 16K flash, 4K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 10K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32f1.ld + diff --git a/F1/2.8TFT/ld/stm32f103x8.ld b/F1/2.8TFT/ld/stm32f103x8.ld new file mode 100644 index 0000000..2c4640f --- /dev/null +++ b/F1/2.8TFT/ld/stm32f103x8.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for STM32F100x4, 16K flash, 4K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32f1.ld + diff --git a/F1/2.8TFT/ld/stm32f103xB.ld b/F1/2.8TFT/ld/stm32f103xB.ld new file mode 100644 index 0000000..138444d --- /dev/null +++ b/F1/2.8TFT/ld/stm32f103xB.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for STM32F100x4, 16K flash, 4K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32f1.ld + diff --git a/F1/2.8TFT/ld/stm32f103xC.ld b/F1/2.8TFT/ld/stm32f103xC.ld new file mode 100644 index 0000000..fda76bf --- /dev/null +++ b/F1/2.8TFT/ld/stm32f103xC.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for STM32F100x4, 16K flash, 4K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32f1.ld + diff --git a/F1/2.8TFT/ld/stm32f103xD.ld b/F1/2.8TFT/ld/stm32f103xD.ld new file mode 100644 index 0000000..0f996c2 --- /dev/null +++ b/F1/2.8TFT/ld/stm32f103xD.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for STM32F100x4, 16K flash, 4K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 384K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32f1.ld + diff --git a/F1/2.8TFT/ld/stm32f103xE.ld b/F1/2.8TFT/ld/stm32f103xE.ld new file mode 100644 index 0000000..b0fcb69 --- /dev/null +++ b/F1/2.8TFT/ld/stm32f103xE.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for STM32F100x4, 16K flash, 4K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32f1.ld + diff --git a/F1/2.8TFT/ld/stm32f103xF.ld b/F1/2.8TFT/ld/stm32f103xF.ld new file mode 100644 index 0000000..62d47db --- /dev/null +++ b/F1/2.8TFT/ld/stm32f103xF.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for STM32F100x4, 16K flash, 4K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 768K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32f1.ld + diff --git a/F1/2.8TFT/ld/stm32f103xG.ld b/F1/2.8TFT/ld/stm32f103xG.ld new file mode 100644 index 0000000..0c0c968 --- /dev/null +++ b/F1/2.8TFT/ld/stm32f103xG.ld @@ -0,0 +1,31 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* Linker script for STM32F100x4, 16K flash, 4K RAM. */ + +/* Define memory regions. */ +MEMORY +{ + rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +/* Include the common ld script. */ +INCLUDE libopencm3_stm32f1.ld + diff --git a/F1/2.8TFT/main.c b/F1/2.8TFT/main.c new file mode 100644 index 0000000..090ca0a --- /dev/null +++ b/F1/2.8TFT/main.c @@ -0,0 +1,128 @@ +/* + * main.c + * + * Copyright 2014 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include "main.h" +#include "hardware_ini.h" +#include "cdcacm.h" +#include "dmagpio.h" +#include "lcd.h" +#include "registers.h" + +volatile uint32_t Timer = 0; // global timer (milliseconds) +usbd_device *usbd_dev; + +int main(){ + uint32_t Old_timer = 0; + + // RCC clocking: 8MHz oscillator -> 72MHz system + rcc_clock_setup_in_hse_8mhz_out_72mhz(); + // SysTick is a system timer with 1ms period + SysTick_init(); + // disable JTAG to use PA13/PA14 + gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF, 0); + GPIO_init(); + + usb_disconnect(); // turn off USB while initializing all + + // USB + usbd_dev = USB_init(); + + dmagpio_init(); + + usb_connect(); // turn on USB + + LCD_reset(); + + int oldusblen = 0, x = 0, y = 0; + int id = LCD_init(); + if(!id) P("failed to init LCD\n"); + uint16_t colr = 0; + while(1){ + usbd_poll(usbd_dev); + if(usbdatalen != oldusblen){ // there's something in USB buffer + parse_incoming_buf(usbdatabuf, &usbdatalen); + oldusblen = usbdatalen; + id = 0; + } + if(transfer_complete){ + P("transfered\n"); + transfer_complete = 0; + } + setpix(x++, y++, colr); + if(x > 200) x = 0; + if(y > 200) y = 0; + if(Timer - Old_timer > 999){ // one-second cycle + Old_timer += 1000; + P("Display id: "); + print_hex((uint8_t*)&id, 2); + newline(); + //write_reg(ILI932X_DISP_CTRL1, 0x0133); + if(id){ + uint16_t r = read_reg(ILI932X_RW_GRAM); + print_hex((uint8_t*)&r, 2); + /*P(", status: "); + r = LCD_status_read(); + print_hex((uint8_t*)&r, 2);*/ + newline(); + uint16_t i; + for(i = 0; i < 0x29; ++i){ + r = read_reg(i); + print_hex((uint8_t*)&i, 2); P(" = "); + print_hex((uint8_t*)&r, 2); usb_send(' '); + r = read_reg(i); print_hex((uint8_t*)&r, 2); + newline(); + } + putpoint(colr); + colr += 32; + }else{ + LCD_reset(); + id = LCD_init(); + if(!id) P("failed to init LCD\n"); + } + }else if(Timer < Old_timer){ // Timer overflow + Old_timer = 0; + } + } +} + + +/** + * SysTick interrupt: increment global time & send data buffer through USB + */ +void sys_tick_handler(){ + Timer++; + usbd_poll(usbd_dev); + usb_send_buffer(); +} + +// pause function, delay in ms +void Delay(uint16_t _U_ time){ + uint32_t waitto = Timer + time; + while(Timer < waitto); +} + +/** + * print current time in milliseconds: 4 bytes for ovrvlow + 4 bytes for time + * with ' ' as delimeter + */ +void print_time(){ + print_int(Timer); +} diff --git a/F1/2.8TFT/main.h b/F1/2.8TFT/main.h new file mode 100644 index 0000000..3a781a0 --- /dev/null +++ b/F1/2.8TFT/main.h @@ -0,0 +1,53 @@ +/* + * main.h + * + * Copyright 2014 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + + +#pragma once +#ifndef __MAIN_H__ +#define __MAIN_H__ + +#include +#include // memcpy +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sync.h" // mutexes +#include "user_proto.h" + +#define _U_ __attribute__((__unused__)) +#define U8(x) ((uint8_t) x) +#define U16(x) ((uint16_t) x) +#define U32(x) ((uint32_t) x) + +extern volatile uint32_t Timer; // global timer (milliseconds) +void Delay(uint16_t time); + +#endif // __MAIN_H__ + diff --git a/F1/2.8TFT/registers.h b/F1/2.8TFT/registers.h new file mode 100644 index 0000000..810805d --- /dev/null +++ b/F1/2.8TFT/registers.h @@ -0,0 +1,172 @@ +// Register names from Peter Barrett's Microtouch code +#define ILI932X_START_OSC 0x00 +#define ILI932X_DRIV_OUT_CTRL 0x01 +#define ILI932X_DRIV_WAV_CTRL 0x02 +#define ILI932X_ENTRY_MOD 0x03 +#define ILI932X_RESIZE_CTRL 0x04 +#define ILI932X_DISP_CTRL1 0x07 +#define ILI932X_DISP_CTRL2 0x08 +#define ILI932X_DISP_CTRL3 0x09 +#define ILI932X_DISP_CTRL4 0x0A +#define ILI932X_RGB_DISP_IF_CTRL1 0x0C +#define ILI932X_FRM_MARKER_POS 0x0D +#define ILI932X_RGB_DISP_IF_CTRL2 0x0F +#define ILI932X_POW_CTRL1 0x10 +#define ILI932X_POW_CTRL2 0x11 +#define ILI932X_POW_CTRL3 0x12 +#define ILI932X_POW_CTRL4 0x13 +#define ILI932X_GRAM_HOR_AD 0x20 +#define ILI932X_GRAM_VER_AD 0x21 +#define ILI932X_RW_GRAM 0x22 +#define ILI932X_POW_CTRL7 0x29 +#define ILI932X_FRM_RATE_COL_CTRL 0x2B +#define ILI932X_GAMMA_CTRL1 0x30 +#define ILI932X_GAMMA_CTRL2 0x31 +#define ILI932X_GAMMA_CTRL3 0x32 +#define ILI932X_GAMMA_CTRL4 0x35 +#define ILI932X_GAMMA_CTRL5 0x36 +#define ILI932X_GAMMA_CTRL6 0x37 +#define ILI932X_GAMMA_CTRL7 0x38 +#define ILI932X_GAMMA_CTRL8 0x39 +#define ILI932X_GAMMA_CTRL9 0x3C +#define ILI932X_GAMMA_CTRL10 0x3D +#define ILI932X_HOR_START_AD 0x50 +#define ILI932X_HOR_END_AD 0x51 +#define ILI932X_VER_START_AD 0x52 +#define ILI932X_VER_END_AD 0x53 +#define ILI932X_GATE_SCAN_CTRL1 0x60 +#define ILI932X_GATE_SCAN_CTRL2 0x61 +#define ILI932X_GATE_SCAN_CTRL3 0x6A +#define ILI932X_PART_IMG1_DISP_POS 0x80 +#define ILI932X_PART_IMG1_START_AD 0x81 +#define ILI932X_PART_IMG1_END_AD 0x82 +#define ILI932X_PART_IMG2_DISP_POS 0x83 +#define ILI932X_PART_IMG2_START_AD 0x84 +#define ILI932X_PART_IMG2_END_AD 0x85 +#define ILI932X_PANEL_IF_CTRL1 0x90 +#define ILI932X_PANEL_IF_CTRL2 0x92 +#define ILI932X_PANEL_IF_CTRL3 0x93 +#define ILI932X_PANEL_IF_CTRL4 0x95 +#define ILI932X_PANEL_IF_CTRL5 0x97 +#define ILI932X_PANEL_IF_CTRL6 0x98 + +#define HX8347G_COLADDRSTART_HI 0x02 +#define HX8347G_COLADDRSTART_LO 0x03 +#define HX8347G_COLADDREND_HI 0x04 +#define HX8347G_COLADDREND_LO 0x05 +#define HX8347G_ROWADDRSTART_HI 0x06 +#define HX8347G_ROWADDRSTART_LO 0x07 +#define HX8347G_ROWADDREND_HI 0x08 +#define HX8347G_ROWADDREND_LO 0x09 +#define HX8347G_MEMACCESS 0x16 + + + +#define ILI9341_SOFTRESET 0x01 +#define ILI9341_SLEEPIN 0x10 +#define ILI9341_SLEEPOUT 0x11 +#define ILI9341_NORMALDISP 0x13 +#define ILI9341_INVERTOFF 0x20 +#define ILI9341_INVERTON 0x21 +#define ILI9341_GAMMASET 0x26 +#define ILI9341_DISPLAYOFF 0x28 +#define ILI9341_DISPLAYON 0x29 +#define ILI9341_COLADDRSET 0x2A +#define ILI9341_PAGEADDRSET 0x2B +#define ILI9341_MEMORYWRITE 0x2C +#define ILI9341_PIXELFORMAT 0x3A +#define ILI9341_FRAMECONTROL 0xB1 +#define ILI9341_DISPLAYFUNC 0xB6 +#define ILI9341_ENTRYMODE 0xB7 +#define ILI9341_POWERCONTROL1 0xC0 +#define ILI9341_POWERCONTROL2 0xC1 +#define ILI9341_VCOMCONTROL1 0xC5 +#define ILI9341_VCOMCONTROL2 0xC7 +#define ILI9341_MEMCONTROL 0x36 +#define ILI9341_MADCTL 0x36 + +#define ILI9341_MADCTL_MY 0x80 +#define ILI9341_MADCTL_MX 0x40 +#define ILI9341_MADCTL_MV 0x20 +#define ILI9341_MADCTL_ML 0x10 +#define ILI9341_MADCTL_RGB 0x00 +#define ILI9341_MADCTL_BGR 0x08 +#define ILI9341_MADCTL_MH 0x04 + + + +#define HX8357_NOP 0x00 +#define HX8357_SWRESET 0x01 +#define HX8357_RDDID 0x04 +#define HX8357_RDDST 0x09 + +#define HX8357B_RDPOWMODE 0x0A +#define HX8357B_RDMADCTL 0x0B +#define HX8357B_RDCOLMOD 0x0C +#define HX8357B_RDDIM 0x0D +#define HX8357B_RDDSDR 0x0F + +#define HX8357_SLPIN 0x10 +#define HX8357_SLPOUT 0x11 +#define HX8357B_PTLON 0x12 +#define HX8357B_NORON 0x13 + +#define HX8357_INVOFF 0x20 +#define HX8357_INVON 0x21 +#define HX8357_DISPOFF 0x28 +#define HX8357_DISPON 0x29 + +#define HX8357_CASET 0x2A +#define HX8357_PASET 0x2B +#define HX8357_RAMWR 0x2C +#define HX8357_RAMRD 0x2E + +#define HX8357B_PTLAR 0x30 +#define HX8357_TEON 0x35 +#define HX8357_TEARLINE 0x44 +#define HX8357_MADCTL 0x36 +#define HX8357_COLMOD 0x3A + +#define HX8357_SETOSC 0xB0 +#define HX8357_SETPWR1 0xB1 +#define HX8357B_SETDISPLAY 0xB2 +#define HX8357_SETRGB 0xB3 +#define HX8357D_SETCOM 0xB6 + +#define HX8357B_SETDISPMODE 0xB4 +#define HX8357D_SETCYC 0xB4 +#define HX8357B_SETOTP 0xB7 +#define HX8357D_SETC 0xB9 + +#define HX8357B_SET_PANEL_DRIVING 0xC0 +#define HX8357D_SETSTBA 0xC0 +#define HX8357B_SETDGC 0xC1 +#define HX8357B_SETID 0xC3 +#define HX8357B_SETDDB 0xC4 +#define HX8357B_SETDISPLAYFRAME 0xC5 +#define HX8357B_GAMMASET 0xC8 +#define HX8357B_SETCABC 0xC9 +#define HX8357_SETPANEL 0xCC + + +#define HX8357B_SETPOWER 0xD0 +#define HX8357B_SETVCOM 0xD1 +#define HX8357B_SETPWRNORMAL 0xD2 + +#define HX8357B_RDID1 0xDA +#define HX8357B_RDID2 0xDB +#define HX8357B_RDID3 0xDC +#define HX8357B_RDID4 0xDD + +#define HX8357D_SETGAMMA 0xE0 + +#define HX8357B_SETGAMMA 0xC8 +#define HX8357B_SETPANELRELATED 0xE9 + +#define HX8357B_MADCTL_MY 0x80 +#define HX8357B_MADCTL_MX 0x40 +#define HX8357B_MADCTL_MV 0x20 +#define HX8357B_MADCTL_ML 0x10 +#define HX8357B_MADCTL_RGB 0x00 +#define HX8357B_MADCTL_BGR 0x08 +#define HX8357B_MADCTL_MH 0x04 diff --git a/F1/2.8TFT/sync.c b/F1/2.8TFT/sync.c new file mode 100644 index 0000000..ba688c3 --- /dev/null +++ b/F1/2.8TFT/sync.c @@ -0,0 +1,93 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * TODO: + * implement mutexes for other type of MCU (which doesn't have strex & ldrex) + */ + +#include + +/* DMB is supported on CM0 */ +void __dmb() +{ + __asm__ volatile ("dmb"); +} + +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +uint32_t __ldrex(volatile uint32_t *addr) +{ + uint32_t res; + __asm__ volatile ("ldrex %0, [%1]" : "=r" (res) : "r" (addr)); + return res; +} + +uint32_t __strex(uint32_t val, volatile uint32_t *addr) +{ + uint32_t res; + __asm__ volatile ("strex %0, %2, [%1]" + : "=&r" (res) : "r" (addr), "r" (val)); + return res; +} + +void mutex_lock(mutex_t *m) +{ + uint32_t status = 0; + + do { + /* Wait until the mutex is unlocked. */ + while (__ldrex(m) != MUTEX_UNLOCKED); + + /* Try to acquire it. */ + status = __strex(MUTEX_LOCKED, m); + + /* Did we get it? If not then try again. */ + } while (status != 0); + + /* Execute the mysterious Data Memory Barrier instruction! */ + __dmb(); +} + +void mutex_unlock(mutex_t *m) +{ + /* Ensure accesses to protected resource are finished */ + __dmb(); + + /* Free the lock. */ + *m = MUTEX_UNLOCKED; +} + +/* + * Try to lock mutex + * if it's already locked or there was error in STREX, return MUTEX_LOCKED + * else return MUTEX_UNLOCKED + */ +mutex_t mutex_trylock(mutex_t *m){ + uint32_t status = 0; + mutex_t old_lock = __ldrex(m); // get mutex value + // set mutex + status = __strex(MUTEX_LOCKED, m); + if(status == 0) __dmb(); + else old_lock = MUTEX_LOCKED; + return old_lock; +} + +#endif diff --git a/F1/2.8TFT/sync.h b/F1/2.8TFT/sync.h new file mode 100644 index 0000000..bfe837b --- /dev/null +++ b/F1/2.8TFT/sync.h @@ -0,0 +1,53 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CM3_SYNC_H +#define LIBOPENCM3_CM3_SYNC_H + +void __dmb(void); + +/* Implements synchronisation primitives as discussed in the ARM document + * DHT0008A (ID081709) "ARM Synchronization Primitives" and the ARM v7-M + * Architecture Reference Manual. +*/ + +/* --- Exclusive load and store instructions ------------------------------- */ + +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +uint32_t __ldrex(volatile uint32_t *addr); +uint32_t __strex(uint32_t val, volatile uint32_t *addr); + +/* --- Convenience functions ----------------------------------------------- */ + +/* Here we implement some simple synchronisation primitives. */ + +typedef uint32_t mutex_t; + +#define MUTEX_UNLOCKED 0 +#define MUTEX_LOCKED 1 + +void mutex_lock(mutex_t *m); +void mutex_unlock(mutex_t *m); +mutex_t mutex_trylock(mutex_t *m); + +#endif + +#endif diff --git a/F1/2.8TFT/user_proto.c b/F1/2.8TFT/user_proto.c new file mode 100644 index 0000000..0034c54 --- /dev/null +++ b/F1/2.8TFT/user_proto.c @@ -0,0 +1,93 @@ +/* + * user_proto.c + * + * Copyright 2014 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include "cdcacm.h" +#include "main.h" +#include "hardware_ini.h" +#include "dmagpio.h" + +/** + * parce command buffer buf with length len + * return 0 if buffer processed or len if there's not enough data in buffer + */ +void parse_incoming_buf(uint8_t *buf, int *len){ + static int lastidx = 0; + int l = *len; + for(; lastidx < l; ++lastidx){ + uint8_t cmd = buf[lastidx]; + usb_send(cmd); + if(cmd == '\n'){ + dmagpio_transfer(buf, *len); + *len = 0; + lastidx = 0; + return; + } + } +} + +/** + * Send char array wrd thru USB + */ +void prnt(uint8_t *wrd){ + if(!wrd) return; + while(*wrd) usb_send(*wrd++); +} + +/** + * Print buff as hex values + * @param buf - buffer to print + * @param l - buf length + * @param s - function to send a byte + */ +void print_hex(uint8_t *buff, uint8_t l){ + void putc(uint8_t c){ + if(c < 10) + usb_send(c + '0'); + else + usb_send(c + 'a' - 10); + } + usb_send('0'); usb_send('x'); // prefix 0x + while(l--){ + putc(buff[l] >> 4); + putc(buff[l] & 0x0f); + } +} + +/** + * Print decimal integer value + * @param N - value to print + * @param s - function to send a byte + */ +void print_int(int32_t N){ + uint8_t buf[10], L = 0; + if(N < 0){ + usb_send('-'); + N = -N; + } + if(N){ + while(N){ + buf[L++] = N % 10 + '0'; + N /= 10; + } + while(L--) usb_send(buf[L]); + }else usb_send('0'); +} + diff --git a/F1/2.8TFT/user_proto.h b/F1/2.8TFT/user_proto.h new file mode 100644 index 0000000..3835098 --- /dev/null +++ b/F1/2.8TFT/user_proto.h @@ -0,0 +1,47 @@ +/* + * user_proto.h + * + * Copyright 2014 Edward V. Emelianov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#pragma once +#ifndef __USER_PROTO_H__ +#define __USER_PROTO_H__ + +#include "cdcacm.h" + +// shorthand for prnt +#define P(arg) do{prnt((uint8_t*)arg);}while(0) +// debug message - over USB +#ifdef EBUG + #define DBG(a) do{prnt((uint8_t*)a);}while(0) +#else + #define DBG(a) +#endif + +typedef uint8_t (*intfun)(int32_t); + +void prnt(uint8_t *wrd); +#define newline() usb_send('\n') + +void print_int(int32_t N); +void print_hex(uint8_t *buff, uint8_t l); + +void parse_incoming_buf(uint8_t *buf, int *len); + +#endif // __USER_PROTO_H__