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Edward Emelianov
2021-08-17 00:01:41 +03:00
parent a4c7123a63
commit 50fdc3e104
14 changed files with 49461 additions and 2125 deletions
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F0-nolib/3steppersLB/kicad/gerbers/stm32-drl.rpt Normal file
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Drill report for /home/eddy/Yandex.Disk/Projects/stm32samples/F0-nolib/3steppersLB/kicad/stm32.kicad_pcb
Created on Пн 09 авг 2021 17:28:16
Copper Layer Stackup:
=============================================================
L1 : F.Cu front
L2 : B.Cu back
Drill file 'stm32.drl' contains
plated through holes:
=============================================================
T1 0.400mm 0.0157" (68 holes)
T2 0.600mm 0.0236" (29 holes)
T3 0.750mm 0.0295" (50 holes)
T4 0.800mm 0.0315" (12 holes)
T5 0.920mm 0.0362" (4 holes)
T6 1.000mm 0.0394" (8 holes)
T7 1.100mm 0.0433" (5 holes)
T8 1.300mm 0.0512" (15 holes)
T9 2.330mm 0.0917" (2 holes)
T10 3.000mm 0.1181" (4 holes)
Total plated holes count 197
Not plated through holes are merged with plated holes
unplated through holes:
=============================================================
Total unplated holes count 0