mirror of
https://github.com/eddyem/stm32samples.git
synced 2025-12-06 10:45:11 +03:00
almost fix SPI in F0 testboard
This commit is contained in:
parent
83b3e56587
commit
3c452a6f19
@ -24,6 +24,9 @@
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#include "adc.h"
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#include "adc.h"
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#include "hardware.h"
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#include "hardware.h"
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#include "proto.h"
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#include "proto.h"
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#include "spi.h"
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#include "usart.h"
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#include "usb.h"
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void iwdg_setup(){
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void iwdg_setup(){
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uint32_t tmout = 16000000;
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uint32_t tmout = 16000000;
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@ -173,3 +176,44 @@ void hw_setup(){
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adc_setup();
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adc_setup();
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pwm_setup();
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pwm_setup();
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}
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}
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// USART & SPI both use common DMA interrupts, so put them together here
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// SPI Rx use the same DMA channels as USART Tx, so they can't work together!
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// USART1 Tx (channel 2) & SPI1 Tx (channel 3)
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void dma1_channel2_3_isr(){
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if(DMA1->ISR & DMA_ISR_TCIF2){ // Tx
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DMA1->IFCR |= DMA_IFCR_CTCIF2; // clear TC flag
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txrdy[0] = 1;
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}
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if(DMA1->ISR & DMA_ISR_TCIF3){ // transfer done
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DMA1->IFCR |= DMA_IFCR_CTCIF3;
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SPI_status[0] = SPI_READY;
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USND("SPI1 tx done\n");
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}
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if(DMA1->ISR & DMA_ISR_TEIF2){ // receiver overflow
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DMA1->IFCR |= DMA_IFCR_CTEIF2;
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SPIoverfl[0] = 1;
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}
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}
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// USART2 + USART3 Tx (channels 4 and 7) & SPI2 Tx (channel 5)
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void dma1_channel4_5_isr(){
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if(DMA1->ISR & DMA_ISR_TCIF4){ // Tx
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DMA1->IFCR |= DMA_IFCR_CTCIF4; // clear TC flag
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txrdy[1] = 1;
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}
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if(DMA1->ISR & DMA_ISR_TEIF4){
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DMA1->IFCR |= DMA_IFCR_CTEIF4;
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SPIoverfl[1] = 1;
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}
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if(DMA1->ISR & DMA_ISR_TCIF5){
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DMA1->IFCR |= DMA_IFCR_CTCIF5;
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SPI_status[1] = SPI_READY;
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USND("SPI2 tx done\n");
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}
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#ifdef USART3
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if(DMA1->ISR & DMA_ISR_TCIF7){ // Tx
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DMA1->IFCR |= DMA_IFCR_CTCIF7; // clear TC flag
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txrdy[2] = 1;
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}
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#endif
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}
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@ -46,12 +46,10 @@ int main(void){
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sysreset();
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sysreset();
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SysTick_Config(6000, 1);
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SysTick_Config(6000, 1);
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hw_setup();
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hw_setup();
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usart_setup();
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RCC->CSR |= RCC_CSR_RMVF; // remove reset flags
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RCC->CSR |= RCC_CSR_RMVF; // remove reset flags
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USB_setup();
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USB_setup();
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spi_setup();
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iwdg_setup();
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iwdg_setup();
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while (1){
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while (1){
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Binary file not shown.
@ -182,6 +182,7 @@ static inline char *DAC_chval(char *buf){
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static inline void wrSPI(int SPIidx, char *buf){
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static inline void wrSPI(int SPIidx, char *buf){
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uint16_t N = readNnumbers(buf);
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uint16_t N = readNnumbers(buf);
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if(N < 1){
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if(N < 1){
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*(uint8_t *)&(SPI1->DR) = 0xea;
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USND("Enter at least 1 number (max: ");
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USND("Enter at least 1 number (max: ");
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USB_sendstr(u2str(LOCBUFFSZ)); USND(")\n");
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USB_sendstr(u2str(LOCBUFFSZ)); USND(")\n");
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return;
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return;
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@ -234,7 +235,9 @@ const char *helpstring =
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"pr - get data from SPI2\n"
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"pr - get data from SPI2\n"
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"R - software reset\n"
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"R - software reset\n"
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"S - send short string over USB\n"
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"S - send short string over USB\n"
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"s - setup SPI (and turn off USARTs)\n"
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"Ux str - send string to USARTx (1..3)\n"
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"Ux str - send string to USARTx (1..3)\n"
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"u - setup USARTs (and turn off SPI)\n"
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"T - MCU temperature\n"
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"T - MCU temperature\n"
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"V - Vdd\n"
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"V - Vdd\n"
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"W - test watchdog\n"
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"W - test watchdog\n"
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@ -314,9 +317,19 @@ const char *parse_cmd(char *buf){
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USND("Test string for USB\n");
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USND("Test string for USB\n");
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return "Short test sent";
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return "Short test sent";
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break;
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break;
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case 's':
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USND("SPI are ON, USART are OFF\n");
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usart_stop();
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spi_setup();
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break;
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case 'T':
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case 'T':
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return u2str(getMCUtemp());
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return u2str(getMCUtemp());
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break;
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break;
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case 'u':
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USND("USART are ON, SPI are OFF\n");
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spi_stop();
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usart_setup();
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break;
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case 'V':
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case 'V':
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return u2str(getVdd());
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return u2str(getVdd());
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break;
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break;
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@ -25,7 +25,7 @@
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// buffers for DMA rx/tx
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// buffers for DMA rx/tx
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static uint8_t inbuff[SPInumber][SPIBUFSZ], outbuf[SPInumber][SPIBUFSZ];
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static uint8_t inbuff[SPInumber][SPIBUFSZ], outbuf[SPInumber][SPIBUFSZ];
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static uint8_t overfl[SPInumber] = {0, 0};
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volatile uint8_t SPIoverfl[SPInumber] = {0, 0};
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spiStatus SPI_status[SPInumber] = {SPI_NOTREADY, SPI_NOTREADY};
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spiStatus SPI_status[SPInumber] = {SPI_NOTREADY, SPI_NOTREADY};
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static DMA_Channel_TypeDef * const rxDMA[SPInumber] = {DMA1_Channel2, DMA1_Channel4};
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static DMA_Channel_TypeDef * const rxDMA[SPInumber] = {DMA1_Channel2, DMA1_Channel4};
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static DMA_Channel_TypeDef * const txDMA[SPInumber] = {DMA1_Channel3, DMA1_Channel5};
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static DMA_Channel_TypeDef * const txDMA[SPInumber] = {DMA1_Channel3, DMA1_Channel5};
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@ -46,6 +46,7 @@ static void spicommonsetup(uint8_t SPIidx, uint8_t master){
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/* Peripheral to memory */
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/* Peripheral to memory */
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/* 8-bit transfer */
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/* 8-bit transfer */
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/* Overflow IR */
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/* Overflow IR */
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rxDMA[SPIidx]->CCR &= ~DMA_CCR_EN;
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rxDMA[SPIidx]->CPAR = (uint32_t)&(SPI[SPIidx]->DR); /* (1) */
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rxDMA[SPIidx]->CPAR = (uint32_t)&(SPI[SPIidx]->DR); /* (1) */
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rxDMA[SPIidx]->CMAR = (uint32_t)inbuff[SPIidx]; /* (2) */
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rxDMA[SPIidx]->CMAR = (uint32_t)inbuff[SPIidx]; /* (2) */
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rxDMA[SPIidx]->CNDTR = SPIBUFSZ; /* (3) */
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rxDMA[SPIidx]->CNDTR = SPIBUFSZ; /* (3) */
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@ -57,6 +58,7 @@ static void spicommonsetup(uint8_t SPIidx, uint8_t master){
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/* Memory to peripheral*/
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/* Memory to peripheral*/
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/* 8-bit transfer */
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/* 8-bit transfer */
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/* Transfer complete IT */
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/* Transfer complete IT */
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txDMA[SPIidx]->CCR &= ~DMA_CCR_EN;
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txDMA[SPIidx]->CPAR = (uint32_t)&(SPI[SPIidx]->DR); /* (5) */
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txDMA[SPIidx]->CPAR = (uint32_t)&(SPI[SPIidx]->DR); /* (5) */
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txDMA[SPIidx]->CMAR = (uint32_t)outbuf[SPIidx]; /* (6) */
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txDMA[SPIidx]->CMAR = (uint32_t)outbuf[SPIidx]; /* (6) */
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txDMA[SPIidx]->CCR |= DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_DIR; /* (7) */
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txDMA[SPIidx]->CCR |= DMA_CCR_MINC | DMA_CCR_TCIE | DMA_CCR_DIR; /* (7) */
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@ -67,10 +69,12 @@ static void spicommonsetup(uint8_t SPIidx, uint8_t master){
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NVIC_EnableIRQ(txDMAirqn[SPIidx]);
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NVIC_EnableIRQ(txDMAirqn[SPIidx]);
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/* Configure SPI */
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/* Configure SPI */
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/* (1) Master selection, BR: Fpclk/256 CPOL and CPHA at zero (rising first edge) */
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/* (1) Master selection, BR: Fpclk/256 CPOL and CPHA at zero (rising first edge) */
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/* (1a) software slave management (SSI inactive) */
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/* (2) TX and RX with DMA, 8-bit Rx fifo */
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/* (2) TX and RX with DMA, 8-bit Rx fifo */
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/* (3) Enable SPI1 */
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/* (3) Enable SPI */
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SPI[SPIidx]->CR1 = master ? (SPI_CR1_MSTR | SPI_CR1_BR) : (SPI_CR1_BR); /* (1) */
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if(master) SPI[SPIidx]->CR1 = SPI_CR1_MSTR | SPI_CR1_BR | SPI_CR1_SSM | SPI_CR1_SSI; /* (1) */
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SPI[SPIidx]->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (2) */
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else SPI[SPIidx]->CR1 = SPI_CR1_SSM; // (1a)
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SPI[SPIidx]->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN | SPI_CR2_FRXTH | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; /* (2) */
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SPI[SPIidx]->CR1 |= SPI_CR1_SPE; /* (3) */
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SPI[SPIidx]->CR1 |= SPI_CR1_SPE; /* (3) */
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SPI_status[SPIidx] = SPI_READY;
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SPI_status[SPIidx] = SPI_READY;
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SPI_prep_receive(SPIidx);
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SPI_prep_receive(SPIidx);
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@ -90,36 +94,16 @@ void spi_setup(){
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GPIOB->AFR[1] = (GPIOB->AFR[1] & ~(GPIO_AFRH_AFRH5 | GPIO_AFRH_AFRH6 | GPIO_AFRH_AFRH7)); /* (2) */
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GPIOB->AFR[1] = (GPIOB->AFR[1] & ~(GPIO_AFRH_AFRH5 | GPIO_AFRH_AFRH6 | GPIO_AFRH_AFRH7)); /* (2) */
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// enable clocking
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// enable clocking
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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RCC->AHBENR |= RCC_AHBENR_DMA1EN;
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RCC->APB1ENR |= RCC_APB1ENR_SPI2EN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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// SPI1 - master, SPI2 - slave
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// SPI1 - master, SPI2 - slave
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spicommonsetup(0, 1);
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spicommonsetup(0, 1);
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spicommonsetup(1, 0);
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spicommonsetup(1, 0);
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}
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}
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// SPI1 Tx (channel 3)
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void spi_stop(){
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void dma1_channel2_3_isr(){
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RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN;
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if(DMA1->ISR & DMA_ISR_TCIF3){ // transfer done
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RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN;
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DMA1->IFCR |= DMA_IFCR_CTCIF3;
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SPI_status[0] = SPI_READY;
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USND("SPI1 tx done\n");
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}
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if(DMA1->ISR & DMA_ISR_TEIF2){ // receiver overflow
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DMA1->IFCR |= DMA_IFCR_CTEIF2;
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overfl[0] = 1;
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}
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}
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// SPI2 Tx (channel 5)
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void dma1_channel4_5_isr(){
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if(DMA1->ISR & DMA_ISR_TCIF5){
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DMA1->IFCR |= DMA_IFCR_CTCIF5;
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SPI_status[1] = SPI_READY;
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USND("SPI2 tx done\n");
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}
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if(DMA1->ISR & DMA_ISR_TEIF4){
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DMA1->IFCR |= DMA_IFCR_CTEIF4;
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overfl[1] = 1;
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}
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}
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}
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/**
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/**
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@ -132,11 +116,17 @@ void dma1_channel4_5_isr(){
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uint8_t SPI_transmit(uint8_t N, const uint8_t *buf, uint8_t len){
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uint8_t SPI_transmit(uint8_t N, const uint8_t *buf, uint8_t len){
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if(!buf || !len || len > SPIBUFSZ || N >= SPInumber) return 1; // bad data format
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if(!buf || !len || len > SPIBUFSZ || N >= SPInumber) return 1; // bad data format
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if(SPI_status[N] != SPI_READY) return 2; // spi not ready to transmit data
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if(SPI_status[N] != SPI_READY) return 2; // spi not ready to transmit data
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int ctr = 0;
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while(SPI[N]->SR & SPI_SR_FTLVL && ++ctr < 99999); // wait for transmission buffer empty
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ctr = 0;
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while(SPI[N]->SR & SPI_SR_BSY && ++ctr < 99999); // wait while busy
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USND("SPI->SR="); USB_sendstr(uhex2str(SPI[N]->SR)); USND("\n");
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txDMA[N]->CCR &=~ DMA_CCR_EN;
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txDMA[N]->CCR &=~ DMA_CCR_EN;
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memcpy(outbuf[N], buf, len);
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memcpy(outbuf[N], buf, len);
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txDMA[N]->CNDTR = len;
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txDMA[N]->CNDTR = len;
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SPI_status[N] = SPI_BUSY;
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txDMA[N]->CMAR = (uint32_t)outbuf[N];
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SPI_prep_receive(N);
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SPI_prep_receive(N);
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SPI_status[N] = SPI_BUSY;
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txDMA[N]->CCR |= DMA_CCR_EN;
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txDMA[N]->CCR |= DMA_CCR_EN;
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return 0;
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return 0;
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}
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}
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@ -145,9 +135,12 @@ uint8_t SPI_transmit(uint8_t N, const uint8_t *buf, uint8_t len){
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uint8_t SPI_prep_receive(uint8_t N){
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uint8_t SPI_prep_receive(uint8_t N){
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if(N >= SPInumber) return 1;
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if(N >= SPInumber) return 1;
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if(SPI_status[N] != SPI_READY) return 2; // still transmitting data
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if(SPI_status[N] != SPI_READY) return 2; // still transmitting data
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overfl[N] = 0;
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SPIoverfl[N] = 0;
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rxDMA[N]->CCR &= ~DMA_CCR_EN;
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rxDMA[N]->CCR &= ~DMA_CCR_EN;
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(void)SPI[N]->DR; // read DR and SR to clear OVR flag
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(void)SPI[N]->SR;
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rxDMA[N]->CNDTR = SPIBUFSZ;
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rxDMA[N]->CNDTR = SPIBUFSZ;
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rxDMA[N]->CMAR = (uint32_t)inbuff[N];
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rxDMA[N]->CCR |= DMA_CCR_EN;
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rxDMA[N]->CCR |= DMA_CCR_EN;
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return 0;
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return 0;
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}
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}
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@ -164,7 +157,7 @@ uint8_t SPI_getdata(uint8_t N, uint8_t *buf, uint8_t *maxlen){
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if(N >= SPInumber) return 1;
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if(N >= SPInumber) return 1;
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if(SPI_status[N] != SPI_READY) return 2; // still transmitting data
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if(SPI_status[N] != SPI_READY) return 2; // still transmitting data
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rxDMA[N]->CCR &= ~DMA_CCR_EN;
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rxDMA[N]->CCR &= ~DMA_CCR_EN;
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overfl[N] = 0;
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SPIoverfl[N] = 0;
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uint8_t remain = rxDMA[N]->CNDTR;
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uint8_t remain = rxDMA[N]->CNDTR;
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if(maxlen){
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if(maxlen){
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if(buf && *maxlen) memcpy(buf, inbuff[N], *maxlen);
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if(buf && *maxlen) memcpy(buf, inbuff[N], *maxlen);
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@ -179,7 +172,7 @@ uint8_t SPI_getdata(uint8_t N, uint8_t *buf, uint8_t *maxlen){
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// should be called BEFORE SPI_prep_receive() or SPI_getdata()
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// should be called BEFORE SPI_prep_receive() or SPI_getdata()
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uint8_t SPI_isoverflow(uint8_t N){
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uint8_t SPI_isoverflow(uint8_t N){
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if(N >= SPInumber) return 1;
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if(N >= SPInumber) return 1;
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register uint8_t o = overfl[N];
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register uint8_t o = SPIoverfl[N];
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overfl[N] = 0;
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SPIoverfl[N] = 0;
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return o;
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return o;
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}
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}
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@ -24,7 +24,7 @@
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#define SPInumber (2)
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#define SPInumber (2)
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#define SPIBUFSZ 4
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#define SPIBUFSZ (32)
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typedef enum{
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typedef enum{
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SPI_NOTREADY,
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SPI_NOTREADY,
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@ -33,8 +33,10 @@ typedef enum{
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} spiStatus;
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} spiStatus;
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extern spiStatus SPI_status[];
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extern spiStatus SPI_status[];
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extern volatile uint8_t SPIoverfl[];
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void spi_setup();
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void spi_setup();
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void spi_stop();
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uint8_t SPI_transmit(uint8_t N, const uint8_t *buf, uint8_t len);
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uint8_t SPI_transmit(uint8_t N, const uint8_t *buf, uint8_t len);
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uint8_t SPI_prep_receive(uint8_t N);
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uint8_t SPI_prep_receive(uint8_t N);
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uint8_t SPI_getdata(uint8_t N, uint8_t *buf, uint8_t *maxlen);
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uint8_t SPI_getdata(uint8_t N, uint8_t *buf, uint8_t *maxlen);
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@ -134,6 +134,7 @@ void usart_setup(){
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// clock
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// clock
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||||||
RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
|
RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
|
||||||
RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
|
RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
|
||||||
|
RCC->AHBENR |= RCC_AHBENR_DMA1EN;
|
||||||
#ifdef USART3
|
#ifdef USART3
|
||||||
GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER10 | GPIO_MODER_MODER11)) |
|
GPIOB->MODER = (GPIOB->MODER & ~(GPIO_MODER_MODER10 | GPIO_MODER_MODER11)) |
|
||||||
GPIO_MODER_MODER10_AF | GPIO_MODER_MODER11_AF;
|
GPIO_MODER_MODER10_AF | GPIO_MODER_MODER11_AF;
|
||||||
@ -144,6 +145,7 @@ void usart_setup(){
|
|||||||
for(int i = 0; i < USARTNUM; ++i){
|
for(int i = 0; i < USARTNUM; ++i){
|
||||||
USARTs[i]->ICR = 0xffffffff; // clear all flags
|
USARTs[i]->ICR = 0xffffffff; // clear all flags
|
||||||
// USARTX Tx DMA
|
// USARTX Tx DMA
|
||||||
|
USARTDMA[i]->CCR &= ~DMA_CCR_EN;
|
||||||
USARTDMA[i]->CPAR = (uint32_t) &USARTs[i]->TDR; // periph
|
USARTDMA[i]->CPAR = (uint32_t) &USARTs[i]->TDR; // periph
|
||||||
USARTDMA[i]->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq
|
USARTDMA[i]->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq
|
||||||
// setup usarts
|
// setup usarts
|
||||||
@ -168,6 +170,13 @@ void usart_setup(){
|
|||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void usart_stop(){
|
||||||
|
RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN;
|
||||||
|
RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN;
|
||||||
|
#ifdef USART3
|
||||||
|
RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
static void usart_IRQ(int usartno){
|
static void usart_IRQ(int usartno){
|
||||||
USART_TypeDef *USARTX = USARTs[usartno];
|
USART_TypeDef *USARTX = USARTs[usartno];
|
||||||
@ -221,7 +230,6 @@ void usart2_isr(){
|
|||||||
usart_IRQ(1);
|
usart_IRQ(1);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
// work with USART3 only @ boards that have it
|
// work with USART3 only @ boards that have it
|
||||||
#ifdef USART3
|
#ifdef USART3
|
||||||
void usart3_4_isr(){
|
void usart3_4_isr(){
|
||||||
@ -229,23 +237,3 @@ void usart3_4_isr(){
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
// USART1
|
|
||||||
void dma1_channel2_3_isr(){
|
|
||||||
if(DMA1->ISR & DMA_ISR_TCIF2){ // Tx
|
|
||||||
DMA1->IFCR |= DMA_IFCR_CTCIF2; // clear TC flag
|
|
||||||
txrdy[0] = 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
// USART2 + USART3
|
|
||||||
void dma1_channel4_5_isr(){
|
|
||||||
if(DMA1->ISR & DMA_ISR_TCIF4){ // Tx
|
|
||||||
DMA1->IFCR |= DMA_IFCR_CTCIF4; // clear TC flag
|
|
||||||
txrdy[1] = 1;
|
|
||||||
}
|
|
||||||
#ifdef USART3
|
|
||||||
if(DMA1->ISR & DMA_ISR_TCIF7){ // Tx
|
|
||||||
DMA1->IFCR |= DMA_IFCR_CTCIF7; // clear TC flag
|
|
||||||
txrdy[2] = 1;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|||||||
@ -54,5 +54,6 @@ void usart_send(int usartno, const char *str);
|
|||||||
void usart_sendn(int usartno, const char *str, uint32_t L);
|
void usart_sendn(int usartno, const char *str, uint32_t L);
|
||||||
void newline(int usartno);
|
void newline(int usartno);
|
||||||
void usart_putchar(int usartno, const char ch);
|
void usart_putchar(int usartno, const char ch);
|
||||||
|
void usart_stop();
|
||||||
|
|
||||||
#endif // __USART_H__
|
#endif // __USART_H__
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user