mirror of
https://github.com/eddyem/stm32samples.git
synced 2025-12-06 10:45:11 +03:00
add simplest blink for STM32F407
This commit is contained in:
parent
c4ba010c17
commit
3004604893
@ -62,8 +62,8 @@
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35,
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35,
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36
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36
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],
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],
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"visible_layers": "fffffff_ffffffff",
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"visible_layers": "000ffff_80000001",
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"zone_display_mode": 0
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"zone_display_mode": 1
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},
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},
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"meta": {
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"meta": {
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"filename": "stm32.kicad_prl",
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"filename": "stm32.kicad_prl",
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@ -3,52 +3,118 @@
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"design_settings": {
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"design_settings": {
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"defaults": {
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"defaults": {
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"board_outline_line_width": 0.15,
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"board_outline_line_width": 0.15,
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"copper_line_width": 0.2,
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"copper_line_width": 0.19999999999999998,
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"copper_text_italic": false,
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"copper_text_italic": false,
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"copper_text_size_h": 1.5,
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"copper_text_size_h": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_size_v": 1.5,
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"copper_text_thickness": 0.3,
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"copper_text_thickness": 0.3,
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"copper_text_upright": true,
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"copper_text_upright": false,
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"courtyard_line_width": 0.05,
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"courtyard_line_width": 0.049999999999999996,
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"other_line_width": 0.15,
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"dimension_precision": 4,
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"dimension_units": 3,
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"dimensions": {
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"arrow_length": 1270000,
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"extension_offset": 500000,
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"keep_text_aligned": true,
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"suppress_zeroes": false,
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"text_position": 0,
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"units_format": 1
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},
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"fab_line_width": 0.09999999999999999,
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"fab_text_italic": false,
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"fab_text_size_h": 1.0,
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"fab_text_size_v": 1.0,
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"fab_text_thickness": 0.15,
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"fab_text_upright": false,
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"other_line_width": 0.09999999999999999,
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"other_text_italic": false,
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"other_text_italic": false,
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"other_text_size_h": 1.0,
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"other_text_size_h": 1.0,
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"other_text_size_v": 1.0,
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"other_text_size_v": 1.0,
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"other_text_thickness": 0.15,
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"other_text_thickness": 0.15,
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"other_text_upright": true,
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"other_text_upright": false,
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"pads": {
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"drill": 0.8,
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"height": 1.5,
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"width": 1.5
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},
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"silk_line_width": 0.15,
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"silk_line_width": 0.15,
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"silk_text_italic": false,
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"silk_text_italic": false,
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"silk_text_size_h": 1.0,
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"silk_text_size_h": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_size_v": 1.0,
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"silk_text_thickness": 0.15,
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"silk_text_thickness": 0.15,
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"silk_text_upright": true
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"silk_text_upright": false,
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},
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"zones": {
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"diff_pair_dimensions": [
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"45_degree_only": true,
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{
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"min_clearance": 0.5
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"gap": 0.25,
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"via_gap": 0.25,
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"width": 0.2
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}
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}
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],
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},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"drc_exclusions": [],
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"meta": {
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"filename": "board_design_settings.json",
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"version": 2
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},
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"rule_severities": {
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"annular_width": "error",
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"clearance": "error",
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"copper_edge_clearance": "error",
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"courtyards_overlap": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"item_on_disabled_layer": "error",
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"items_not_allowed": "error",
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"length_out_of_range": "error",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"silk_over_copper": "warning",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unresolved_variable": "error",
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"via_dangling": "warning",
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"zone_has_empty_net": "error",
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"zones_intersect": "error"
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},
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"rule_severitieslegacy_courtyards_overlap": true,
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"rule_severitieslegacy_courtyards_overlap": true,
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"rule_severitieslegacy_no_courtyard_defined": false,
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"rule_severitieslegacy_no_courtyard_defined": false,
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"rules": {
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"rules": {
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"allow_blind_buried_vias": false,
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"allow_blind_buried_vias": false,
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"allow_microvias": false,
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"allow_microvias": false,
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_copper_edge_clearance": 0.075,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.2,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_drill": 0.09999999999999999,
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"min_microvia_drill": 0.09999999999999999,
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"min_silk_clearance": 0.0,
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"min_through_hole_diameter": 0.5,
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"min_through_hole_diameter": 0.5,
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"min_track_width": 0.2,
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"min_track_width": 0.19999999999999998,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_diameter": 0.7999999999999999,
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"min_via_diameter": 0.7999999999999999,
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"solder_mask_clearance": 0.2,
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"use_height_for_length_calcs": true
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"solder_mask_min_width": 0.0,
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"solder_paste_clearance": 0.0,
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"solder_paste_margin_ratio": -0.0
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},
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},
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"track_widths": [
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"track_widths": [
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0.2,
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0.0,
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0.2,
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0.2,
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0.3,
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0.3,
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0.5,
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0.5,
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@ -57,8 +123,8 @@
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],
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],
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"via_dimensions": [
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"via_dimensions": [
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{
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{
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"diameter": 1.0,
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"diameter": 0.0,
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"drill": 0.6
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"drill": 0.0
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},
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},
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{
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{
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"diameter": 1.0,
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"diameter": 1.0,
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@ -68,7 +134,9 @@
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"diameter": 1.5,
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"diameter": 1.5,
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"drill": 0.8
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"drill": 0.8
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}
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}
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]
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],
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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},
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},
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"layer_presets": []
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"layer_presets": []
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},
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},
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@ -303,9 +371,45 @@
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"name": "Default",
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.25,
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"track_width": 0.2,
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"via_diameter": 0.8,
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"via_diameter": 1.0,
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"via_drill": 0.4,
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"via_drill": 0.6,
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"wire_width": 6.0
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},
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{
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"bus_width": 12.0,
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"clearance": 0.3,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "0.5",
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"nets": [],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.5,
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"via_diameter": 1.0,
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"via_drill": 0.6,
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"wire_width": 6.0
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},
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{
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"bus_width": 12.0,
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"clearance": 0.5,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "1",
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"nets": [],
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 1.0,
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"via_diameter": 1.5,
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"via_drill": 0.8,
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"wire_width": 6.0
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"wire_width": 6.0
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}
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}
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],
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],
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File diff suppressed because it is too large
Load Diff
@ -33,7 +33,6 @@
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3,
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3,
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4,
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4,
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5,
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5,
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6,
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8,
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8,
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9,
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9,
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10,
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10,
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@ -44,7 +44,7 @@
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"silk_text_thickness": 0.15,
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"silk_text_thickness": 0.15,
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"silk_text_upright": false,
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"silk_text_upright": false,
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"zones": {
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"zones": {
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"45_degree_only": true,
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"45_degree_only": false,
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"min_clearance": 0.5
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"min_clearance": 0.5
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}
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}
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},
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},
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@ -64,6 +64,7 @@
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"drill_out_of_range": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"extra_footprint": "warning",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"hole_near_hole": "error",
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"invalid_outline": "error",
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"invalid_outline": "error",
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@ -79,9 +80,10 @@
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"padstack": "error",
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"padstack": "error",
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"pth_inside_courtyard": "ignore",
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"pth_inside_courtyard": "ignore",
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"shorting_items": "error",
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"shorting_items": "error",
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"silk_over_copper": "error",
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"silk_over_copper": "warning",
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"silk_overlap": "error",
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"silk_overlap": "warning",
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"skew_out_of_range": "error",
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"skew_out_of_range": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"too_many_vias": "error",
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"track_dangling": "warning",
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"track_dangling": "warning",
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"track_width": "error",
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"track_width": "error",
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@ -100,15 +102,16 @@
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"max_error": 0.005,
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"max_error": 0.005,
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"min_clearance": 0.0,
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"min_clearance": 0.0,
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"min_copper_edge_clearance": 0.075,
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"min_copper_edge_clearance": 0.075,
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"min_hole_clearance": 0.0,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_diameter": 0.19999999999999998,
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"min_microvia_drill": 0.09999999999999999,
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"min_microvia_drill": 0.09999999999999999,
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"min_silk_clearance": 0.0,
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"min_silk_clearance": 0.0,
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"min_through_hole_diameter": 0.6,
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"min_through_hole_diameter": 0.39999999999999997,
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"min_track_width": 0.19999999999999998,
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"min_track_width": 0.19999999999999998,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_annular_width": 0.049999999999999996,
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"min_via_diameter": 0.7999999999999999
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"min_via_diameter": 0.7999999999999999,
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"use_height_for_length_calcs": true
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},
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},
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"track_widths": [
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"track_widths": [
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0.0,
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0.0,
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@ -124,8 +127,12 @@
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"drill": 0.0
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"drill": 0.0
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},
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},
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{
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{
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"diameter": 1.5,
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"diameter": 0.8,
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"drill": 0.8
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"drill": 0.4
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},
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{
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"diameter": 1.2,
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"drill": 0.6
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}
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}
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],
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],
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"zones_allow_external_fillets": false,
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"zones_allow_external_fillets": false,
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@ -365,8 +372,8 @@
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.2,
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"track_width": 0.2,
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"via_diameter": 1.0,
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"via_diameter": 0.8,
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"via_drill": 0.6,
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"via_drill": 0.4,
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"wire_width": 6.0
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"wire_width": 6.0
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},
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},
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{
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{
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@ -383,8 +390,8 @@
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.5,
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"track_width": 0.5,
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"via_diameter": 1.5,
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"via_diameter": 1.2,
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"via_drill": 0.8,
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"via_drill": 0.6,
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"wire_width": 6.0
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"wire_width": 6.0
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},
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},
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{
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{
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@ -401,8 +408,8 @@
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 1.0,
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"track_width": 1.0,
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"via_diameter": 1.5,
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"via_diameter": 1.2,
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"via_drill": 0.8,
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"via_drill": 0.6,
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"wire_width": 6.0
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"wire_width": 6.0
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}
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}
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],
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],
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@ -463,6 +470,11 @@
|
|||||||
"subpart_first_id": 65,
|
"subpart_first_id": 65,
|
||||||
"subpart_id_separator": 0
|
"subpart_id_separator": 0
|
||||||
},
|
},
|
||||||
"sheets": [],
|
"sheets": [
|
||||||
|
[
|
||||||
|
"df5160f1-a89e-447f-9d39-7ad3081d6565",
|
||||||
|
""
|
||||||
|
]
|
||||||
|
],
|
||||||
"text_variables": {}
|
"text_variables": {}
|
||||||
}
|
}
|
||||||
|
|||||||
8118
F0:F030,F042,F072/usbcan_relay/kicad/stm32.kicad_sch
Normal file
8118
F0:F030,F042,F072/usbcan_relay/kicad/stm32.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
169
F4:F401/blink/Makefile
Normal file
169
F4:F401/blink/Makefile
Normal file
@ -0,0 +1,169 @@
|
|||||||
|
BINARY = blink
|
||||||
|
BOOTPORT ?= /dev/ttyUSB0
|
||||||
|
BOOTSPEED ?= 115200
|
||||||
|
# MCU FAMILY
|
||||||
|
FAMILY ?= F4
|
||||||
|
# MCU code
|
||||||
|
MCU ?= F407xx
|
||||||
|
# or __ARM_ARCH_7EM__
|
||||||
|
ARMARCH = __ARM_ARCH_7M__=1
|
||||||
|
# change this linking script depending on particular MCU model,
|
||||||
|
LDSCRIPT ?= stm32f407xg.ld
|
||||||
|
# debug
|
||||||
|
#DEFS = -DEBUG
|
||||||
|
|
||||||
|
INDEPENDENT_HEADERS=
|
||||||
|
|
||||||
|
FP_FLAGS ?= -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant
|
||||||
|
ASM_FLAGS ?= -mthumb -mcpu=cortex-m4 -mthumb-interwork -mlittle-endian -march=armv7e-m
|
||||||
|
ARCH_FLAGS = $(ASM_FLAGS) $(FP_FLAGS) -D $(ARMARCH)
|
||||||
|
|
||||||
|
# autoincremental version & build date
|
||||||
|
VERSION_FILE = version.inc
|
||||||
|
ifeq ($(shell test -e $(VERSION_FILE) && echo -n yes), yes)
|
||||||
|
NEXTVER := $(shell expr $$(awk '/#define BUILD_NUMBER/' $(VERSION_FILE) | tr -cd "[0-9]") + 1)
|
||||||
|
else
|
||||||
|
NEXTVER := "1"
|
||||||
|
endif
|
||||||
|
|
||||||
|
BUILDDATE := $(shell date +%Y-%m-%d)
|
||||||
|
|
||||||
|
###############################################################################
|
||||||
|
# Executables
|
||||||
|
#PREFIX ?= arm-none-eabi
|
||||||
|
# gcc from arm web site
|
||||||
|
PREFIX ?= /opt/bin/arm-none-eabi
|
||||||
|
TOOLCHLIB ?= /opt/arm-none-eabi/lib
|
||||||
|
RM := rm -f
|
||||||
|
RMDIR := rmdir
|
||||||
|
CC := $(PREFIX)-gcc
|
||||||
|
# don't replace ld with gcc: the binary size would be much greater!!
|
||||||
|
LD := $(PREFIX)-ld
|
||||||
|
AR := $(PREFIX)-ar
|
||||||
|
AS := $(PREFIX)-as
|
||||||
|
SIZE := $(PREFIX)-size
|
||||||
|
OBJCOPY := $(PREFIX)-objcopy
|
||||||
|
OBJDUMP := $(PREFIX)-objdump
|
||||||
|
GDB := $(PREFIX)-gdb
|
||||||
|
STFLASH := $(shell which st-flash)
|
||||||
|
STBOOT := $(shell which stm32flash)
|
||||||
|
DFUUTIL := $(shell which dfu-util)
|
||||||
|
|
||||||
|
###############################################################################
|
||||||
|
# Source files
|
||||||
|
OBJDIR := mk
|
||||||
|
SRC := $(wildcard *.c)
|
||||||
|
OBJS := $(addprefix $(OBJDIR)/, $(SRC:%.c=%.o))
|
||||||
|
STARTUP := $(OBJDIR)/startup.o
|
||||||
|
MAP := $(OBJDIR)/$(BINARY).map
|
||||||
|
OBJS += $(STARTUP)
|
||||||
|
# dependencies: we need them to recompile files if their headers-dependencies changed
|
||||||
|
DEPS := $(OBJS:.o=.d)
|
||||||
|
|
||||||
|
INC_DIR ?= ../inc
|
||||||
|
|
||||||
|
INCLUDE := -I$(INC_DIR)/Fx -I$(INC_DIR)/cm
|
||||||
|
LIB_DIR := $(INC_DIR)/ld
|
||||||
|
|
||||||
|
###############################################################################
|
||||||
|
# C flags
|
||||||
|
CFLAGS += -g3 -gdwarf-2
|
||||||
|
CFLAGS += -O2 -D__thumb2__=1 -MD
|
||||||
|
CFLAGS += -Wall -Werror -Wextra -Wshadow
|
||||||
|
CFLAGS += -fshort-enums -ffunction-sections -fdata-sections
|
||||||
|
#CFLAGS += -fno-common -ffunction-sections -fdata-sections -fno-stack-protector
|
||||||
|
CFLAGS += $(ARCH_FLAGS)
|
||||||
|
|
||||||
|
###############################################################################
|
||||||
|
# Linker flags
|
||||||
|
#LDFLAGS += -nostartfiles --static -nostdlib -specs=nosys.specs -specs=nano.specs
|
||||||
|
LDFLAGS += $(ARCH_FLAGS)
|
||||||
|
LDFLAGS += -specs=nosys.specs -specs=nano.specs
|
||||||
|
LDFLAGS += -L$(LIB_DIR)
|
||||||
|
#LDFLAGS += -L$(TOOLCHLIB)
|
||||||
|
LDFLAGS += -T$(LDSCRIPT)
|
||||||
|
LDFLAGS += -Wl,-Map=$(MAP),--cref -Wl,--gc-sections
|
||||||
|
|
||||||
|
###############################################################################
|
||||||
|
# Used libraries
|
||||||
|
#LDLIBS += -lc $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
|
||||||
|
|
||||||
|
DEFS += -DSTM32$(FAMILY) -DSTM32$(MCU)
|
||||||
|
|
||||||
|
ELF := $(OBJDIR)/$(BINARY).elf
|
||||||
|
LIST := $(OBJDIR)/$(BINARY).list
|
||||||
|
BIN := $(BINARY).bin
|
||||||
|
HEX := $(BINARY).hex
|
||||||
|
|
||||||
|
all: bin list size
|
||||||
|
|
||||||
|
elf: $(ELF)
|
||||||
|
bin: $(BIN)
|
||||||
|
hex: $(HEX)
|
||||||
|
list: $(LIST)
|
||||||
|
|
||||||
|
ifneq ($(MAKECMDGOALS),clean)
|
||||||
|
-include $(DEPS)
|
||||||
|
endif
|
||||||
|
|
||||||
|
$(OBJDIR):
|
||||||
|
mkdir $(OBJDIR)
|
||||||
|
|
||||||
|
$(STARTUP): $(INC_DIR)/startup/vector.c
|
||||||
|
$(CC) $(CFLAGS) $(DEFS) $(INCLUDE) -o $@ -c $<
|
||||||
|
|
||||||
|
$(VERSION_FILE): *.[ch]
|
||||||
|
[ -f $(VERSION_FILE) ] || echo -e "#define BUILD_NUMBER \"0\"\n#define BUILD_DATE \"none\"" > $(VERSION_FILE)
|
||||||
|
@echo " Generate version: $(NEXTVER) for date $(BUILDDATE)"
|
||||||
|
@sed -i "s/#define BUILD_NUMBER.*/#define BUILD_NUMBER \"$(NEXTVER)\"/" $(VERSION_FILE)
|
||||||
|
@sed -i "s/#define BUILD_DATE.*/#define BUILD_DATE \"$(BUILDDATE)\"/" $(VERSION_FILE)
|
||||||
|
|
||||||
|
#$(OBJDIR)/proto.o: proto.c $(VERSION_FILE)
|
||||||
|
|
||||||
|
$(OBJDIR)/%.o: %.c
|
||||||
|
@echo " CC $<"
|
||||||
|
$(CC) $(CFLAGS) $(DEFS) $(INCLUDE) -o $@ -c $<
|
||||||
|
|
||||||
|
$(BIN): $(ELF)
|
||||||
|
@echo " OBJCOPY $(BIN)"
|
||||||
|
$(OBJCOPY) -Obinary $(ELF) $(BIN)
|
||||||
|
|
||||||
|
$(HEX): $(ELF)
|
||||||
|
@echo " OBJCOPY $(HEX)"
|
||||||
|
$(OBJCOPY) -Oihex $(ELF) $(HEX)
|
||||||
|
|
||||||
|
$(LIST): $(ELF)
|
||||||
|
@echo " OBJDUMP $(LIST)"
|
||||||
|
$(OBJDUMP) -S $(ELF) > $(LIST)
|
||||||
|
|
||||||
|
$(ELF): $(OBJDIR) $(OBJS)
|
||||||
|
@echo " LD $(ELF)"
|
||||||
|
$(CC) $(LDFLAGS) $(OBJS) $(LDLIBS) -o $(ELF)
|
||||||
|
|
||||||
|
size: $(ELF)
|
||||||
|
$(SIZE) $(ELF)
|
||||||
|
|
||||||
|
clean:
|
||||||
|
@echo " CLEAN"
|
||||||
|
$(RM) $(OBJS) $(DEPS) $(ELF) $(HEX) $(LIST) $(MAP)
|
||||||
|
@rmdir $(OBJDIR) 2>/dev/null || true
|
||||||
|
|
||||||
|
|
||||||
|
flash: $(BIN)
|
||||||
|
@echo " FLASH $(BIN)"
|
||||||
|
$(STFLASH) write $(BIN) 0x8000000
|
||||||
|
|
||||||
|
boot: $(BIN)
|
||||||
|
@echo " LOAD $(BIN) through bootloader"
|
||||||
|
$(STBOOT) -b$(BOOTSPEED) $(BOOTPORT) -w $(BIN)
|
||||||
|
|
||||||
|
dfuboot: $(BIN)
|
||||||
|
@echo " LOAD $(BIN) THROUGH DFU"
|
||||||
|
$(DFUUTIL) -a0 -D $(BIN) -s 0x08000000
|
||||||
|
|
||||||
|
openocd:
|
||||||
|
openocd -f openocd.cfg
|
||||||
|
dbg:
|
||||||
|
arm-none-eabi-gdb $(ELF) -ex 'target remote localhost:3333' -ex 'monitor reset halt'
|
||||||
|
|
||||||
|
.PHONY: size clean flash boot dfuboot openocd dbg
|
||||||
1
F4:F401/blink/Readme
Normal file
1
F4:F401/blink/Readme
Normal file
@ -0,0 +1 @@
|
|||||||
|
Simple blink with LED on PC13 (Olimex E407 development board)
|
||||||
BIN
F4:F401/blink/blink.bin
Executable file
BIN
F4:F401/blink/blink.bin
Executable file
Binary file not shown.
49
F4:F401/blink/blink.c
Normal file
49
F4:F401/blink/blink.c
Normal file
@ -0,0 +1,49 @@
|
|||||||
|
/*
|
||||||
|
* systick_blink.c
|
||||||
|
*
|
||||||
|
* Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301, USA.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stm32f4.h>
|
||||||
|
|
||||||
|
static volatile uint32_t blink_ctr = 0;
|
||||||
|
|
||||||
|
void sys_tick_handler(void){
|
||||||
|
++blink_ctr;
|
||||||
|
}
|
||||||
|
|
||||||
|
TRUE_INLINE void gpio_setup(void){
|
||||||
|
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOCEN;
|
||||||
|
GPIOC->MODER = GPIO_MODER_MODER13_O;
|
||||||
|
GPIOE->MODER = GPIO_MODER_MODER2_O;
|
||||||
|
}
|
||||||
|
|
||||||
|
int main(void){
|
||||||
|
if(!StartHSE()) StartHSI();
|
||||||
|
// system frequency is 144MHz
|
||||||
|
SysTick_Config((uint32_t)144000); // 1ms
|
||||||
|
gpio_setup();
|
||||||
|
uint32_t ctr = blink_ctr;
|
||||||
|
while(1){
|
||||||
|
if(blink_ctr - ctr > 499){
|
||||||
|
ctr = blink_ctr;
|
||||||
|
pin_toggle(GPIOE, 1<<2);
|
||||||
|
pin_toggle(GPIOC, 1<<13);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
116
F4:F401/blink/openocd.cfg
Normal file
116
F4:F401/blink/openocd.cfg
Normal file
@ -0,0 +1,116 @@
|
|||||||
|
# script for stm32f4x family
|
||||||
|
|
||||||
|
#
|
||||||
|
# stm32 devices support both JTAG and SWD transports.
|
||||||
|
#
|
||||||
|
source [find interface/stlink-v2-1.cfg]
|
||||||
|
source [find target/swj-dp.tcl]
|
||||||
|
source [find mem_helper.tcl]
|
||||||
|
|
||||||
|
if { [info exists CHIPNAME] } {
|
||||||
|
set _CHIPNAME $CHIPNAME
|
||||||
|
} else {
|
||||||
|
set _CHIPNAME stm32f4x
|
||||||
|
}
|
||||||
|
|
||||||
|
set _ENDIAN little
|
||||||
|
|
||||||
|
# Work-area is a space in RAM used for flash programming
|
||||||
|
# By default use 32kB (Available RAM in smallest device STM32F410)
|
||||||
|
if { [info exists WORKAREASIZE] } {
|
||||||
|
set _WORKAREASIZE $WORKAREASIZE
|
||||||
|
} else {
|
||||||
|
set _WORKAREASIZE 0x8000
|
||||||
|
}
|
||||||
|
|
||||||
|
#jtag scan chain
|
||||||
|
if { [info exists CPUTAPID] } {
|
||||||
|
set _CPUTAPID $CPUTAPID
|
||||||
|
} else {
|
||||||
|
if { [using_jtag] } {
|
||||||
|
# See STM Document RM0090
|
||||||
|
# Section 38.6.3 - corresponds to Cortex-M4 r0p1
|
||||||
|
set _CPUTAPID 0x4ba00477
|
||||||
|
} {
|
||||||
|
set _CPUTAPID 0x2ba01477
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||||
|
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
||||||
|
|
||||||
|
if {[using_jtag]} {
|
||||||
|
jtag newtap $_CHIPNAME bs -irlen 5
|
||||||
|
}
|
||||||
|
|
||||||
|
set _TARGETNAME $_CHIPNAME.cpu
|
||||||
|
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
|
||||||
|
|
||||||
|
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||||
|
|
||||||
|
set _FLASHNAME $_CHIPNAME.flash
|
||||||
|
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
|
||||||
|
|
||||||
|
flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
|
||||||
|
|
||||||
|
if { [info exists QUADSPI] && $QUADSPI } {
|
||||||
|
set a [llength [flash list]]
|
||||||
|
set _QSPINAME $_CHIPNAME.qspi
|
||||||
|
flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
|
||||||
|
}
|
||||||
|
|
||||||
|
# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
|
||||||
|
#
|
||||||
|
# Since we may be running of an RC oscilator, we crank down the speed a
|
||||||
|
# bit more to be on the safe side. Perhaps superstition, but if are
|
||||||
|
# running off a crystal, we can run closer to the limit. Note
|
||||||
|
# that there can be a pretty wide band where things are more or less stable.
|
||||||
|
adapter speed 2000
|
||||||
|
|
||||||
|
adapter srst delay 100
|
||||||
|
if {[using_jtag]} {
|
||||||
|
jtag_ntrst_delay 100
|
||||||
|
}
|
||||||
|
|
||||||
|
reset_config srst_nogate
|
||||||
|
|
||||||
|
if {![using_hla]} {
|
||||||
|
# if srst is not fitted use SYSRESETREQ to
|
||||||
|
# perform a soft reset
|
||||||
|
cortex_m reset_config sysresetreq
|
||||||
|
}
|
||||||
|
|
||||||
|
$_TARGETNAME configure -event examine-end {
|
||||||
|
# Enable debug during low power modes (uses more power)
|
||||||
|
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
|
||||||
|
mmw 0xE0042004 0x00000007 0
|
||||||
|
|
||||||
|
# Stop watchdog counters during halt
|
||||||
|
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
|
||||||
|
mmw 0xE0042008 0x00001800 0
|
||||||
|
}
|
||||||
|
|
||||||
|
$_TARGETNAME configure -event trace-config {
|
||||||
|
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
|
||||||
|
# change this value accordingly to configure trace pins
|
||||||
|
# assignment
|
||||||
|
mmw 0xE0042004 0x00000020 0
|
||||||
|
}
|
||||||
|
|
||||||
|
$_TARGETNAME configure -event reset-init {
|
||||||
|
# Configure PLL to boost clock to HSI x 4 (64 MHz)
|
||||||
|
mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
|
||||||
|
mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
|
||||||
|
mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
|
||||||
|
sleep 10 ;# Wait for PLL to lock
|
||||||
|
mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
|
||||||
|
mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
|
||||||
|
|
||||||
|
# Boost JTAG frequency
|
||||||
|
adapter speed 8000
|
||||||
|
}
|
||||||
|
|
||||||
|
$_TARGETNAME configure -event reset-start {
|
||||||
|
# Reduce speed since CPU speed will slow down to 16MHz with the reset
|
||||||
|
adapter speed 2000
|
||||||
|
}
|
||||||
47
F4:F401/inc/Fx/common_macros.h
Normal file
47
F4:F401/inc/Fx/common_macros.h
Normal file
@ -0,0 +1,47 @@
|
|||||||
|
/*
|
||||||
|
* common_macros.h - common usable things
|
||||||
|
*
|
||||||
|
* Copyright 2018 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301, USA.
|
||||||
|
*/
|
||||||
|
#pragma once
|
||||||
|
#ifndef __COMMON_MACROS_H__
|
||||||
|
#define __COMMON_MACROS_H__
|
||||||
|
|
||||||
|
#ifndef TRUE_INLINE
|
||||||
|
#define TRUE_INLINE __attribute__((always_inline)) static inline
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef NULL
|
||||||
|
#define NULL (0)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// some good things from CMSIS
|
||||||
|
#define nop() __NOP()
|
||||||
|
|
||||||
|
#define pin_toggle(gpioport, gpios) do{ \
|
||||||
|
register uint32_t __port = gpioport->ODR; \
|
||||||
|
gpioport->BSRR = ((__port & (gpios)) << 16) | (~__port & (gpios));}while(0)
|
||||||
|
|
||||||
|
#define pin_set(gpioport, gpios) do{gpioport->BSRR = gpios;}while(0)
|
||||||
|
#define pin_clear(gpioport, gpios) do{gpioport->BSRR = ((gpios) << 16);}while(0)
|
||||||
|
#define pin_read(gpioport, gpios) (gpioport->IDR & (gpios) ? 1 : 0)
|
||||||
|
#define pin_write(gpioport, gpios) do{gpioport->ODR = gpios;}while(0)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#endif // __COMMON_MACROS_H__
|
||||||
285
F4:F401/inc/Fx/stm32f4.h
Normal file
285
F4:F401/inc/Fx/stm32f4.h
Normal file
@ -0,0 +1,285 @@
|
|||||||
|
/*
|
||||||
|
* This file is part of the stm32f4 project.
|
||||||
|
* Copyright 2022 Edward V. Emelianov <edward.emelianoff@gmail.com>.
|
||||||
|
*
|
||||||
|
* This program is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#pragma once
|
||||||
|
|
||||||
|
#include "vector.h"
|
||||||
|
#ifdef STM32F407xx
|
||||||
|
#include "stm32f407xx.h"
|
||||||
|
#else
|
||||||
|
#error "Define STM32F407xx"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "common_macros.h"
|
||||||
|
|
||||||
|
// HSE=12MHz, fVCO=288MHz (PLL_M=12, PLL_N=288), HCLK=144MHz (PLL_P=2), fUSB=48MHz (PLL_Q=6)
|
||||||
|
#ifndef PLL_M
|
||||||
|
#define PLL_M 12
|
||||||
|
#endif
|
||||||
|
#ifndef PLL_N
|
||||||
|
#define PLL_N 288
|
||||||
|
#endif
|
||||||
|
#ifndef PLL_P
|
||||||
|
#define PLL_P 2
|
||||||
|
#endif
|
||||||
|
#ifndef PLL_Q
|
||||||
|
#define PLL_Q 6
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef VECT_TAB_OFFSET
|
||||||
|
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
|
||||||
|
This value must be a multiple of 0x200. */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
/**
|
||||||
|
* @brief Setup the microcontroller system
|
||||||
|
* Initialize the FPU setting, vector table location and the PLL configuration is reset.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
TRUE_INLINE void sysreset(void) // not usable
|
||||||
|
{
|
||||||
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||||
|
/* Set HSION bit */
|
||||||
|
RCC->CR |= RCC_CR_HSION;
|
||||||
|
|
||||||
|
/* Reset CFGR register */
|
||||||
|
RCC->CFGR = 0;
|
||||||
|
|
||||||
|
/* Reset HSEON, CSSON and PLLON bits */
|
||||||
|
RCC->CR &=(uint32_t)0xFEF6FFFF;
|
||||||
|
|
||||||
|
/* Reset PLLCFGR register */
|
||||||
|
RCC->PLLCFGR = (uint32_t)0x24003010;
|
||||||
|
|
||||||
|
/* Reset HSEBYP bit */
|
||||||
|
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||||
|
|
||||||
|
/* Disable all interrupts */
|
||||||
|
RCC->CIR = 0x00000000;
|
||||||
|
|
||||||
|
#ifdef VECT_TAB_SRAM
|
||||||
|
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||||
|
#else
|
||||||
|
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define WAITWHILE(x) do{StartUpCounter = 0; while((x) && (++StartUpCounter < 0xffffff)){} if(StartUpCounter == 0xffffff) return 0;}while(0)
|
||||||
|
TRUE_INLINE int StartHSI(){ // HSI is 16MHz, so PLL_M=16, PLL_N=288, PLL_P=2, PLL_Q=6
|
||||||
|
uint32_t StartUpCounter = 0;
|
||||||
|
RCC->CR = (RCC->CR & ~RCC_CR_PLLON) | RCC_CR_HSION;
|
||||||
|
WAITWHILE(!(RCC->CR & RCC_CR_HSIRDY));
|
||||||
|
// Enable high performance mode (default after reset), System frequency up to 168 MHz, Vreg += 10%
|
||||||
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||||
|
PWR->CR |= PWR_CR_VOS;
|
||||||
|
WAITWHILE(!(PWR->CSR & PWR_CSR_VOSRDY));
|
||||||
|
// HCLK = SYSCLK, PCLK1 = HCLK/4, PCLK2 = HCLK/2
|
||||||
|
RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2)
|
||||||
|
) | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV2;
|
||||||
|
/* Configure the main PLL */
|
||||||
|
RCC->PLLCFGR = 16 | (288 << 6) | (6 << 24);
|
||||||
|
RCC->CR |= RCC_CR_PLLON; // Enable PLL
|
||||||
|
// Wait till PLL is ready
|
||||||
|
WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
|
||||||
|
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
||||||
|
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||||
|
// Select PLL as system clock source
|
||||||
|
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
// @return 1 if OK, 0 if failed
|
||||||
|
TRUE_INLINE int StartHSE(){ // fVCO can be from 192 to 432MHz
|
||||||
|
uint32_t StartUpCounter = 0;
|
||||||
|
RCC->CR = (RCC->CR & ~RCC_CR_PLLON) | RCC_CR_HSEON; // disable PLL to reconfigure, enable HSE
|
||||||
|
WAITWHILE(!(RCC->CR & RCC_CR_HSERDY));
|
||||||
|
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||||
|
// Enable high performance mode (default after reset), System frequency up to 168 MHz, Vreg += 10%
|
||||||
|
PWR->CR |= PWR_CR_VOS;
|
||||||
|
WAITWHILE(!(PWR->CSR & PWR_CSR_VOSRDY));
|
||||||
|
// HCLK = SYSCLK, PCLK1 = HCLK/4, PCLK2 = HCLK/2
|
||||||
|
RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2)
|
||||||
|
) | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV2;
|
||||||
|
/* Configure the main PLL */
|
||||||
|
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
|
||||||
|
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
||||||
|
RCC->CR |= RCC_CR_PLLON; // Enable PLL
|
||||||
|
// Wait till PLL is ready
|
||||||
|
WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
|
||||||
|
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
||||||
|
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||||
|
// Select PLL as system clock source
|
||||||
|
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
#undef WAITWHILE
|
||||||
|
|
||||||
|
|
||||||
|
/******************* Bit definition for GPIO_MODER register *****************/
|
||||||
|
// _AI - analog inpt, _O - general output, _AF - alternate function
|
||||||
|
#define GPIO_MODER_MODER0_AI ((uint32_t)0x00000003)
|
||||||
|
#define GPIO_MODER_MODER0_O ((uint32_t)0x00000001)
|
||||||
|
#define GPIO_MODER_MODER0_AF ((uint32_t)0x00000002)
|
||||||
|
#define GPIO_MODER_MODER1_AI ((uint32_t)0x0000000C)
|
||||||
|
#define GPIO_MODER_MODER1_O ((uint32_t)0x00000004)
|
||||||
|
#define GPIO_MODER_MODER1_AF ((uint32_t)0x00000008)
|
||||||
|
#define GPIO_MODER_MODER2_AI ((uint32_t)0x00000030)
|
||||||
|
#define GPIO_MODER_MODER2_O ((uint32_t)0x00000010)
|
||||||
|
#define GPIO_MODER_MODER2_AF ((uint32_t)0x00000020)
|
||||||
|
#define GPIO_MODER_MODER3_AI ((uint32_t)0x000000C0)
|
||||||
|
#define GPIO_MODER_MODER3_O ((uint32_t)0x00000040)
|
||||||
|
#define GPIO_MODER_MODER3_AF ((uint32_t)0x00000080)
|
||||||
|
#define GPIO_MODER_MODER4_AI ((uint32_t)0x00000300)
|
||||||
|
#define GPIO_MODER_MODER4_O ((uint32_t)0x00000100)
|
||||||
|
#define GPIO_MODER_MODER4_AF ((uint32_t)0x00000200)
|
||||||
|
#define GPIO_MODER_MODER5_AI ((uint32_t)0x00000C00)
|
||||||
|
#define GPIO_MODER_MODER5_O ((uint32_t)0x00000400)
|
||||||
|
#define GPIO_MODER_MODER5_AF ((uint32_t)0x00000800)
|
||||||
|
#define GPIO_MODER_MODER6_AI ((uint32_t)0x00003000)
|
||||||
|
#define GPIO_MODER_MODER6_O ((uint32_t)0x00001000)
|
||||||
|
#define GPIO_MODER_MODER6_AF ((uint32_t)0x00002000)
|
||||||
|
#define GPIO_MODER_MODER7_AI ((uint32_t)0x0000C000)
|
||||||
|
#define GPIO_MODER_MODER7_O ((uint32_t)0x00004000)
|
||||||
|
#define GPIO_MODER_MODER7_AF ((uint32_t)0x00008000)
|
||||||
|
#define GPIO_MODER_MODER8_AI ((uint32_t)0x00030000)
|
||||||
|
#define GPIO_MODER_MODER8_O ((uint32_t)0x00010000)
|
||||||
|
#define GPIO_MODER_MODER8_AF ((uint32_t)0x00020000)
|
||||||
|
#define GPIO_MODER_MODER9_AI ((uint32_t)0x000C0000)
|
||||||
|
#define GPIO_MODER_MODER9_O ((uint32_t)0x00040000)
|
||||||
|
#define GPIO_MODER_MODER9_AF ((uint32_t)0x00080000)
|
||||||
|
#define GPIO_MODER_MODER10_AI ((uint32_t)0x00300000)
|
||||||
|
#define GPIO_MODER_MODER10_O ((uint32_t)0x00100000)
|
||||||
|
#define GPIO_MODER_MODER10_AF ((uint32_t)0x00200000)
|
||||||
|
#define GPIO_MODER_MODER11_AI ((uint32_t)0x00C00000)
|
||||||
|
#define GPIO_MODER_MODER11_O ((uint32_t)0x00400000)
|
||||||
|
#define GPIO_MODER_MODER11_AF ((uint32_t)0x00800000)
|
||||||
|
#define GPIO_MODER_MODER12_AI ((uint32_t)0x03000000)
|
||||||
|
#define GPIO_MODER_MODER12_O ((uint32_t)0x01000000)
|
||||||
|
#define GPIO_MODER_MODER12_AF ((uint32_t)0x02000000)
|
||||||
|
#define GPIO_MODER_MODER13_AI ((uint32_t)0x0C000000)
|
||||||
|
#define GPIO_MODER_MODER13_O ((uint32_t)0x04000000)
|
||||||
|
#define GPIO_MODER_MODER13_AF ((uint32_t)0x08000000)
|
||||||
|
#define GPIO_MODER_MODER14_AI ((uint32_t)0x30000000)
|
||||||
|
#define GPIO_MODER_MODER14_O ((uint32_t)0x10000000)
|
||||||
|
#define GPIO_MODER_MODER14_AF ((uint32_t)0x20000000)
|
||||||
|
#define GPIO_MODER_MODER15_AI ((uint32_t)0xC0000000)
|
||||||
|
#define GPIO_MODER_MODER15_O ((uint32_t)0x40000000)
|
||||||
|
#define GPIO_MODER_MODER15_AF ((uint32_t)0x80000000)
|
||||||
|
|
||||||
|
/******************* Bit definition for GPIO_PUPDR register *****************/
|
||||||
|
// no/pullup/pulldown/reserved
|
||||||
|
// for n in $(seq 0 15); do echo "#define GPIO_PUPDR${n}_PU ((uint32_t)(1<<$((n*2))))";
|
||||||
|
// echo "#define GPIO_PUPDR${n}_PD ((uint32_t)(1<<$((n*2+1))))"; done
|
||||||
|
// alt+select column -> delete
|
||||||
|
#define GPIO_PUPDR0_PU ((uint32_t)(1<<0))
|
||||||
|
#define GPIO_PUPDR0_PD ((uint32_t)(1<<1))
|
||||||
|
#define GPIO_PUPDR1_PU ((uint32_t)(1<<2))
|
||||||
|
#define GPIO_PUPDR1_PD ((uint32_t)(1<<3))
|
||||||
|
#define GPIO_PUPDR2_PU ((uint32_t)(1<<4))
|
||||||
|
#define GPIO_PUPDR2_PD ((uint32_t)(1<<5))
|
||||||
|
#define GPIO_PUPDR3_PU ((uint32_t)(1<<6))
|
||||||
|
#define GPIO_PUPDR3_PD ((uint32_t)(1<<7))
|
||||||
|
#define GPIO_PUPDR4_PU ((uint32_t)(1<<8))
|
||||||
|
#define GPIO_PUPDR4_PD ((uint32_t)(1<<9))
|
||||||
|
#define GPIO_PUPDR5_PU ((uint32_t)(1<<10))
|
||||||
|
#define GPIO_PUPDR5_PD ((uint32_t)(1<<11))
|
||||||
|
#define GPIO_PUPDR6_PU ((uint32_t)(1<<12))
|
||||||
|
#define GPIO_PUPDR6_PD ((uint32_t)(1<<13))
|
||||||
|
#define GPIO_PUPDR7_PU ((uint32_t)(1<<14))
|
||||||
|
#define GPIO_PUPDR7_PD ((uint32_t)(1<<15))
|
||||||
|
#define GPIO_PUPDR8_PU ((uint32_t)(1<<16))
|
||||||
|
#define GPIO_PUPDR8_PD ((uint32_t)(1<<17))
|
||||||
|
#define GPIO_PUPDR9_PU ((uint32_t)(1<<18))
|
||||||
|
#define GPIO_PUPDR9_PD ((uint32_t)(1<<19))
|
||||||
|
#define GPIO_PUPDR10_PU ((uint32_t)(1<<20))
|
||||||
|
#define GPIO_PUPDR10_PD ((uint32_t)(1<<21))
|
||||||
|
#define GPIO_PUPDR11_PU ((uint32_t)(1<<22))
|
||||||
|
#define GPIO_PUPDR11_PD ((uint32_t)(1<<23))
|
||||||
|
#define GPIO_PUPDR12_PU ((uint32_t)(1<<24))
|
||||||
|
#define GPIO_PUPDR12_PD ((uint32_t)(1<<25))
|
||||||
|
#define GPIO_PUPDR13_PU ((uint32_t)(1<<26))
|
||||||
|
#define GPIO_PUPDR13_PD ((uint32_t)(1<<27))
|
||||||
|
#define GPIO_PUPDR14_PU ((uint32_t)(1<<28))
|
||||||
|
#define GPIO_PUPDR14_PD ((uint32_t)(1<<29))
|
||||||
|
#define GPIO_PUPDR15_PU ((uint32_t)(1<<30))
|
||||||
|
#define GPIO_PUPDR15_PD ((uint32_t)(1<<31))
|
||||||
|
// OSPEEDR
|
||||||
|
// for n in $(seq 0 15); do echo "#define GPIO_OSPEEDR${n}_MED ((uint32_t)(1<<$((n*2))))";
|
||||||
|
// echo "#define GPIO_OSPEEDR${n}_HIGH ((uint32_t)(3<<$((2*n))))"; done
|
||||||
|
#define GPIO_OSPEEDR0_MED ((uint32_t)(1<<0))
|
||||||
|
#define GPIO_OSPEEDR0_HIGH ((uint32_t)(3<<0))
|
||||||
|
#define GPIO_OSPEEDR1_MED ((uint32_t)(1<<2))
|
||||||
|
#define GPIO_OSPEEDR1_HIGH ((uint32_t)(3<<2))
|
||||||
|
#define GPIO_OSPEEDR2_MED ((uint32_t)(1<<4))
|
||||||
|
#define GPIO_OSPEEDR2_HIGH ((uint32_t)(3<<4))
|
||||||
|
#define GPIO_OSPEEDR3_MED ((uint32_t)(1<<6))
|
||||||
|
#define GPIO_OSPEEDR3_HIGH ((uint32_t)(3<<6))
|
||||||
|
#define GPIO_OSPEEDR4_MED ((uint32_t)(1<<8))
|
||||||
|
#define GPIO_OSPEEDR4_HIGH ((uint32_t)(3<<8))
|
||||||
|
#define GPIO_OSPEEDR5_MED ((uint32_t)(1<<10))
|
||||||
|
#define GPIO_OSPEEDR5_HIGH ((uint32_t)(3<<10))
|
||||||
|
#define GPIO_OSPEEDR6_MED ((uint32_t)(1<<12))
|
||||||
|
#define GPIO_OSPEEDR6_HIGH ((uint32_t)(3<<12))
|
||||||
|
#define GPIO_OSPEEDR7_MED ((uint32_t)(1<<14))
|
||||||
|
#define GPIO_OSPEEDR7_HIGH ((uint32_t)(3<<14))
|
||||||
|
#define GPIO_OSPEEDR8_MED ((uint32_t)(1<<16))
|
||||||
|
#define GPIO_OSPEEDR8_HIGH ((uint32_t)(3<<16))
|
||||||
|
#define GPIO_OSPEEDR9_MED ((uint32_t)(1<<18))
|
||||||
|
#define GPIO_OSPEEDR9_HIGH ((uint32_t)(3<<18))
|
||||||
|
#define GPIO_OSPEEDR10_MED ((uint32_t)(1<<20))
|
||||||
|
#define GPIO_OSPEEDR10_HIGH ((uint32_t)(3<<20))
|
||||||
|
#define GPIO_OSPEEDR11_MED ((uint32_t)(1<<22))
|
||||||
|
#define GPIO_OSPEEDR11_HIGH ((uint32_t)(3<<22))
|
||||||
|
#define GPIO_OSPEEDR12_MED ((uint32_t)(1<<24))
|
||||||
|
#define GPIO_OSPEEDR12_HIGH ((uint32_t)(3<<24))
|
||||||
|
#define GPIO_OSPEEDR13_MED ((uint32_t)(1<<26))
|
||||||
|
#define GPIO_OSPEEDR13_HIGH ((uint32_t)(3<<26))
|
||||||
|
#define GPIO_OSPEEDR14_MED ((uint32_t)(1<<28))
|
||||||
|
#define GPIO_OSPEEDR14_HIGH ((uint32_t)(3<<28))
|
||||||
|
#define GPIO_OSPEEDR15_MED ((uint32_t)(1<<30))
|
||||||
|
#define GPIO_OSPEEDR15_HIGH ((uint32_t)(3<<30))
|
||||||
|
|
||||||
|
|
||||||
|
/************************* ADC *************************/
|
||||||
|
/* inner termometer calibration values
|
||||||
|
* Temp = (V30 - Vsense)/Avg_Slope + 30
|
||||||
|
* Avg_Slope = (V30 - V110) / (110 - 30)
|
||||||
|
*/
|
||||||
|
#define TEMP110_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7C2))
|
||||||
|
#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
|
||||||
|
// VDDA_Actual = 3.3V * VREFINT_CAL / average vref value
|
||||||
|
#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7BA))
|
||||||
|
#define VDD_CALIB ((uint16_t) (330))
|
||||||
|
#define VDD_APPLI ((uint16_t) (300))
|
||||||
|
|
||||||
|
/************************* USART *************************/
|
||||||
|
|
||||||
|
#define USART_CR2_ADD_SHIFT 24
|
||||||
|
// set address/character match value
|
||||||
|
#define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)
|
||||||
|
|
||||||
|
/************************* IWDG *************************/
|
||||||
|
#define IWDG_REFRESH (uint32_t)(0x0000AAAA)
|
||||||
|
#define IWDG_WRITE_ACCESS (uint32_t)(0x00005555)
|
||||||
|
#define IWDG_START (uint32_t)(0x0000CCCC)
|
||||||
|
|
||||||
|
|
||||||
|
//#define do{}while(0)
|
||||||
15606
F4:F401/inc/Fx/stm32f407xx.h
Normal file
15606
F4:F401/inc/Fx/stm32f407xx.h
Normal file
File diff suppressed because it is too large
Load Diff
412
F4:F401/inc/Fx/vector.h
Normal file
412
F4:F401/inc/Fx/vector.h
Normal file
@ -0,0 +1,412 @@
|
|||||||
|
/*
|
||||||
|
* vector.h
|
||||||
|
*
|
||||||
|
* Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301, USA.
|
||||||
|
*/
|
||||||
|
#pragma once
|
||||||
|
#ifndef VECTOR_H
|
||||||
|
#define VECTOR_H
|
||||||
|
|
||||||
|
#ifndef WEAK
|
||||||
|
#define WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void WEAK reset_handler(void);
|
||||||
|
void WEAK nmi_handler(void);
|
||||||
|
void WEAK hard_fault_handler(void);
|
||||||
|
void WEAK sv_call_handler(void);
|
||||||
|
void WEAK pend_sv_handler(void);
|
||||||
|
void WEAK sys_tick_handler(void);
|
||||||
|
|
||||||
|
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||||
|
void WEAK mem_manage_handler(void);
|
||||||
|
void WEAK bus_fault_handler(void);
|
||||||
|
void WEAK usage_fault_handler(void);
|
||||||
|
void WEAK debug_monitor_handler(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined STM32F0
|
||||||
|
void WEAK wwdg_isr(void);
|
||||||
|
void WEAK pvd_isr(void);
|
||||||
|
void WEAK rtc_isr(void);
|
||||||
|
void WEAK flash_isr(void);
|
||||||
|
void WEAK rcc_isr(void);
|
||||||
|
void WEAK exti0_1_isr(void);
|
||||||
|
void WEAK exti2_3_isr(void);
|
||||||
|
void WEAK exti4_15_isr(void);
|
||||||
|
void WEAK tsc_isr(void);
|
||||||
|
void WEAK dma1_channel1_isr(void);
|
||||||
|
void WEAK dma1_channel2_3_isr(void);
|
||||||
|
void WEAK dma1_channel4_5_isr(void);
|
||||||
|
void WEAK adc_comp_isr(void);
|
||||||
|
void WEAK tim1_brk_up_trg_com_isr(void);
|
||||||
|
void WEAK tim1_cc_isr(void);
|
||||||
|
void WEAK tim2_isr(void);
|
||||||
|
void WEAK tim3_isr(void);
|
||||||
|
void WEAK tim6_dac_isr(void);
|
||||||
|
void WEAK tim7_isr(void);
|
||||||
|
void WEAK tim14_isr(void);
|
||||||
|
void WEAK tim15_isr(void);
|
||||||
|
void WEAK tim16_isr(void);
|
||||||
|
void WEAK tim17_isr(void);
|
||||||
|
void WEAK i2c1_isr(void);
|
||||||
|
void WEAK i2c2_isr(void);
|
||||||
|
void WEAK spi1_isr(void);
|
||||||
|
void WEAK spi2_isr(void);
|
||||||
|
void WEAK usart1_isr(void);
|
||||||
|
void WEAK usart2_isr(void);
|
||||||
|
void WEAK usart3_4_isr(void);
|
||||||
|
void WEAK cec_can_isr(void);
|
||||||
|
void WEAK usb_isr(void);
|
||||||
|
|
||||||
|
#elif defined STM32F1
|
||||||
|
void WEAK wwdg_isr(void);
|
||||||
|
void WEAK pvd_isr(void);
|
||||||
|
void WEAK tamper_isr(void);
|
||||||
|
void WEAK rtc_isr(void);
|
||||||
|
void WEAK flash_isr(void);
|
||||||
|
void WEAK rcc_isr(void);
|
||||||
|
void WEAK exti0_isr(void);
|
||||||
|
void WEAK exti1_isr(void);
|
||||||
|
void WEAK exti2_isr(void);
|
||||||
|
void WEAK exti3_isr(void);
|
||||||
|
void WEAK exti4_isr(void);
|
||||||
|
void WEAK dma1_channel1_isr(void);
|
||||||
|
void WEAK dma1_channel2_isr(void);
|
||||||
|
void WEAK dma1_channel3_isr(void);
|
||||||
|
void WEAK dma1_channel4_isr(void);
|
||||||
|
void WEAK dma1_channel5_isr(void);
|
||||||
|
void WEAK dma1_channel6_isr(void);
|
||||||
|
void WEAK dma1_channel7_isr(void);
|
||||||
|
void WEAK adc1_2_isr(void);
|
||||||
|
void WEAK usb_hp_can_tx_isr(void);
|
||||||
|
void WEAK usb_lp_can_rx0_isr(void);
|
||||||
|
void WEAK can_rx1_isr(void);
|
||||||
|
void WEAK can_sce_isr(void);
|
||||||
|
void WEAK exti9_5_isr(void);
|
||||||
|
void WEAK tim1_brk_isr(void);
|
||||||
|
void WEAK tim1_up_isr(void);
|
||||||
|
void WEAK tim1_trg_com_isr(void);
|
||||||
|
void WEAK tim1_cc_isr(void);
|
||||||
|
void WEAK tim2_isr(void);
|
||||||
|
void WEAK tim3_isr(void);
|
||||||
|
void WEAK tim4_isr(void);
|
||||||
|
void WEAK i2c1_ev_isr(void);
|
||||||
|
void WEAK i2c1_er_isr(void);
|
||||||
|
void WEAK i2c2_ev_isr(void);
|
||||||
|
void WEAK i2c2_er_isr(void);
|
||||||
|
void WEAK spi1_isr(void);
|
||||||
|
void WEAK spi2_isr(void);
|
||||||
|
void WEAK usart1_isr(void);
|
||||||
|
void WEAK usart2_isr(void);
|
||||||
|
void WEAK usart3_isr(void);
|
||||||
|
void WEAK exti15_10_isr(void);
|
||||||
|
void WEAK rtc_alarm_isr(void);
|
||||||
|
void WEAK usb_wakeup_isr(void);
|
||||||
|
void WEAK tim8_brk_isr(void);
|
||||||
|
void WEAK tim8_up_isr(void);
|
||||||
|
void WEAK tim8_trg_com_isr(void);
|
||||||
|
void WEAK tim8_cc_isr(void);
|
||||||
|
void WEAK adc3_isr(void);
|
||||||
|
void WEAK fsmc_isr(void);
|
||||||
|
void WEAK sdio_isr(void);
|
||||||
|
void WEAK tim5_isr(void);
|
||||||
|
void WEAK spi3_isr(void);
|
||||||
|
void WEAK uart4_isr(void);
|
||||||
|
void WEAK uart5_isr(void);
|
||||||
|
void WEAK tim6_isr(void);
|
||||||
|
void WEAK tim7_isr(void);
|
||||||
|
void WEAK dma2_channel1_isr(void);
|
||||||
|
void WEAK dma2_channel2_isr(void);
|
||||||
|
void WEAK dma2_channel3_isr(void);
|
||||||
|
void WEAK dma2_channel4_5_isr(void);
|
||||||
|
void WEAK dma2_channel5_isr(void);
|
||||||
|
void WEAK eth_isr(void);
|
||||||
|
void WEAK eth_wkup_isr(void);
|
||||||
|
void WEAK can2_tx_isr(void);
|
||||||
|
void WEAK can2_rx0_isr(void);
|
||||||
|
void WEAK can2_rx1_isr(void);
|
||||||
|
void WEAK can2_sce_isr(void);
|
||||||
|
void WEAK otg_fs_isr(void);
|
||||||
|
|
||||||
|
#elif defined STM32F2
|
||||||
|
void WEAK nvic_wwdg_isr(void);
|
||||||
|
void WEAK pvd_isr(void);
|
||||||
|
void WEAK tamp_stamp_isr(void);
|
||||||
|
void WEAK rtc_wkup_isr(void);
|
||||||
|
void WEAK flash_isr(void);
|
||||||
|
void WEAK rcc_isr(void);
|
||||||
|
void WEAK exti0_isr(void);
|
||||||
|
void WEAK exti1_isr(void);
|
||||||
|
void WEAK exti2_isr(void);
|
||||||
|
void WEAK exti3_isr(void);
|
||||||
|
void WEAK exti4_isr(void);
|
||||||
|
void WEAK dma1_stream0_isr(void);
|
||||||
|
void WEAK dma1_stream1_isr(void);
|
||||||
|
void WEAK dma1_stream2_isr(void);
|
||||||
|
void WEAK dma1_stream3_isr(void);
|
||||||
|
void WEAK dma1_stream4_isr(void);
|
||||||
|
void WEAK dma1_stream5_isr(void);
|
||||||
|
void WEAK dma1_stream6_isr(void);
|
||||||
|
void WEAK adc_isr(void);
|
||||||
|
void WEAK can1_tx_isr(void);
|
||||||
|
void WEAK can1_rx0_isr(void);
|
||||||
|
void WEAK can1_rx1_isr(void);
|
||||||
|
void WEAK can1_sce_isr(void);
|
||||||
|
void WEAK exti9_5_isr(void);
|
||||||
|
void WEAK tim1_brk_tim9_isr(void);
|
||||||
|
void WEAK tim1_up_tim10_isr(void);
|
||||||
|
void WEAK tim1_trg_com_tim11_isr(void);
|
||||||
|
void WEAK tim1_cc_isr(void);
|
||||||
|
void WEAK tim2_isr(void);
|
||||||
|
void WEAK tim3_isr(void);
|
||||||
|
void WEAK tim4_isr(void);
|
||||||
|
void WEAK i2c1_ev_isr(void);
|
||||||
|
void WEAK i2c1_er_isr(void);
|
||||||
|
void WEAK i2c2_ev_isr(void);
|
||||||
|
void WEAK i2c2_er_isr(void);
|
||||||
|
void WEAK spi1_isr(void);
|
||||||
|
void WEAK spi2_isr(void);
|
||||||
|
void WEAK usart1_isr(void);
|
||||||
|
void WEAK usart2_isr(void);
|
||||||
|
void WEAK usart3_isr(void);
|
||||||
|
void WEAK exti15_10_isr(void);
|
||||||
|
void WEAK rtc_alarm_isr(void);
|
||||||
|
void WEAK usb_fs_wkup_isr(void);
|
||||||
|
void WEAK tim8_brk_tim12_isr(void);
|
||||||
|
void WEAK tim8_up_tim13_isr(void);
|
||||||
|
void WEAK tim8_trg_com_tim14_isr(void);
|
||||||
|
void WEAK tim8_cc_isr(void);
|
||||||
|
void WEAK dma1_stream7_isr(void);
|
||||||
|
void WEAK fsmc_isr(void);
|
||||||
|
void WEAK sdio_isr(void);
|
||||||
|
void WEAK tim5_isr(void);
|
||||||
|
void WEAK spi3_isr(void);
|
||||||
|
void WEAK uart4_isr(void);
|
||||||
|
void WEAK uart5_isr(void);
|
||||||
|
void WEAK tim6_dac_isr(void);
|
||||||
|
void WEAK tim7_isr(void);
|
||||||
|
void WEAK dma2_stream0_isr(void);
|
||||||
|
void WEAK dma2_stream1_isr(void);
|
||||||
|
void WEAK dma2_stream2_isr(void);
|
||||||
|
void WEAK dma2_stream3_isr(void);
|
||||||
|
void WEAK dma2_stream4_isr(void);
|
||||||
|
void WEAK eth_isr(void);
|
||||||
|
void WEAK eth_wkup_isr(void);
|
||||||
|
void WEAK can2_tx_isr(void);
|
||||||
|
void WEAK can2_rx0_isr(void);
|
||||||
|
void WEAK can2_rx1_isr(void);
|
||||||
|
void WEAK can2_sce_isr(void);
|
||||||
|
void WEAK otg_fs_isr(void);
|
||||||
|
void WEAK dma2_stream5_isr(void);
|
||||||
|
void WEAK dma2_stream6_isr(void);
|
||||||
|
void WEAK dma2_stream7_isr(void);
|
||||||
|
void WEAK usart6_isr(void);
|
||||||
|
void WEAK i2c3_ev_isr(void);
|
||||||
|
void WEAK i2c3_er_isr(void);
|
||||||
|
void WEAK otg_hs_ep1_out_isr(void);
|
||||||
|
void WEAK otg_hs_ep1_in_isr(void);
|
||||||
|
void WEAK otg_hs_wkup_isr(void);
|
||||||
|
void WEAK otg_hs_isr(void);
|
||||||
|
void WEAK dcmi_isr(void);
|
||||||
|
void WEAK cryp_isr(void);
|
||||||
|
void WEAK hash_rng_isr(void);
|
||||||
|
|
||||||
|
#elif defined STM32F3
|
||||||
|
void WEAK nvic_wwdg_isr(void);
|
||||||
|
void WEAK pvd_isr(void);
|
||||||
|
void WEAK tamp_stamp_isr(void);
|
||||||
|
void WEAK rtc_wkup_isr(void);
|
||||||
|
void WEAK flash_isr(void);
|
||||||
|
void WEAK rcc_isr(void);
|
||||||
|
void WEAK exti0_isr(void);
|
||||||
|
void WEAK exti1_isr(void);
|
||||||
|
void WEAK exti2_tsc_isr(void);
|
||||||
|
void WEAK exti3_isr(void);
|
||||||
|
void WEAK exti4_isr(void);
|
||||||
|
void WEAK dma1_channel1_isr(void);
|
||||||
|
void WEAK dma1_channel2_isr(void);
|
||||||
|
void WEAK dma1_channel3_isr(void);
|
||||||
|
void WEAK dma1_channel4_isr(void);
|
||||||
|
void WEAK dma1_channel5_isr(void);
|
||||||
|
void WEAK dma1_channel6_isr(void);
|
||||||
|
void WEAK dma1_channel7_isr(void);
|
||||||
|
void WEAK adc1_2_isr(void);
|
||||||
|
void WEAK usb_hp_can1_tx_isr(void);
|
||||||
|
void WEAK usb_lp_can1_rx0_isr(void);
|
||||||
|
void WEAK can1_rx1_isr(void);
|
||||||
|
void WEAK can1_sce_isr(void);
|
||||||
|
void WEAK exti9_5_isr(void);
|
||||||
|
void WEAK tim1_brk_tim15_isr(void);
|
||||||
|
void WEAK tim1_up_tim16_isr(void);
|
||||||
|
void WEAK tim1_trg_com_tim17_isr(void);
|
||||||
|
void WEAK tim1_cc_isr(void);
|
||||||
|
void WEAK tim2_isr(void);
|
||||||
|
void WEAK tim3_isr(void);
|
||||||
|
void WEAK tim4_isr(void);
|
||||||
|
void WEAK i2c1_ev_exti23_isr(void);
|
||||||
|
void WEAK i2c1_er_isr(void);
|
||||||
|
void WEAK i2c2_ev_exti24_isr(void);
|
||||||
|
void WEAK i2c2_er_isr(void);
|
||||||
|
void WEAK spi1_isr(void);
|
||||||
|
void WEAK spi2_isr(void);
|
||||||
|
void WEAK usart1_exti25_isr(void);
|
||||||
|
void WEAK usart2_exti26_isr(void);
|
||||||
|
void WEAK usart3_exti28_isr(void);
|
||||||
|
void WEAK exti15_10_isr(void);
|
||||||
|
void WEAK rtc_alarm_isr(void);
|
||||||
|
void WEAK usb_wkup_a_isr(void);
|
||||||
|
void WEAK tim8_brk_isr(void);
|
||||||
|
void WEAK tim8_up_isr(void);
|
||||||
|
void WEAK tim8_trg_com_isr(void);
|
||||||
|
void WEAK tim8_cc_isr(void);
|
||||||
|
void WEAK adc3_isr(void);
|
||||||
|
void WEAK reserved_1_isr(void);
|
||||||
|
void WEAK reserved_2_isr(void);
|
||||||
|
void WEAK reserved_3_isr(void);
|
||||||
|
void WEAK spi3_isr(void);
|
||||||
|
void WEAK uart4_exti34_isr(void);
|
||||||
|
void WEAK uart5_exti35_isr(void);
|
||||||
|
void WEAK tim6_dac_isr(void);
|
||||||
|
void WEAK tim7_isr(void);
|
||||||
|
void WEAK dma2_channel1_isr(void);
|
||||||
|
void WEAK dma2_channel2_isr(void);
|
||||||
|
void WEAK dma2_channel3_isr(void);
|
||||||
|
void WEAK dma2_channel4_isr(void);
|
||||||
|
void WEAK dma2_channel5_isr(void);
|
||||||
|
void WEAK adc4_isr(void);
|
||||||
|
void WEAK reserved_4_isr(void);
|
||||||
|
void WEAK reserved_5_isr(void);
|
||||||
|
void WEAK comp123_isr(void);
|
||||||
|
void WEAK comp456_isr(void);
|
||||||
|
void WEAK comp7_isr(void);
|
||||||
|
void WEAK reserved_6_isr(void);
|
||||||
|
void WEAK reserved_7_isr(void);
|
||||||
|
void WEAK reserved_8_isr(void);
|
||||||
|
void WEAK reserved_9_isr(void);
|
||||||
|
void WEAK reserved_10_isr(void);
|
||||||
|
void WEAK reserved_11_isr(void);
|
||||||
|
void WEAK reserved_12_isr(void);
|
||||||
|
void WEAK usb_hp_isr(void);
|
||||||
|
void WEAK usb_lp_isr(void);
|
||||||
|
void WEAK usb_wkup_isr(void);
|
||||||
|
void WEAK reserved_13_isr(void);
|
||||||
|
void WEAK reserved_14_isr(void);
|
||||||
|
void WEAK reserved_15_isr(void);
|
||||||
|
void WEAK reserved_16_isr(void);
|
||||||
|
void WEAK fpu_isr(void);
|
||||||
|
|
||||||
|
#elif defined STM32F4
|
||||||
|
#include "stm32f4.h"
|
||||||
|
void WEAK nvic_wwdg_isr(void);
|
||||||
|
void WEAK pvd_isr(void);
|
||||||
|
void WEAK tamp_stamp_isr(void);
|
||||||
|
void WEAK rtc_wkup_isr(void);
|
||||||
|
void WEAK flash_isr(void);
|
||||||
|
void WEAK rcc_isr(void);
|
||||||
|
void WEAK exti0_isr(void);
|
||||||
|
void WEAK exti1_isr(void);
|
||||||
|
void WEAK exti2_isr(void);
|
||||||
|
void WEAK exti3_isr(void);
|
||||||
|
void WEAK exti4_isr(void);
|
||||||
|
void WEAK dma1_stream0_isr(void);
|
||||||
|
void WEAK dma1_stream1_isr(void);
|
||||||
|
void WEAK dma1_stream2_isr(void);
|
||||||
|
void WEAK dma1_stream3_isr(void);
|
||||||
|
void WEAK dma1_stream4_isr(void);
|
||||||
|
void WEAK dma1_stream5_isr(void);
|
||||||
|
void WEAK dma1_stream6_isr(void);
|
||||||
|
void WEAK adc_isr(void);
|
||||||
|
void WEAK can1_tx_isr(void);
|
||||||
|
void WEAK can1_rx0_isr(void);
|
||||||
|
void WEAK can1_rx1_isr(void);
|
||||||
|
void WEAK can1_sce_isr(void);
|
||||||
|
void WEAK exti9_5_isr(void);
|
||||||
|
void WEAK tim1_brk_tim9_isr(void);
|
||||||
|
void WEAK tim1_up_tim10_isr(void);
|
||||||
|
void WEAK tim1_trg_com_tim11_isr(void);
|
||||||
|
void WEAK tim1_cc_isr(void);
|
||||||
|
void WEAK tim2_isr(void);
|
||||||
|
void WEAK tim3_isr(void);
|
||||||
|
void WEAK tim4_isr(void);
|
||||||
|
void WEAK i2c1_ev_isr(void);
|
||||||
|
void WEAK i2c1_er_isr(void);
|
||||||
|
void WEAK i2c2_ev_isr(void);
|
||||||
|
void WEAK i2c2_er_isr(void);
|
||||||
|
void WEAK spi1_isr(void);
|
||||||
|
void WEAK spi2_isr(void);
|
||||||
|
void WEAK usart1_isr(void);
|
||||||
|
void WEAK usart2_isr(void);
|
||||||
|
void WEAK usart3_isr(void);
|
||||||
|
void WEAK exti15_10_isr(void);
|
||||||
|
void WEAK rtc_alarm_isr(void);
|
||||||
|
void WEAK usb_fs_wkup_isr(void);
|
||||||
|
void WEAK tim8_brk_tim12_isr(void);
|
||||||
|
void WEAK tim8_up_tim13_isr(void);
|
||||||
|
void WEAK tim8_trg_com_tim14_isr(void);
|
||||||
|
void WEAK tim8_cc_isr(void);
|
||||||
|
void WEAK dma1_stream7_isr(void);
|
||||||
|
void WEAK fsmc_isr(void);
|
||||||
|
void WEAK sdio_isr(void);
|
||||||
|
void WEAK tim5_isr(void);
|
||||||
|
void WEAK spi3_isr(void);
|
||||||
|
void WEAK uart4_isr(void);
|
||||||
|
void WEAK uart5_isr(void);
|
||||||
|
void WEAK tim6_dac_isr(void);
|
||||||
|
void WEAK tim7_isr(void);
|
||||||
|
void WEAK dma2_stream0_isr(void);
|
||||||
|
void WEAK dma2_stream1_isr(void);
|
||||||
|
void WEAK dma2_stream2_isr(void);
|
||||||
|
void WEAK dma2_stream3_isr(void);
|
||||||
|
void WEAK dma2_stream4_isr(void);
|
||||||
|
void WEAK eth_isr(void);
|
||||||
|
void WEAK eth_wkup_isr(void);
|
||||||
|
void WEAK can2_tx_isr(void);
|
||||||
|
void WEAK can2_rx0_isr(void);
|
||||||
|
void WEAK can2_rx1_isr(void);
|
||||||
|
void WEAK can2_sce_isr(void);
|
||||||
|
void WEAK otg_fs_isr(void);
|
||||||
|
void WEAK dma2_stream5_isr(void);
|
||||||
|
void WEAK dma2_stream6_isr(void);
|
||||||
|
void WEAK dma2_stream7_isr(void);
|
||||||
|
void WEAK usart6_isr(void);
|
||||||
|
void WEAK i2c3_ev_isr(void);
|
||||||
|
void WEAK i2c3_er_isr(void);
|
||||||
|
void WEAK otg_hs_ep1_out_isr(void);
|
||||||
|
void WEAK otg_hs_ep1_in_isr(void);
|
||||||
|
void WEAK otg_hs_wkup_isr(void);
|
||||||
|
void WEAK otg_hs_isr(void);
|
||||||
|
void WEAK dcmi_isr(void);
|
||||||
|
void WEAK cryp_isr(void);
|
||||||
|
void WEAK hash_rng_isr(void);
|
||||||
|
void WEAK fpu_isr(void);
|
||||||
|
void WEAK uart7_isr(void);
|
||||||
|
void WEAK uart8_isr(void);
|
||||||
|
void WEAK spi4_isr(void);
|
||||||
|
void WEAK spi5_isr(void);
|
||||||
|
void WEAK spi6_isr(void);
|
||||||
|
void WEAK sai1_isr(void);
|
||||||
|
void WEAK lcd_tft_isr(void);
|
||||||
|
void WEAK lcd_tft_err_isr(void);
|
||||||
|
void WEAK dma2d_isr(void);
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error "Not supported platform"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif // VECTOR_H
|
||||||
266
F4:F401/inc/cm/cmsis_compiler.h
Normal file
266
F4:F401/inc/cm/cmsis_compiler.h
Normal file
@ -0,0 +1,266 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_compiler.h
|
||||||
|
* @brief CMSIS compiler generic header file
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CMSIS_COMPILER_H
|
||||||
|
#define __CMSIS_COMPILER_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 4/5
|
||||||
|
*/
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#include "cmsis_armcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Arm Compiler 6 (armclang)
|
||||||
|
*/
|
||||||
|
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||||
|
#include "cmsis_armclang.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* GNU Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#include "cmsis_gcc.h"
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* IAR Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#include <cmsis_iccarm.h>
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TI Arm Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TI_ARM__ )
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __attribute__((packed))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TASKING Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM __asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
#define __NO_RETURN __attribute__((noreturn))
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#define __USED __attribute__((used))
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __attribute__((weak))
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT struct __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION union __packed__
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
struct __packed__ T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#define __ALIGNED(x) __align(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* COSMIC Compiler
|
||||||
|
*/
|
||||||
|
#elif defined ( __CSMC__ )
|
||||||
|
#include <cmsis_csm.h>
|
||||||
|
|
||||||
|
#ifndef __ASM
|
||||||
|
#define __ASM _asm
|
||||||
|
#endif
|
||||||
|
#ifndef __INLINE
|
||||||
|
#define __INLINE inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_INLINE
|
||||||
|
#define __STATIC_INLINE static inline
|
||||||
|
#endif
|
||||||
|
#ifndef __STATIC_FORCEINLINE
|
||||||
|
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||||
|
#endif
|
||||||
|
#ifndef __NO_RETURN
|
||||||
|
// NO RETURN is automatically detected hence no warning here
|
||||||
|
#define __NO_RETURN
|
||||||
|
#endif
|
||||||
|
#ifndef __USED
|
||||||
|
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||||
|
#define __USED
|
||||||
|
#endif
|
||||||
|
#ifndef __WEAK
|
||||||
|
#define __WEAK __weak
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED
|
||||||
|
#define __PACKED @packed
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_STRUCT
|
||||||
|
#define __PACKED_STRUCT @packed struct
|
||||||
|
#endif
|
||||||
|
#ifndef __PACKED_UNION
|
||||||
|
#define __PACKED_UNION @packed union
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||||
|
@packed struct T_UINT32 { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT16_READ
|
||||||
|
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||||
|
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_WRITE
|
||||||
|
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||||
|
#endif
|
||||||
|
#ifndef __UNALIGNED_UINT32_READ
|
||||||
|
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||||
|
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||||
|
#endif
|
||||||
|
#ifndef __ALIGNED
|
||||||
|
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||||
|
#define __ALIGNED(x)
|
||||||
|
#endif
|
||||||
|
#ifndef __RESTRICT
|
||||||
|
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||||
|
#define __RESTRICT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#else
|
||||||
|
#error Unknown compiler.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CMSIS_COMPILER_H */
|
||||||
|
|
||||||
2085
F4:F401/inc/cm/cmsis_gcc.h
Normal file
2085
F4:F401/inc/cm/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
39
F4:F401/inc/cm/cmsis_version.h
Normal file
39
F4:F401/inc/cm/cmsis_version.h
Normal file
@ -0,0 +1,39 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file cmsis_version.h
|
||||||
|
* @brief CMSIS Core(M) Version definitions
|
||||||
|
* @version V5.0.2
|
||||||
|
* @date 19. April 2017
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CMSIS_VERSION_H
|
||||||
|
#define __CMSIS_VERSION_H
|
||||||
|
|
||||||
|
/* CMSIS Version definitions */
|
||||||
|
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||||
|
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||||
|
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||||
|
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||||
|
#endif
|
||||||
2129
F4:F401/inc/cm/core_cm4.h
Normal file
2129
F4:F401/inc/cm/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
270
F4:F401/inc/cm/mpu_armv7.h
Normal file
270
F4:F401/inc/cm/mpu_armv7.h
Normal file
@ -0,0 +1,270 @@
|
|||||||
|
/******************************************************************************
|
||||||
|
* @file mpu_armv7.h
|
||||||
|
* @brief CMSIS MPU API for Armv7-M MPU
|
||||||
|
* @version V5.0.4
|
||||||
|
* @date 10. January 2018
|
||||||
|
******************************************************************************/
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#elif defined (__clang__)
|
||||||
|
#pragma clang system_header /* treat file as system include file */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef ARM_MPU_ARMV7_H
|
||||||
|
#define ARM_MPU_ARMV7_H
|
||||||
|
|
||||||
|
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||||
|
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||||
|
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||||
|
|
||||||
|
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||||
|
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||||
|
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||||
|
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||||
|
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||||
|
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||||
|
|
||||||
|
/** MPU Region Base Address Register Value
|
||||||
|
*
|
||||||
|
* \param Region The region to be configured, number 0 to 15.
|
||||||
|
* \param BaseAddress The base address for the region.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||||
|
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||||
|
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||||
|
(MPU_RBAR_VALID_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attributes
|
||||||
|
*
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||||
|
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||||
|
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||||
|
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||||
|
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||||
|
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||||
|
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||||
|
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Region Attribute and Size Register Value
|
||||||
|
*
|
||||||
|
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||||
|
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||||
|
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||||
|
* \param IsShareable Region is shareable between multiple bus masters.
|
||||||
|
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||||
|
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||||
|
* \param SubRegionDisable Sub-region disable field.
|
||||||
|
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||||
|
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for strongly ordered memory.
|
||||||
|
* - TEX: 000b
|
||||||
|
* - Shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Non-bufferable
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for device memory.
|
||||||
|
* - TEX: 000b (if non-shareable) or 010b (if shareable)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Non-cacheable
|
||||||
|
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||||
|
*
|
||||||
|
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute for normal memory.
|
||||||
|
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||||
|
* - Shareable or non-shareable
|
||||||
|
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||||
|
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||||
|
*
|
||||||
|
* \param OuterCp Configures the outer cache policy.
|
||||||
|
* \param InnerCp Configures the inner cache policy.
|
||||||
|
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute non-cacheable policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||||
|
|
||||||
|
/**
|
||||||
|
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||||
|
*/
|
||||||
|
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Struct for a single MPU Region
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||||
|
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||||
|
} ARM_MPU_Region_t;
|
||||||
|
|
||||||
|
/** Enable the MPU.
|
||||||
|
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Disable the MPU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||||
|
{
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||||
|
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||||
|
#endif
|
||||||
|
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Clear and disable the given MPU region.
|
||||||
|
* \param rnr Region number to be cleared.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RASR = 0U;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure an MPU region.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Configure the given MPU region.
|
||||||
|
* \param rnr Region number to be configured.
|
||||||
|
* \param rbar Value for RBAR register.
|
||||||
|
* \param rsar Value for RSAR register.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||||
|
{
|
||||||
|
MPU->RNR = rnr;
|
||||||
|
MPU->RBAR = rbar;
|
||||||
|
MPU->RASR = rasr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||||
|
* \param dst Destination data is copied to.
|
||||||
|
* \param src Source data is copied from.
|
||||||
|
* \param len Amount of data words to be copied.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
for (i = 0U; i < len; ++i)
|
||||||
|
{
|
||||||
|
dst[i] = src[i];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Load the given number of MPU regions from a table.
|
||||||
|
* \param table Pointer to the MPU configuration table.
|
||||||
|
* \param cnt Amount of regions to be configured.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||||
|
{
|
||||||
|
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||||
|
while (cnt > MPU_TYPE_RALIASES) {
|
||||||
|
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||||
|
table += MPU_TYPE_RALIASES;
|
||||||
|
cnt -= MPU_TYPE_RALIASES;
|
||||||
|
}
|
||||||
|
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
393
F4:F401/inc/ld/devices.data
Normal file
393
F4:F401/inc/ld/devices.data
Normal file
@ -0,0 +1,393 @@
|
|||||||
|
################################################################################
|
||||||
|
#
|
||||||
|
# Device chip tree definition file.
|
||||||
|
#
|
||||||
|
# Copyright (c) 2013 Frantisek Burian <Bufran@seznam.cz>
|
||||||
|
# Copyright (C) 2013 Werner Almesberger <wpwrak>
|
||||||
|
#
|
||||||
|
# Line description:
|
||||||
|
# <pattern> <parent> (<data> ...)
|
||||||
|
#
|
||||||
|
# <pattern>: is the pattern for the chip description to be searched for.
|
||||||
|
# The case of the pattern string is ignored.
|
||||||
|
# Pattern match symbols:
|
||||||
|
# ? - matches exactly one character
|
||||||
|
# * - matches none or more characters
|
||||||
|
# + - matches single or more characters
|
||||||
|
#
|
||||||
|
# <parent>: is the parent group name, where the search will continue.
|
||||||
|
# There are special parents names that controls traversing:
|
||||||
|
# "END" - Exit traversal.
|
||||||
|
# "+" - Don't change the parent. Use for split long line to two.
|
||||||
|
#
|
||||||
|
# <data>: space-separated list of preprocessor symbols supplied to the linker.
|
||||||
|
# -D option name is automatically prepended to each symbol definition
|
||||||
|
#
|
||||||
|
# All lines starting with # symbol are treated as Comments
|
||||||
|
#
|
||||||
|
# Recommended tree hierarchy:
|
||||||
|
#
|
||||||
|
# <device name> <family group> <device specific params>
|
||||||
|
# +- <family group> <family> <family group specific params>
|
||||||
|
# +- <family> <architecture> <device family specific params>
|
||||||
|
# +- <architecture> END <architecture specific params>
|
||||||
|
#
|
||||||
|
# You can split the long line into two or more by using "+" in the parent field,
|
||||||
|
# and defining same regex with appropriate parent on the next line. Example:
|
||||||
|
#
|
||||||
|
# device + PARAM1=aaa PARAM2=bbbb PARAM3=ccc PARAM4=dddd PARAM5=eeee
|
||||||
|
# device parent PARAM6=ffff PARAM7=gggg PARAM8=hhhh
|
||||||
|
# parent END
|
||||||
|
#
|
||||||
|
# The order of the lines is important. After the regex match, its parent will
|
||||||
|
# be used for match on the next line. If two regexp lines matches input, only
|
||||||
|
# the first will be evaluated, except special group definition "+"
|
||||||
|
#
|
||||||
|
# The regex matches entire sym
|
||||||
|
#
|
||||||
|
# Example:
|
||||||
|
#
|
||||||
|
# --- devices.data file ---
|
||||||
|
# stm32f05[01]?4* stm32f0 ROM=16K RAM=4K
|
||||||
|
# stm32f0 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000
|
||||||
|
# stm32 END
|
||||||
|
#
|
||||||
|
# --- queried chip name ---
|
||||||
|
# stm32f051c8t6
|
||||||
|
#
|
||||||
|
# --- output of the awk script ---
|
||||||
|
# -DROM=16K -DRAM=4K -DROM_OFF=0x08000000 -DRAM_OFF=0x20000000
|
||||||
|
#
|
||||||
|
# The generated linker script file will contain sections rom and ram with
|
||||||
|
# appropriate initialization code, specified in linker file source linker.ld.S
|
||||||
|
#
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# the STM32 chips
|
||||||
|
|
||||||
|
stm32f03[01]?4* stm32f0 ROM=16K RAM=4K
|
||||||
|
stm32f03[01]?6* stm32f0 ROM=32K RAM=4K
|
||||||
|
stm32f030?8* stm32f0 ROM=64K RAM=8K
|
||||||
|
stm32f050?4* stm32f0 ROM=16K RAM=4K
|
||||||
|
stm32f050?6* stm32f0 ROM=32K RAM=4K
|
||||||
|
stm32f051?4* stm32f0 ROM=16K RAM=8K
|
||||||
|
stm32f051?6* stm32f0 ROM=32K RAM=8K
|
||||||
|
stm32f051?8* stm32f0 ROM=64K RAM=8K
|
||||||
|
stm32f072?8* stm32f0 ROM=64K RAM=16K
|
||||||
|
stm32f07[12]?B* stm32f0 ROM=128K RAM=16K
|
||||||
|
|
||||||
|
stm32f10[012]?4* stm32f1 ROM=16K RAM=4K
|
||||||
|
stm32f103?4* stm32f1 ROM=16K RAM=6K
|
||||||
|
stm32f100?6* stm32f1 ROM=32K RAM=4K
|
||||||
|
stm32f103?6* stm32f1 ROM=32K RAM=10K
|
||||||
|
stm32f10[12]?6* stm32f1 ROM=32K RAM=6K
|
||||||
|
stm32f100?8* stm32f1 ROM=64K RAM=8K
|
||||||
|
stm32f10[12]?8* stm32f1 ROM=64K RAM=10K
|
||||||
|
stm32f103?8* stm32f1 ROM=64K RAM=20K
|
||||||
|
stm32f100?b* stm32f1 ROM=128K RAM=8K
|
||||||
|
stm32f10[12]?b* stm32f1 ROM=128K RAM=16K
|
||||||
|
stm32f103?b* stm32f1 ROM=128K RAM=20K
|
||||||
|
stm32f10[57]?b* stm32f1 ROM=128K RAM=64K
|
||||||
|
stm32f100?c* stm32f1 ROM=256K RAM=24K
|
||||||
|
stm32f101?c* stm32f1 ROM=256K RAM=32K
|
||||||
|
stm32f103?c* stm32f1 ROM=256K RAM=48K
|
||||||
|
stm32f10[57]?c* stm32f1 ROM=256K RAM=64K
|
||||||
|
stm32f100?d* stm32f1 ROM=384K RAM=32K
|
||||||
|
stm32f101?d* stm32f1 ROM=384K RAM=48K
|
||||||
|
stm32f103?d* stm32f1 ROM=384K RAM=64K
|
||||||
|
stm32f100?e* stm32f1 ROM=512K RAM=32K
|
||||||
|
stm32f101?e* stm32f1 ROM=512K RAM=48K
|
||||||
|
stm32f103?e* stm32f1 ROM=512K RAM=64K
|
||||||
|
stm32f100?f* stm32f1 ROM=768K RAM=80K
|
||||||
|
stm32f103?f* stm32f1 ROM=768K RAM=96K
|
||||||
|
stm32f100?g* stm32f1 ROM=1024K RAM=80K
|
||||||
|
stm32f103?g* stm32f1 ROM=1024K RAM=96K
|
||||||
|
|
||||||
|
stm32f205?b* stm32f2 ROM=128K RAM=64K
|
||||||
|
stm32f205?c* stm32f2 ROM=256K RAM=96K
|
||||||
|
stm32f207?c* stm32f2 ROM=256K RAM=128K
|
||||||
|
stm32f2[01][57]?e* stm32f2 ROM=512K RAM=128K
|
||||||
|
stm32f20[57]?f* stm32f2 ROM=768K RAM=128K
|
||||||
|
stm32f2[01][57]?g* stm32f2 ROM=1024K RAM=128K
|
||||||
|
|
||||||
|
stm32f302?b* stm32f3ccm ROM=128K RAM=24K CCM=8K
|
||||||
|
stm32f302?c* stm32f3ccm ROM=256K RAM=32K CCM=8K
|
||||||
|
stm32f303?b* stm32f3ccm ROM=128K RAM=40K CCM=8K
|
||||||
|
stm32f3[01]3?c* stm32f3ccm ROM=256K RAM=48K CCM=8K
|
||||||
|
stm32f373?8* stm32f3 ROM=64K RAM=16K
|
||||||
|
stm32f373?b* stm32f3 ROM=128K RAM=24K
|
||||||
|
stm32f3[78]3?8* stm32f3 ROM=256K RAM=32K
|
||||||
|
|
||||||
|
stm32f401?b* stm32f4 ROM=128K RAM=64K
|
||||||
|
stm32f401?c* stm32f4 ROM=256K RAM=64K
|
||||||
|
stm32f401?d* stm32f4 ROM=512K RAM=96K
|
||||||
|
stm32f401?e* stm32f4 ROM=384K RAM=96K
|
||||||
|
stm32f4[01][57]?e* stm32f4ccm ROM=512K RAM=128K CCM=64K
|
||||||
|
stm32f4[01][57]?g* stm32f4ccm ROM=1024K RAM=128K CCM=64K
|
||||||
|
stm32f4[23][79]?g* stm32f4ccm ROM=1024K RAM=192K CCM=64K
|
||||||
|
stm32f4[23][79]?i* stm32f4ccm ROM=2048K RAM=192K CCM=64K
|
||||||
|
|
||||||
|
stm32l0???6* stm32l0 ROM=32K RAM=8K
|
||||||
|
stm32l0???8* stm32l0 ROM=64K RAM=8K
|
||||||
|
|
||||||
|
stm32l100?6* stm32l1 ROM=32K RAM=4K
|
||||||
|
stm32l100?8* stm32l1 ROM=64K RAM=8K
|
||||||
|
stm32l100?b* stm32l1 ROM=128K RAM=10K
|
||||||
|
stm32l100?c* stm32l1 ROM=256K RAM=16K
|
||||||
|
stm32l15[12]?6* stm32l1eep ROM=32K RAM=10K EEP=4K
|
||||||
|
stm32l15[12]?8* stm32l1eep ROM=64K RAM=10K EEP=4K
|
||||||
|
stm32l15[12]?b* stm32l1eep ROM=128K RAM=16K EEP=4K
|
||||||
|
stm32l15[12]?c* stm32l1eep ROM=256K RAM=32K EEP=8K
|
||||||
|
stm32l15[12]?d* stm32l1eep ROM=384K RAM=48K EEP=12K
|
||||||
|
stm32l162?c* stm32l1eep ROM=256K RAM=32K EEP=8K
|
||||||
|
stm32l162?d* stm32l1eep ROM=384K RAM=48K EEP=12K
|
||||||
|
|
||||||
|
stm32ts60 stm32t ROM=32K RAM=10K
|
||||||
|
|
||||||
|
stm32w108c8 stm32w ROM=64K RAM=8K
|
||||||
|
stm32w108?b stm32w ROM=128K RAM=8K
|
||||||
|
stm32w108cz stm32w ROM=192K RAM=12K
|
||||||
|
stm32w108cc stm32w ROM=256K RAM=16K
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# the SAM3 chips
|
||||||
|
|
||||||
|
sam3a4* sam3a ROM=256K RAM=32K RAM1=32K
|
||||||
|
sam3a8* sam3a ROM=512K RAM=64K RAM1=32K
|
||||||
|
|
||||||
|
sam3n00* sam3n ROM=16K RAM=4K
|
||||||
|
sam3n0* sam3n ROM=32K RAM=8K
|
||||||
|
sam3n1* sam3n ROM=64K RAM=8K
|
||||||
|
sam3n2* sam3n ROM=128K RAM=16K
|
||||||
|
sam3n4* sam3n ROM=256K RAM=24K
|
||||||
|
|
||||||
|
sam3s1* sam3s ROM=64K RAM=16K
|
||||||
|
sam3s2* sam3s ROM=128K RAM=32K
|
||||||
|
sam3s4* sam3s ROM=256K RAM=48K
|
||||||
|
sam3s8* sam3s ROM=512K RAM=64K
|
||||||
|
sam3sd8* sam3s ROM=512K RAM=64K
|
||||||
|
|
||||||
|
sam3u1* sam3u ROM=64K RAM=8K RAM1=8K
|
||||||
|
sam3u2* sam3u ROM=128K RAM=16K RAM1=16K
|
||||||
|
sam3u4* sam3u ROM=265K RAM=32K RAM1=16K
|
||||||
|
|
||||||
|
sam3x4c* sam3x ROM=256K RAM=32K RAM1=32K
|
||||||
|
sam3x4e* sam3xnfc ROM=256K RAM=32K RAM1=32K
|
||||||
|
sam3x8c* sam3x ROM=512K RAM=64K RAM1=32K
|
||||||
|
sam3x8e* sam3xnfc ROM=512K RAM=64K RAM1=32K
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# the lpc chips
|
||||||
|
|
||||||
|
lpc1311* lpc13 ROM=8K RAM=4K
|
||||||
|
lpc1313* lpc13 ROM=32K RAM=8K
|
||||||
|
lpc1342* lpc13 ROM=16K RAM=4K
|
||||||
|
lpc1343* lpc13 ROM=32K RAM=8K
|
||||||
|
lpc1315* lpc13u ROM=32K RAM=8K
|
||||||
|
lpc1316* lpc13u ROM=48K RAM=8K
|
||||||
|
lpc1317* lpc13u ROM=64K RAM=8K RAM1=2K
|
||||||
|
lpc1345* lpc13u ROM=32K RAM=8K USBRAM=2K
|
||||||
|
lpc1346* lpc13u ROM=48K RAM=8K USBRAM=2K
|
||||||
|
lpc1346* lpc13u ROM=64K RAM=8K USBRAM=2K RAM1=2K
|
||||||
|
|
||||||
|
lpc1751* lpc175x ROM=32K RAM=8K
|
||||||
|
lpc1752* lpc175x ROM=64K RAM=16K
|
||||||
|
lpc1754* lpc175x ROM=128K RAM=16K RAM1=16K
|
||||||
|
lpc1756* lpc175x ROM=256K RAM=16K RAM1=16K
|
||||||
|
lpc1758* lpc175x ROM=512K RAM=32K RAM1=16K RAM2=16K
|
||||||
|
lpc1759* lpc175x ROM=512K RAM=32K RAM1=16K RAM2=16K
|
||||||
|
lpc1763* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K
|
||||||
|
lpc1764* lpc176x ROM=128K RAM=16K RAM1=16K
|
||||||
|
lpc1765* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K
|
||||||
|
lpc1766* lpc176x ROM=256K RAM=32K RAM1=16K RAM2=16K
|
||||||
|
lpc1767* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K
|
||||||
|
lpc1768* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K
|
||||||
|
lpc1769* lpc176x ROM=512K RAM=32K RAM1=16K RAM2=16K
|
||||||
|
lpc1774* lpc177x ROM=128K RAM=32K RAM1=8K
|
||||||
|
lpc1776* lpc177x ROM=256K RAM=64K RAM1=16K
|
||||||
|
lpc1777* lpc177x ROM=512K RAM=64K RAM1=16K RAM2=16K
|
||||||
|
lpc1778* lpc177x ROM=512K RAM=64K RAM1=16K RAM2=16K
|
||||||
|
lpc1785* lpc178x ROM=256K RAM=64K RAM1=16K
|
||||||
|
lpc1786* lpc178x ROM=256K RAM=64K RAM1=16K
|
||||||
|
lpc1787* lpc178x ROM=512K RAM=64K RAM1=16K RAM2=16K
|
||||||
|
lpc1788* lpc178x ROM=512K RAM=64K RAM1=16K RAM2=16K
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# the efm32 chips
|
||||||
|
|
||||||
|
# Zero Gecko
|
||||||
|
efm32zg???f4 efm32zg ROM=4K RAM=2K
|
||||||
|
efm32zg???f8 efm32zg ROM=8K RAM=2K
|
||||||
|
efm32zg???f16 efm32zg ROM=16K RAM=4K
|
||||||
|
efm32zg???f32 efm32zg ROM=32K RAM=4K
|
||||||
|
|
||||||
|
# Tiny Gecko
|
||||||
|
efm32tg108f4 efm32tg ROM=4K RAM=1K
|
||||||
|
efm32tg110f4 efm32tg ROM=4K RAM=2K
|
||||||
|
efm32tg???f8 efm32tg ROM=8K RAM=2K
|
||||||
|
efm32tg???f16 efm32tg ROM=16K RAM=4K
|
||||||
|
efm32tg???f32 efm32tg ROM=32K RAM=4K
|
||||||
|
|
||||||
|
# Gecko
|
||||||
|
efm32g200f16 efm32g ROM=16K RAM=8K
|
||||||
|
efm32g???f32 efm32g ROM=32K RAM=8K
|
||||||
|
efm32g???f64 efm32g ROM=64K RAM=16K
|
||||||
|
efm32g???f128 efm32g ROM=128K RAM=16K
|
||||||
|
|
||||||
|
# Large Gecko
|
||||||
|
efm32lg???f64 efm32lg ROM=64K RAM=32K
|
||||||
|
efm32lg???f128 efm32lg ROM=128K RAM=32K
|
||||||
|
efm32lg???f256 efm32lg ROM=256K RAM=32K
|
||||||
|
|
||||||
|
# Giant Gecko
|
||||||
|
efm32gg???f512 efm32gg ROM=512K RAM=128K
|
||||||
|
efm32gg???f1024 efm32gg ROM=1024K RAM=128K
|
||||||
|
|
||||||
|
# Wonder Gecko
|
||||||
|
efm32wg???f64 efm32gg ROM=64K RAM=32K
|
||||||
|
efm32wg???f128 efm32gg ROM=128K RAM=32K
|
||||||
|
efm32wg???f256 efm32gg ROM=256K RAM=32K
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# the TI cortex M3 chips
|
||||||
|
|
||||||
|
lm3s101 lm3sandstorm ROM=8K RAM=2K
|
||||||
|
lm3s102 lm3sandstorm ROM=8K RAM=2K
|
||||||
|
|
||||||
|
lm3s300 lm3sandstorm ROM=16K RAM=4K
|
||||||
|
lm3s301 lm3sandstorm ROM=16K RAM=2K
|
||||||
|
lm3s308 lm3sandstorm ROM=16K RAM=4K
|
||||||
|
lm3s310 lm3sandstorm ROM=16K RAM=4K
|
||||||
|
lm3s315 lm3sandstorm ROM=16K RAM=4K
|
||||||
|
lm3s316 lm3sandstorm ROM=16K RAM=4K
|
||||||
|
lm3s317 lm3sandstorm ROM=16K RAM=4K
|
||||||
|
lm3s328 lm3sandstorm ROM=16K RAM=4K
|
||||||
|
lm3s600 lm3sandstorm ROM=32K RAM=8K
|
||||||
|
lm3s601 lm3sandstorm ROM=32K RAM=8K
|
||||||
|
lm3s608 lm3sandstorm ROM=32K RAM=8K
|
||||||
|
lm3s610 lm3sandstorm ROM=32K RAM=8K
|
||||||
|
lm3s611 lm3sandstorm ROM=32K RAM=8K
|
||||||
|
lm3s612 lm3sandstorm ROM=32K RAM=8K
|
||||||
|
lm3s613 lm3sandstorm ROM=32K RAM=8K
|
||||||
|
lm3s615 lm3sandstorm ROM=32K RAM=8K
|
||||||
|
lm3s617 lm3sandstorm ROM=32K RAM=8K
|
||||||
|
lm3s618 lm3sandstorm ROM=32K RAM=8K
|
||||||
|
lm3s628 lm3sandstorm ROM=32K RAM=8K
|
||||||
|
lm3s800 lm3sandstorm ROM=64K RAM=8K
|
||||||
|
lm3s801 lm3sandstorm ROM=64K RAM=8K
|
||||||
|
lm3s808 lm3sandstorm ROM=64K RAM=8K
|
||||||
|
lm3s811 lm3sandstorm ROM=64K RAM=8K
|
||||||
|
lm3s812 lm3sandstorm ROM=64K RAM=8K
|
||||||
|
lm3s815 lm3sandstorm ROM=64K RAM=8K
|
||||||
|
lm3s817 lm3sandstorm ROM=64K RAM=8K
|
||||||
|
lm3s818 lm3sandstorm ROM=64K RAM=8K
|
||||||
|
lm3s828 lm3sandstorm ROM=64K RAM=8K
|
||||||
|
|
||||||
|
lm3s1110 lm3fury ROM=64K RAM=16K
|
||||||
|
lm3s1133 lm3fury ROM=64K RAM=16K
|
||||||
|
lm3s1138 lm3fury ROM=64K RAM=16K
|
||||||
|
lm3s1150 lm3fury ROM=64K RAM=16K
|
||||||
|
lm3s1162 lm3fury ROM=64K RAM=16K
|
||||||
|
lm3s1165 lm3fury ROM=64K RAM=16K
|
||||||
|
lm3s1332 lm3fury ROM=96K RAM=16K
|
||||||
|
lm3s1435 lm3fury ROM=96K RAM=32K
|
||||||
|
lm3s1439 lm3fury ROM=96K RAM=32K
|
||||||
|
lm3s1512 lm3fury ROM=96K RAM=64K
|
||||||
|
lm3s1538 lm3fury ROM=96K RAM=64K
|
||||||
|
lm3s1601 lm3fury ROM=128K RAM=32K
|
||||||
|
lm3s1607 lm3fury ROM=128K RAM=32K
|
||||||
|
lm3s1608 lm3fury ROM=128K RAM=32K
|
||||||
|
lm3s1620 lm3fury ROM=128K RAM=32K
|
||||||
|
lm3s8962 lm3fury ROM=256K RAM=64K
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# the TI cortex R4F chips
|
||||||
|
|
||||||
|
rm46l852* rm46l ROM=1280K RAM=192K
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
################################################################################
|
||||||
|
################################################################################
|
||||||
|
# the STM32 family groups
|
||||||
|
|
||||||
|
stm32f3ccm stm32f3 CCM_OFF=0x10000000
|
||||||
|
stm32f4ccm stm32f4 CCM_OFF=0x10000000
|
||||||
|
stm32l1eep stm32l1 EEP_OFF=0x08080000
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# the SAM3 family groups
|
||||||
|
sam3xnfc sam3x NFCRAM=4K NFCRAM_OFF=0x20100000
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# the lpc family groups
|
||||||
|
|
||||||
|
|
||||||
|
lpc13u lpc13 USBRAM_OFF=0x20004000
|
||||||
|
|
||||||
|
lpc17[56]x lpc17 RAM1_OFF=0x2007C000 RAM2_OFF=0x20080000
|
||||||
|
lpc17[78]x lpc17 RAM1_OFF=0x20000000 RAM2_OFF=0x20040000
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
################################################################################
|
||||||
|
################################################################################
|
||||||
|
# the STM32 families
|
||||||
|
|
||||||
|
stm32f0 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m0 -mthumb -DSTM32F0 -lopencm3_stm32f0 -msoft-float
|
||||||
|
stm32f1 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb -DSTM32F1 -lopencm3_stm32f1 -msoft-float
|
||||||
|
stm32f2 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb -DSTM32F2 -lopencm3_stm32f2 -msoft-float
|
||||||
|
stm32f3 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m4 -mthumb -DSTM32F3 -lopencm3_stm32f3 -mfloat-abi=hard -mfpu=fpv4-sp-d16
|
||||||
|
stm32f4 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m4 -mthumb -DSTM32F4 -lopencm3_stm32f4 -mfloat-abi=hard -mfpu=fpv4-sp-d16
|
||||||
|
stm32l0 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m0 -mthumb -DSTM32L0 -lopencm3_stm32l0 -msoft-float
|
||||||
|
stm32l1 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb -DSTM32L1 -lopencm3_stm32l1 -msoft-float
|
||||||
|
stm32w stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb
|
||||||
|
stm32t stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# the SAM3 families
|
||||||
|
|
||||||
|
sam3a sam3 ROM_OFF=0x00080000 RAM_OFF=0x20000000 RAM1_OFF=0x20080000
|
||||||
|
sam3n sam3 ROM_OFF=0x00400000 RAM_OFF=0x20000000
|
||||||
|
sam3s sam3 ROM_OFF=0x00400000 RAM_OFF=0x20000000
|
||||||
|
sam3u sam3 ROM_OFF=0x00080000 RAM_OFF=0x20000000 RAM1_OFF=0x20080000 NFCRAM=4K NFCRAM_OFF=0x20100000
|
||||||
|
sam3x sam3 ROM_OFF=0x00080000 RAM_OFF=0x20000000 RAM1_OFF=0x20080000
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# the lpc families
|
||||||
|
|
||||||
|
lpc13 lpc ROM_OFF=0x00000000 RAM_OFF=0x10000000 RAM1_OFF=0x20000000
|
||||||
|
lpc17 lpc ROM_OFF=0x00000000 RAM_OFF=0x10000000
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# the efm32 Gecko families
|
||||||
|
|
||||||
|
efm32zg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
|
||||||
|
efm32tg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
|
||||||
|
efm32g efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
|
||||||
|
efm32lg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
|
||||||
|
efm32gg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
|
||||||
|
efm32wg efm32 ROM_OFF=0x00000000 RAM_OFF=0x20000000 RAM1_OFF=0x10000000
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# Cortex LM3 families
|
||||||
|
|
||||||
|
lm3fury lm3 ROM_OFF=0x00000000 RAM_OFF=0x20000000
|
||||||
|
lm3sandstorm lm3 ROM_OFF=0x00000000 RAM_OFF=0x20000000
|
||||||
|
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
# Cortex R4F families
|
||||||
|
|
||||||
|
rm46l rm4 ROM_OFF=0x00000000 RAM_OFF=0x08000000 RAM1_OFF=0x08400000
|
||||||
|
|
||||||
|
################################################################################
|
||||||
|
################################################################################
|
||||||
|
################################################################################
|
||||||
|
# the architectures
|
||||||
|
|
||||||
|
stm32 END
|
||||||
|
sam3 END
|
||||||
|
lpc END
|
||||||
|
efm32 END
|
||||||
|
lm3 END
|
||||||
|
rm4 END
|
||||||
|
|
||||||
110
F4:F401/inc/ld/stm32f4.ld
Normal file
110
F4:F401/inc/ld/stm32f4.ld
Normal file
@ -0,0 +1,110 @@
|
|||||||
|
/*
|
||||||
|
********************************************************************************
|
||||||
|
* *
|
||||||
|
* Copyright (c) 2017 Andrea Loi *
|
||||||
|
* *
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a *
|
||||||
|
* copy of this software and associated documentation files (the "Software"), *
|
||||||
|
* to deal in the Software without restriction, including without limitation *
|
||||||
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
|
||||||
|
* and/or sell copies of the Software, and to permit persons to whom the *
|
||||||
|
* Software is furnished to do so, subject to the following conditions: *
|
||||||
|
* *
|
||||||
|
* The above copyright notice and this permission notice shall be included *
|
||||||
|
* in all copies or substantial portions of the Software. *
|
||||||
|
* *
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
|
||||||
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
|
||||||
|
* DEALINGS IN THE SOFTWARE. *
|
||||||
|
* *
|
||||||
|
********************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* DON'T EDIT THIS FILE UNLESS YOU KNOW WHAT YOU'RE DOING! */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/* _isrvectors_tend = 0x00000150; - different for different series */
|
||||||
|
|
||||||
|
ENTRY(reset_handler)
|
||||||
|
|
||||||
|
SECTIONS {
|
||||||
|
.vector_table 0x08000000 :
|
||||||
|
{
|
||||||
|
_sisrvectors = .;
|
||||||
|
KEEP(*(.vector_table))
|
||||||
|
/* ASSERT(. == _isrvectors_tend, "The vector table needs to be 84 elements long!"); */
|
||||||
|
_eisrvectors = .;
|
||||||
|
} >rom
|
||||||
|
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_stext = .;
|
||||||
|
*(.text*)
|
||||||
|
*(.rodata*)
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .;
|
||||||
|
} >rom
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >rom
|
||||||
|
|
||||||
|
.ARM : {
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
} >rom
|
||||||
|
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .;
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .;
|
||||||
|
} >ram AT >rom
|
||||||
|
|
||||||
|
.myvars :
|
||||||
|
{
|
||||||
|
. = ALIGN(2048);
|
||||||
|
__varsstart = ABSOLUTE(.);
|
||||||
|
KEEP(*(.myvars))
|
||||||
|
} > rom
|
||||||
|
|
||||||
|
_ldata = LOADADDR(.data);
|
||||||
|
|
||||||
|
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sbss = .;
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .;
|
||||||
|
} >ram
|
||||||
|
|
||||||
|
.ccmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sccmram = .;
|
||||||
|
*(.ccmram)
|
||||||
|
*(.ccmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_eccmram = .;
|
||||||
|
} >ccmram
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
|
||||||
31
F4:F401/inc/ld/stm32f407xg.ld
Normal file
31
F4:F401/inc/ld/stm32f407xg.ld
Normal file
@ -0,0 +1,31 @@
|
|||||||
|
/*
|
||||||
|
* This file is part of the libopencm3 project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
|
||||||
|
*
|
||||||
|
* This library is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This library is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU Lesser General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU Lesser General Public License
|
||||||
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
|
||||||
|
|
||||||
|
/* Define memory regions. */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||||
|
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
ccmram (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Include the common ld script. */
|
||||||
|
INCLUDE stm32f4.ld
|
||||||
1257
F4:F401/inc/startup/vector.c
Normal file
1257
F4:F401/inc/startup/vector.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,194 +0,0 @@
|
|||||||
#include "stm32f411xe.h"
|
|
||||||
#include <stddef.h>
|
|
||||||
|
|
||||||
void SystemInit();
|
|
||||||
void __libc_init_array();
|
|
||||||
int main();
|
|
||||||
|
|
||||||
// These magic symbols are provided by the linker.
|
|
||||||
extern void *_estack;
|
|
||||||
extern void *_sidata, *_sdata, *_edata;
|
|
||||||
extern void *_sbss, *_ebss;
|
|
||||||
extern void (*__preinit_array_start[]) (void) __attribute__((weak));
|
|
||||||
extern void (*__preinit_array_end[]) (void) __attribute__((weak));
|
|
||||||
extern void (*__init_array_start[]) (void) __attribute__((weak));
|
|
||||||
extern void (*__init_array_end[]) (void) __attribute__((weak));
|
|
||||||
extern void (*__fini_array_start[]) (void) __attribute__((weak));
|
|
||||||
extern void (*__fini_array_end[]) (void) __attribute__((weak));
|
|
||||||
|
|
||||||
void __attribute__((naked, noreturn)) Reset_Handler()
|
|
||||||
{
|
|
||||||
#ifdef __DEBUG_SRAM__
|
|
||||||
__set_MSP((uint32_t)&_estack);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
SystemInit();
|
|
||||||
|
|
||||||
for (void **pSrc = &_sidata, **pDst = &_sdata; pDst < &_edata; *pDst++ = *pSrc++);
|
|
||||||
for (void **pDst = &_sbss; pDst < &_ebss; *pDst++ = 0); // Zero -> BSS
|
|
||||||
|
|
||||||
// Use with the "-nostartfiles" linker option instead __libc_init_array();
|
|
||||||
// Iterate over all the preinit/init routines (mainly static constructors).
|
|
||||||
for(void(**fConstr)() = __preinit_array_start; fConstr < __preinit_array_end; (*fConstr++)());
|
|
||||||
for(void(**fConstr)() = __init_array_start; fConstr < __init_array_end; (*fConstr++)());
|
|
||||||
|
|
||||||
//__libc_init_array(); // Use with libc start files
|
|
||||||
|
|
||||||
(void)main();
|
|
||||||
}
|
|
||||||
|
|
||||||
void Default_Handler() { for(;;); }
|
|
||||||
|
|
||||||
void NMI_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void HardFault_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void MemManage_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void BusFault_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void UsageFault_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SVC_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DebugMon_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void PendSV_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SysTick_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void WWDG_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void PVD_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TAMP_STAMP_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void RTC_WKUP_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void FLASH_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void RCC_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI0_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI1_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI4_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Stream0_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Stream1_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Stream2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Stream3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Stream4_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Stream5_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Stream6_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void ADC_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI9_5_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM1_BRK_TIM9_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM1_UP_TIM10_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM1_TRG_COM_TIM11_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM1_CC_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM4_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void I2C1_EV_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void I2C1_ER_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void I2C2_EV_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void I2C2_ER_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SPI1_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SPI2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USART1_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USART2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI15_10_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void RTC_Alarm_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void OTG_FS_WKUP_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Stream7_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SDIO_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM5_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SPI3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Stream0_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Stream1_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Stream2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Stream3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Stream4_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void OTG_FS_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Stream5_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Stream6_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Stream7_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USART6_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void I2C3_EV_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void I2C3_ER_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void FPU_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SPI4_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SPI5_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
|
|
||||||
|
|
||||||
typedef void(*intvec_elem)();
|
|
||||||
|
|
||||||
__EXTERN_C const intvec_elem __vector_table[] __VECTOR_TABLE_ATTRIBUTE =
|
|
||||||
{ (intvec_elem)&_estack, &Reset_Handler,
|
|
||||||
&NMI_Handler,
|
|
||||||
&HardFault_Handler,
|
|
||||||
&MemManage_Handler,
|
|
||||||
&BusFault_Handler,
|
|
||||||
&UsageFault_Handler,
|
|
||||||
NULL, NULL, NULL, NULL,
|
|
||||||
&SVC_Handler,
|
|
||||||
&DebugMon_Handler,
|
|
||||||
NULL,
|
|
||||||
&PendSV_Handler,
|
|
||||||
&SysTick_Handler,
|
|
||||||
&WWDG_IRQHandler,
|
|
||||||
&PVD_IRQHandler,
|
|
||||||
&TAMP_STAMP_IRQHandler,
|
|
||||||
&RTC_WKUP_IRQHandler,
|
|
||||||
&FLASH_IRQHandler,
|
|
||||||
&RCC_IRQHandler,
|
|
||||||
&EXTI0_IRQHandler,
|
|
||||||
&EXTI1_IRQHandler,
|
|
||||||
&EXTI2_IRQHandler,
|
|
||||||
&EXTI3_IRQHandler,
|
|
||||||
&EXTI4_IRQHandler,
|
|
||||||
&DMA1_Stream0_IRQHandler,
|
|
||||||
&DMA1_Stream1_IRQHandler,
|
|
||||||
&DMA1_Stream2_IRQHandler,
|
|
||||||
&DMA1_Stream3_IRQHandler,
|
|
||||||
&DMA1_Stream4_IRQHandler,
|
|
||||||
&DMA1_Stream5_IRQHandler,
|
|
||||||
&DMA1_Stream6_IRQHandler,
|
|
||||||
&ADC_IRQHandler,
|
|
||||||
NULL, NULL, NULL, NULL,
|
|
||||||
&EXTI9_5_IRQHandler,
|
|
||||||
&TIM1_BRK_TIM9_IRQHandler,
|
|
||||||
&TIM1_UP_TIM10_IRQHandler,
|
|
||||||
&TIM1_TRG_COM_TIM11_IRQHandler,
|
|
||||||
&TIM1_CC_IRQHandler,
|
|
||||||
&TIM2_IRQHandler,
|
|
||||||
&TIM3_IRQHandler,
|
|
||||||
&TIM4_IRQHandler,
|
|
||||||
&I2C1_EV_IRQHandler,
|
|
||||||
&I2C1_ER_IRQHandler,
|
|
||||||
&I2C2_EV_IRQHandler,
|
|
||||||
&I2C2_ER_IRQHandler,
|
|
||||||
&SPI1_IRQHandler,
|
|
||||||
&SPI2_IRQHandler,
|
|
||||||
&USART1_IRQHandler,
|
|
||||||
&USART2_IRQHandler,
|
|
||||||
NULL,
|
|
||||||
&EXTI15_10_IRQHandler,
|
|
||||||
&RTC_Alarm_IRQHandler,
|
|
||||||
&OTG_FS_WKUP_IRQHandler,
|
|
||||||
NULL, NULL, NULL, NULL,
|
|
||||||
&DMA1_Stream7_IRQHandler,
|
|
||||||
NULL,
|
|
||||||
&SDIO_IRQHandler,
|
|
||||||
&TIM5_IRQHandler,
|
|
||||||
&SPI3_IRQHandler,
|
|
||||||
NULL, NULL, NULL, NULL,
|
|
||||||
&DMA2_Stream0_IRQHandler,
|
|
||||||
&DMA2_Stream1_IRQHandler,
|
|
||||||
&DMA2_Stream2_IRQHandler,
|
|
||||||
&DMA2_Stream3_IRQHandler,
|
|
||||||
&DMA2_Stream4_IRQHandler,
|
|
||||||
NULL, NULL, NULL, NULL, NULL, NULL,
|
|
||||||
&OTG_FS_IRQHandler,
|
|
||||||
&DMA2_Stream5_IRQHandler,
|
|
||||||
&DMA2_Stream6_IRQHandler,
|
|
||||||
&DMA2_Stream7_IRQHandler,
|
|
||||||
&USART6_IRQHandler,
|
|
||||||
&I2C3_EV_IRQHandler,
|
|
||||||
&I2C3_ER_IRQHandler,
|
|
||||||
NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
|
||||||
&FPU_IRQHandler,
|
|
||||||
NULL, NULL,
|
|
||||||
&SPI4_IRQHandler,
|
|
||||||
&SPI5_IRQHandler,
|
|
||||||
};
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
@ -1,267 +0,0 @@
|
|||||||
// STM32F303 Startup file
|
|
||||||
// IAR, GCC, Keil compatible
|
|
||||||
|
|
||||||
#include "stm32f303xc.h"
|
|
||||||
#include <stddef.h>
|
|
||||||
|
|
||||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION>=6100100)
|
|
||||||
#define __KEIL_CODE__
|
|
||||||
#elif defined(__GNUC__)
|
|
||||||
#define __GCC_CODE__
|
|
||||||
#elif defined(__ICCARM__)
|
|
||||||
#define __IAR_CODE__
|
|
||||||
#elif defined( __CC_ARM ) || defined(__MICROLIB)
|
|
||||||
#error "ARMCC v5 and MICROLIB not supported"
|
|
||||||
#else
|
|
||||||
#error "Can't detect compiler"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
#define __EXTERN_C extern "C"
|
|
||||||
extern "C" {
|
|
||||||
#else
|
|
||||||
#define __EXTERN_C
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef __IAR_CODE__
|
|
||||||
//------------------------------
|
|
||||||
// IAR startup code
|
|
||||||
//------------------------------
|
|
||||||
#define __Reset_Handler __cmain
|
|
||||||
#pragma segment="CSTACK"
|
|
||||||
#define __STACK_TOP ((uint32_t)__sfe( "CSTACK" ))
|
|
||||||
void exit(){}
|
|
||||||
void __exit(){}
|
|
||||||
void abort(){}
|
|
||||||
void __cmain();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef __KEIL_CODE__
|
|
||||||
//------------------------------
|
|
||||||
// Keil startup code
|
|
||||||
//------------------------------
|
|
||||||
void __main();
|
|
||||||
void SystemInit();
|
|
||||||
void exit() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
#define __Reset_Handler Reset_Handler
|
|
||||||
#define __STACK_TOP (void *)&Image$$ARM_LIB_STACK$$ZI$$Limit
|
|
||||||
extern int Image$$ARM_LIB_STACK$$ZI$$Limit;
|
|
||||||
|
|
||||||
void Reset_Handler()
|
|
||||||
{
|
|
||||||
SystemInit();
|
|
||||||
__main();
|
|
||||||
}
|
|
||||||
#endif // __KEIL_CODE__
|
|
||||||
|
|
||||||
#ifdef __GCC_CODE__
|
|
||||||
//------------------------------
|
|
||||||
// GCC Newlib startup code
|
|
||||||
//------------------------------
|
|
||||||
#define __Reset_Handler Reset_Handler
|
|
||||||
#define __STACK_TOP &_estack
|
|
||||||
void SystemInit();
|
|
||||||
void __libc_init_array();
|
|
||||||
int main();
|
|
||||||
|
|
||||||
// These magic symbols are provided by the linker.
|
|
||||||
extern void *_estack;
|
|
||||||
extern void *_sidata, *_sdata, *_edata;
|
|
||||||
extern void *_sbss, *_ebss;
|
|
||||||
extern void (*__preinit_array_start[]) (void) __attribute__((weak));
|
|
||||||
extern void (*__preinit_array_end[]) (void) __attribute__((weak));
|
|
||||||
extern void (*__init_array_start[]) (void) __attribute__((weak));
|
|
||||||
extern void (*__init_array_end[]) (void) __attribute__((weak));
|
|
||||||
extern void (*__fini_array_start[]) (void) __attribute__((weak));
|
|
||||||
extern void (*__fini_array_end[]) (void) __attribute__((weak));
|
|
||||||
|
|
||||||
void __attribute__((naked, noreturn)) Reset_Handler()
|
|
||||||
{
|
|
||||||
#ifdef __DEBUG_SRAM__
|
|
||||||
__set_MSP((uint32_t)&_estack);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
SystemInit();
|
|
||||||
|
|
||||||
for (void **pSrc = &_sidata, **pDst = &_sdata; pDst < &_edata; *pDst++ = *pSrc++);
|
|
||||||
for (void **pDst = &_sbss; pDst < &_ebss; *pDst++ = 0); // Zero -> BSS
|
|
||||||
|
|
||||||
// Use with the "-nostartfiles" linker option instead __libc_init_array();
|
|
||||||
// Iterate over all the preinit/init routines (mainly static constructors).
|
|
||||||
for(void(**fConstr)() = __preinit_array_start; fConstr < __preinit_array_end; (*fConstr++)());
|
|
||||||
for(void(**fConstr)() = __init_array_start; fConstr < __init_array_end; (*fConstr++)());
|
|
||||||
|
|
||||||
//__libc_init_array(); // Use with libc start files
|
|
||||||
|
|
||||||
(void)main();
|
|
||||||
}
|
|
||||||
#endif // __GCC_CODE__
|
|
||||||
|
|
||||||
void Default_Handler() { for(;;); }
|
|
||||||
|
|
||||||
void NMI_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void HardFault_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void MemManage_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void BusFault_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void UsageFault_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SVC_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DebugMon_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void PendSV_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SysTick_Handler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void WWDG_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void PVD_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TAMP_STAMP_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void RTC_WKUP_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void FLASH_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void RCC_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI0_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI1_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI2_TSC_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI4_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Channel1_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Channel2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Channel3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Channel4_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Channel5_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Channel6_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA1_Channel7_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void ADC1_2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USB_HP_CAN_TX_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USB_LP_CAN_RX0_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void CAN_RX1_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void CAN_SCE_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI9_5_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM1_BRK_TIM15_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM1_UP_TIM16_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM1_TRG_COM_TIM17_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM1_CC_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM4_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void I2C1_EV_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void I2C1_ER_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void I2C2_EV_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void I2C2_ER_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SPI1_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SPI2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USART1_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USART2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USART3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void EXTI15_10_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void RTC_Alarm_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USBWakeUp_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM8_BRK_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM8_UP_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM8_TRG_COM_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM8_CC_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void ADC3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void SPI3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void UART4_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void UART5_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM6_DAC_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void TIM7_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Channel1_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Channel2_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Channel3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Channel4_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void DMA2_Channel5_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void ADC4_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void COMP1_2_3_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void COMP4_5_6_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void COMP7_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USB_HP_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USB_LP_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void USBWakeUp_RMP_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
void FPU_IRQHandler() __attribute__ ((weak, alias ("Default_Handler")));
|
|
||||||
|
|
||||||
typedef void(*intvec_elem)();
|
|
||||||
|
|
||||||
__EXTERN_C const intvec_elem __vector_table[] __VECTOR_TABLE_ATTRIBUTE =
|
|
||||||
{ (intvec_elem)__STACK_TOP, &__Reset_Handler,
|
|
||||||
&NMI_Handler,
|
|
||||||
&HardFault_Handler,
|
|
||||||
&MemManage_Handler,
|
|
||||||
&BusFault_Handler,
|
|
||||||
&UsageFault_Handler,
|
|
||||||
NULL, NULL, NULL, NULL,
|
|
||||||
&SVC_Handler,
|
|
||||||
&DebugMon_Handler,
|
|
||||||
NULL,
|
|
||||||
&PendSV_Handler,
|
|
||||||
&SysTick_Handler,
|
|
||||||
&WWDG_IRQHandler,
|
|
||||||
&PVD_IRQHandler,
|
|
||||||
&TAMP_STAMP_IRQHandler,
|
|
||||||
&RTC_WKUP_IRQHandler,
|
|
||||||
&FLASH_IRQHandler,
|
|
||||||
&RCC_IRQHandler,
|
|
||||||
&EXTI0_IRQHandler,
|
|
||||||
&EXTI1_IRQHandler,
|
|
||||||
&EXTI2_TSC_IRQHandler,
|
|
||||||
&EXTI3_IRQHandler,
|
|
||||||
&EXTI4_IRQHandler,
|
|
||||||
&DMA1_Channel1_IRQHandler,
|
|
||||||
&DMA1_Channel2_IRQHandler,
|
|
||||||
&DMA1_Channel3_IRQHandler,
|
|
||||||
&DMA1_Channel4_IRQHandler,
|
|
||||||
&DMA1_Channel5_IRQHandler,
|
|
||||||
&DMA1_Channel6_IRQHandler,
|
|
||||||
&DMA1_Channel7_IRQHandler,
|
|
||||||
&ADC1_2_IRQHandler,
|
|
||||||
&USB_HP_CAN_TX_IRQHandler,
|
|
||||||
&USB_LP_CAN_RX0_IRQHandler,
|
|
||||||
&CAN_RX1_IRQHandler,
|
|
||||||
&CAN_SCE_IRQHandler,
|
|
||||||
&EXTI9_5_IRQHandler,
|
|
||||||
&TIM1_BRK_TIM15_IRQHandler,
|
|
||||||
&TIM1_UP_TIM16_IRQHandler,
|
|
||||||
&TIM1_TRG_COM_TIM17_IRQHandler,
|
|
||||||
&TIM1_CC_IRQHandler,
|
|
||||||
&TIM2_IRQHandler,
|
|
||||||
&TIM3_IRQHandler,
|
|
||||||
&TIM4_IRQHandler,
|
|
||||||
&I2C1_EV_IRQHandler,
|
|
||||||
&I2C1_ER_IRQHandler,
|
|
||||||
&I2C2_EV_IRQHandler,
|
|
||||||
&I2C2_ER_IRQHandler,
|
|
||||||
&SPI1_IRQHandler,
|
|
||||||
&SPI2_IRQHandler,
|
|
||||||
&USART1_IRQHandler,
|
|
||||||
&USART2_IRQHandler,
|
|
||||||
&USART3_IRQHandler,
|
|
||||||
&EXTI15_10_IRQHandler,
|
|
||||||
&RTC_Alarm_IRQHandler,
|
|
||||||
&USBWakeUp_IRQHandler,
|
|
||||||
&TIM8_BRK_IRQHandler,
|
|
||||||
&TIM8_UP_IRQHandler,
|
|
||||||
&TIM8_TRG_COM_IRQHandler,
|
|
||||||
&TIM8_CC_IRQHandler,
|
|
||||||
&ADC3_IRQHandler,
|
|
||||||
NULL, NULL, NULL,
|
|
||||||
&SPI3_IRQHandler,
|
|
||||||
&UART4_IRQHandler,
|
|
||||||
&UART5_IRQHandler,
|
|
||||||
&TIM6_DAC_IRQHandler,
|
|
||||||
&TIM7_IRQHandler,
|
|
||||||
&DMA2_Channel1_IRQHandler,
|
|
||||||
&DMA2_Channel2_IRQHandler,
|
|
||||||
&DMA2_Channel3_IRQHandler,
|
|
||||||
&DMA2_Channel4_IRQHandler,
|
|
||||||
&DMA2_Channel5_IRQHandler,
|
|
||||||
&ADC4_IRQHandler,
|
|
||||||
NULL, NULL,
|
|
||||||
&COMP1_2_3_IRQHandler,
|
|
||||||
&COMP4_5_6_IRQHandler,
|
|
||||||
&COMP7_IRQHandler,
|
|
||||||
NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
|
||||||
&USB_HP_IRQHandler,
|
|
||||||
&USB_LP_IRQHandler,
|
|
||||||
&USBWakeUp_RMP_IRQHandler,
|
|
||||||
NULL, NULL, NULL, NULL,
|
|
||||||
&FPU_IRQHandler
|
|
||||||
};
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
Loading…
x
Reference in New Issue
Block a user