mirror of
https://github.com/eddyem/stm32samples.git
synced 2026-02-28 20:04:30 +03:00
add simplest blink for STM32F407
This commit is contained in:
285
F4:F401/inc/Fx/stm32f4.h
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285
F4:F401/inc/Fx/stm32f4.h
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/*
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* This file is part of the stm32f4 project.
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* Copyright 2022 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include "vector.h"
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#ifdef STM32F407xx
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#include "stm32f407xx.h"
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#else
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#error "Define STM32F407xx"
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#endif
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#include "common_macros.h"
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// HSE=12MHz, fVCO=288MHz (PLL_M=12, PLL_N=288), HCLK=144MHz (PLL_P=2), fUSB=48MHz (PLL_Q=6)
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#ifndef PLL_M
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#define PLL_M 12
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#endif
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#ifndef PLL_N
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#define PLL_N 288
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#endif
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#ifndef PLL_P
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#define PLL_P 2
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#endif
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#ifndef PLL_Q
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#define PLL_Q 6
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#endif
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#ifndef VECT_TAB_OFFSET
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#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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#endif
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#if 0
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/**
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* @brief Setup the microcontroller system
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* Initialize the FPU setting, vector table location and the PLL configuration is reset.
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* @param None
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* @retval None
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*/
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TRUE_INLINE void sysreset(void) // not usable
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{
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= RCC_CR_HSION;
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/* Reset CFGR register */
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RCC->CFGR = 0;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &=(uint32_t)0xFEF6FFFF;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = (uint32_t)0x24003010;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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#endif
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#define WAITWHILE(x) do{StartUpCounter = 0; while((x) && (++StartUpCounter < 0xffffff)){} if(StartUpCounter == 0xffffff) return 0;}while(0)
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TRUE_INLINE int StartHSI(){ // HSI is 16MHz, so PLL_M=16, PLL_N=288, PLL_P=2, PLL_Q=6
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uint32_t StartUpCounter = 0;
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RCC->CR = (RCC->CR & ~RCC_CR_PLLON) | RCC_CR_HSION;
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WAITWHILE(!(RCC->CR & RCC_CR_HSIRDY));
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// Enable high performance mode (default after reset), System frequency up to 168 MHz, Vreg += 10%
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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PWR->CR |= PWR_CR_VOS;
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WAITWHILE(!(PWR->CSR & PWR_CSR_VOSRDY));
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// HCLK = SYSCLK, PCLK1 = HCLK/4, PCLK2 = HCLK/2
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RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2)
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) | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV2;
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/* Configure the main PLL */
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RCC->PLLCFGR = 16 | (288 << 6) | (6 << 24);
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RCC->CR |= RCC_CR_PLLON; // Enable PLL
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// Wait till PLL is ready
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WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
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/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
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// Select PLL as system clock source
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RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
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return 1;
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}
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// @return 1 if OK, 0 if failed
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TRUE_INLINE int StartHSE(){ // fVCO can be from 192 to 432MHz
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uint32_t StartUpCounter = 0;
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RCC->CR = (RCC->CR & ~RCC_CR_PLLON) | RCC_CR_HSEON; // disable PLL to reconfigure, enable HSE
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WAITWHILE(!(RCC->CR & RCC_CR_HSERDY));
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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// Enable high performance mode (default after reset), System frequency up to 168 MHz, Vreg += 10%
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PWR->CR |= PWR_CR_VOS;
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WAITWHILE(!(PWR->CSR & PWR_CSR_VOSRDY));
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// HCLK = SYSCLK, PCLK1 = HCLK/4, PCLK2 = HCLK/2
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RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2)
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) | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV2;
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/* Configure the main PLL */
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RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
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(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
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RCC->CR |= RCC_CR_PLLON; // Enable PLL
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// Wait till PLL is ready
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WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY));
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/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
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FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
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// Select PLL as system clock source
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RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
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return 1;
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}
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#undef WAITWHILE
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/******************* Bit definition for GPIO_MODER register *****************/
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// _AI - analog inpt, _O - general output, _AF - alternate function
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#define GPIO_MODER_MODER0_AI ((uint32_t)0x00000003)
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#define GPIO_MODER_MODER0_O ((uint32_t)0x00000001)
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#define GPIO_MODER_MODER0_AF ((uint32_t)0x00000002)
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#define GPIO_MODER_MODER1_AI ((uint32_t)0x0000000C)
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#define GPIO_MODER_MODER1_O ((uint32_t)0x00000004)
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#define GPIO_MODER_MODER1_AF ((uint32_t)0x00000008)
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#define GPIO_MODER_MODER2_AI ((uint32_t)0x00000030)
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#define GPIO_MODER_MODER2_O ((uint32_t)0x00000010)
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#define GPIO_MODER_MODER2_AF ((uint32_t)0x00000020)
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#define GPIO_MODER_MODER3_AI ((uint32_t)0x000000C0)
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#define GPIO_MODER_MODER3_O ((uint32_t)0x00000040)
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#define GPIO_MODER_MODER3_AF ((uint32_t)0x00000080)
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#define GPIO_MODER_MODER4_AI ((uint32_t)0x00000300)
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#define GPIO_MODER_MODER4_O ((uint32_t)0x00000100)
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#define GPIO_MODER_MODER4_AF ((uint32_t)0x00000200)
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#define GPIO_MODER_MODER5_AI ((uint32_t)0x00000C00)
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#define GPIO_MODER_MODER5_O ((uint32_t)0x00000400)
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#define GPIO_MODER_MODER5_AF ((uint32_t)0x00000800)
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#define GPIO_MODER_MODER6_AI ((uint32_t)0x00003000)
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#define GPIO_MODER_MODER6_O ((uint32_t)0x00001000)
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#define GPIO_MODER_MODER6_AF ((uint32_t)0x00002000)
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#define GPIO_MODER_MODER7_AI ((uint32_t)0x0000C000)
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#define GPIO_MODER_MODER7_O ((uint32_t)0x00004000)
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#define GPIO_MODER_MODER7_AF ((uint32_t)0x00008000)
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#define GPIO_MODER_MODER8_AI ((uint32_t)0x00030000)
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#define GPIO_MODER_MODER8_O ((uint32_t)0x00010000)
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#define GPIO_MODER_MODER8_AF ((uint32_t)0x00020000)
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#define GPIO_MODER_MODER9_AI ((uint32_t)0x000C0000)
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#define GPIO_MODER_MODER9_O ((uint32_t)0x00040000)
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#define GPIO_MODER_MODER9_AF ((uint32_t)0x00080000)
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#define GPIO_MODER_MODER10_AI ((uint32_t)0x00300000)
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#define GPIO_MODER_MODER10_O ((uint32_t)0x00100000)
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#define GPIO_MODER_MODER10_AF ((uint32_t)0x00200000)
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#define GPIO_MODER_MODER11_AI ((uint32_t)0x00C00000)
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#define GPIO_MODER_MODER11_O ((uint32_t)0x00400000)
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#define GPIO_MODER_MODER11_AF ((uint32_t)0x00800000)
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#define GPIO_MODER_MODER12_AI ((uint32_t)0x03000000)
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#define GPIO_MODER_MODER12_O ((uint32_t)0x01000000)
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#define GPIO_MODER_MODER12_AF ((uint32_t)0x02000000)
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#define GPIO_MODER_MODER13_AI ((uint32_t)0x0C000000)
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#define GPIO_MODER_MODER13_O ((uint32_t)0x04000000)
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#define GPIO_MODER_MODER13_AF ((uint32_t)0x08000000)
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#define GPIO_MODER_MODER14_AI ((uint32_t)0x30000000)
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#define GPIO_MODER_MODER14_O ((uint32_t)0x10000000)
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#define GPIO_MODER_MODER14_AF ((uint32_t)0x20000000)
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#define GPIO_MODER_MODER15_AI ((uint32_t)0xC0000000)
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#define GPIO_MODER_MODER15_O ((uint32_t)0x40000000)
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#define GPIO_MODER_MODER15_AF ((uint32_t)0x80000000)
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/******************* Bit definition for GPIO_PUPDR register *****************/
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// no/pullup/pulldown/reserved
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// for n in $(seq 0 15); do echo "#define GPIO_PUPDR${n}_PU ((uint32_t)(1<<$((n*2))))";
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// echo "#define GPIO_PUPDR${n}_PD ((uint32_t)(1<<$((n*2+1))))"; done
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// alt+select column -> delete
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#define GPIO_PUPDR0_PU ((uint32_t)(1<<0))
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#define GPIO_PUPDR0_PD ((uint32_t)(1<<1))
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#define GPIO_PUPDR1_PU ((uint32_t)(1<<2))
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#define GPIO_PUPDR1_PD ((uint32_t)(1<<3))
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#define GPIO_PUPDR2_PU ((uint32_t)(1<<4))
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#define GPIO_PUPDR2_PD ((uint32_t)(1<<5))
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#define GPIO_PUPDR3_PU ((uint32_t)(1<<6))
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#define GPIO_PUPDR3_PD ((uint32_t)(1<<7))
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#define GPIO_PUPDR4_PU ((uint32_t)(1<<8))
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#define GPIO_PUPDR4_PD ((uint32_t)(1<<9))
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#define GPIO_PUPDR5_PU ((uint32_t)(1<<10))
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#define GPIO_PUPDR5_PD ((uint32_t)(1<<11))
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#define GPIO_PUPDR6_PU ((uint32_t)(1<<12))
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#define GPIO_PUPDR6_PD ((uint32_t)(1<<13))
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#define GPIO_PUPDR7_PU ((uint32_t)(1<<14))
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#define GPIO_PUPDR7_PD ((uint32_t)(1<<15))
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#define GPIO_PUPDR8_PU ((uint32_t)(1<<16))
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#define GPIO_PUPDR8_PD ((uint32_t)(1<<17))
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#define GPIO_PUPDR9_PU ((uint32_t)(1<<18))
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#define GPIO_PUPDR9_PD ((uint32_t)(1<<19))
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#define GPIO_PUPDR10_PU ((uint32_t)(1<<20))
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#define GPIO_PUPDR10_PD ((uint32_t)(1<<21))
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#define GPIO_PUPDR11_PU ((uint32_t)(1<<22))
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#define GPIO_PUPDR11_PD ((uint32_t)(1<<23))
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#define GPIO_PUPDR12_PU ((uint32_t)(1<<24))
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#define GPIO_PUPDR12_PD ((uint32_t)(1<<25))
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#define GPIO_PUPDR13_PU ((uint32_t)(1<<26))
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#define GPIO_PUPDR13_PD ((uint32_t)(1<<27))
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#define GPIO_PUPDR14_PU ((uint32_t)(1<<28))
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#define GPIO_PUPDR14_PD ((uint32_t)(1<<29))
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#define GPIO_PUPDR15_PU ((uint32_t)(1<<30))
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#define GPIO_PUPDR15_PD ((uint32_t)(1<<31))
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// OSPEEDR
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// for n in $(seq 0 15); do echo "#define GPIO_OSPEEDR${n}_MED ((uint32_t)(1<<$((n*2))))";
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// echo "#define GPIO_OSPEEDR${n}_HIGH ((uint32_t)(3<<$((2*n))))"; done
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#define GPIO_OSPEEDR0_MED ((uint32_t)(1<<0))
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#define GPIO_OSPEEDR0_HIGH ((uint32_t)(3<<0))
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#define GPIO_OSPEEDR1_MED ((uint32_t)(1<<2))
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#define GPIO_OSPEEDR1_HIGH ((uint32_t)(3<<2))
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#define GPIO_OSPEEDR2_MED ((uint32_t)(1<<4))
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#define GPIO_OSPEEDR2_HIGH ((uint32_t)(3<<4))
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#define GPIO_OSPEEDR3_MED ((uint32_t)(1<<6))
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#define GPIO_OSPEEDR3_HIGH ((uint32_t)(3<<6))
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#define GPIO_OSPEEDR4_MED ((uint32_t)(1<<8))
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#define GPIO_OSPEEDR4_HIGH ((uint32_t)(3<<8))
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#define GPIO_OSPEEDR5_MED ((uint32_t)(1<<10))
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#define GPIO_OSPEEDR5_HIGH ((uint32_t)(3<<10))
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#define GPIO_OSPEEDR6_MED ((uint32_t)(1<<12))
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#define GPIO_OSPEEDR6_HIGH ((uint32_t)(3<<12))
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#define GPIO_OSPEEDR7_MED ((uint32_t)(1<<14))
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#define GPIO_OSPEEDR7_HIGH ((uint32_t)(3<<14))
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#define GPIO_OSPEEDR8_MED ((uint32_t)(1<<16))
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#define GPIO_OSPEEDR8_HIGH ((uint32_t)(3<<16))
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#define GPIO_OSPEEDR9_MED ((uint32_t)(1<<18))
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#define GPIO_OSPEEDR9_HIGH ((uint32_t)(3<<18))
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#define GPIO_OSPEEDR10_MED ((uint32_t)(1<<20))
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#define GPIO_OSPEEDR10_HIGH ((uint32_t)(3<<20))
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#define GPIO_OSPEEDR11_MED ((uint32_t)(1<<22))
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#define GPIO_OSPEEDR11_HIGH ((uint32_t)(3<<22))
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#define GPIO_OSPEEDR12_MED ((uint32_t)(1<<24))
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#define GPIO_OSPEEDR12_HIGH ((uint32_t)(3<<24))
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#define GPIO_OSPEEDR13_MED ((uint32_t)(1<<26))
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#define GPIO_OSPEEDR13_HIGH ((uint32_t)(3<<26))
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#define GPIO_OSPEEDR14_MED ((uint32_t)(1<<28))
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#define GPIO_OSPEEDR14_HIGH ((uint32_t)(3<<28))
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#define GPIO_OSPEEDR15_MED ((uint32_t)(1<<30))
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#define GPIO_OSPEEDR15_HIGH ((uint32_t)(3<<30))
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/************************* ADC *************************/
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/* inner termometer calibration values
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* Temp = (V30 - Vsense)/Avg_Slope + 30
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* Avg_Slope = (V30 - V110) / (110 - 30)
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*/
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#define TEMP110_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7C2))
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#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
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// VDDA_Actual = 3.3V * VREFINT_CAL / average vref value
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#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7BA))
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#define VDD_CALIB ((uint16_t) (330))
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#define VDD_APPLI ((uint16_t) (300))
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/************************* USART *************************/
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#define USART_CR2_ADD_SHIFT 24
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// set address/character match value
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#define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)
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/************************* IWDG *************************/
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#define IWDG_REFRESH (uint32_t)(0x0000AAAA)
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#define IWDG_WRITE_ACCESS (uint32_t)(0x00005555)
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#define IWDG_START (uint32_t)(0x0000CCCC)
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//#define do{}while(0)
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