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https://github.com/eddyem/stm32samples.git
synced 2026-02-28 11:54:30 +03:00
add simplest blink for STM32F407
This commit is contained in:
169
F4:F401/blink/Makefile
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169
F4:F401/blink/Makefile
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@@ -0,0 +1,169 @@
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BINARY = blink
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BOOTPORT ?= /dev/ttyUSB0
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BOOTSPEED ?= 115200
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# MCU FAMILY
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FAMILY ?= F4
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# MCU code
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MCU ?= F407xx
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# or __ARM_ARCH_7EM__
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ARMARCH = __ARM_ARCH_7M__=1
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# change this linking script depending on particular MCU model,
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LDSCRIPT ?= stm32f407xg.ld
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# debug
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#DEFS = -DEBUG
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INDEPENDENT_HEADERS=
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FP_FLAGS ?= -mfpu=fpv4-sp-d16 -mfloat-abi=hard -fsingle-precision-constant
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ASM_FLAGS ?= -mthumb -mcpu=cortex-m4 -mthumb-interwork -mlittle-endian -march=armv7e-m
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ARCH_FLAGS = $(ASM_FLAGS) $(FP_FLAGS) -D $(ARMARCH)
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# autoincremental version & build date
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VERSION_FILE = version.inc
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ifeq ($(shell test -e $(VERSION_FILE) && echo -n yes), yes)
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NEXTVER := $(shell expr $$(awk '/#define BUILD_NUMBER/' $(VERSION_FILE) | tr -cd "[0-9]") + 1)
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else
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NEXTVER := "1"
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endif
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BUILDDATE := $(shell date +%Y-%m-%d)
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###############################################################################
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# Executables
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#PREFIX ?= arm-none-eabi
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# gcc from arm web site
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PREFIX ?= /opt/bin/arm-none-eabi
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TOOLCHLIB ?= /opt/arm-none-eabi/lib
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RM := rm -f
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RMDIR := rmdir
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CC := $(PREFIX)-gcc
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# don't replace ld with gcc: the binary size would be much greater!!
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LD := $(PREFIX)-ld
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AR := $(PREFIX)-ar
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AS := $(PREFIX)-as
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SIZE := $(PREFIX)-size
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OBJCOPY := $(PREFIX)-objcopy
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OBJDUMP := $(PREFIX)-objdump
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GDB := $(PREFIX)-gdb
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STFLASH := $(shell which st-flash)
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STBOOT := $(shell which stm32flash)
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DFUUTIL := $(shell which dfu-util)
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###############################################################################
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# Source files
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OBJDIR := mk
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SRC := $(wildcard *.c)
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OBJS := $(addprefix $(OBJDIR)/, $(SRC:%.c=%.o))
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STARTUP := $(OBJDIR)/startup.o
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MAP := $(OBJDIR)/$(BINARY).map
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OBJS += $(STARTUP)
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# dependencies: we need them to recompile files if their headers-dependencies changed
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DEPS := $(OBJS:.o=.d)
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INC_DIR ?= ../inc
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INCLUDE := -I$(INC_DIR)/Fx -I$(INC_DIR)/cm
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LIB_DIR := $(INC_DIR)/ld
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###############################################################################
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# C flags
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CFLAGS += -g3 -gdwarf-2
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CFLAGS += -O2 -D__thumb2__=1 -MD
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CFLAGS += -Wall -Werror -Wextra -Wshadow
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CFLAGS += -fshort-enums -ffunction-sections -fdata-sections
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#CFLAGS += -fno-common -ffunction-sections -fdata-sections -fno-stack-protector
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CFLAGS += $(ARCH_FLAGS)
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###############################################################################
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# Linker flags
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#LDFLAGS += -nostartfiles --static -nostdlib -specs=nosys.specs -specs=nano.specs
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LDFLAGS += $(ARCH_FLAGS)
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LDFLAGS += -specs=nosys.specs -specs=nano.specs
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LDFLAGS += -L$(LIB_DIR)
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#LDFLAGS += -L$(TOOLCHLIB)
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LDFLAGS += -T$(LDSCRIPT)
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LDFLAGS += -Wl,-Map=$(MAP),--cref -Wl,--gc-sections
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###############################################################################
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# Used libraries
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#LDLIBS += -lc $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
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DEFS += -DSTM32$(FAMILY) -DSTM32$(MCU)
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ELF := $(OBJDIR)/$(BINARY).elf
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LIST := $(OBJDIR)/$(BINARY).list
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BIN := $(BINARY).bin
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HEX := $(BINARY).hex
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all: bin list size
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elf: $(ELF)
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bin: $(BIN)
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hex: $(HEX)
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list: $(LIST)
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ifneq ($(MAKECMDGOALS),clean)
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-include $(DEPS)
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endif
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$(OBJDIR):
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mkdir $(OBJDIR)
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$(STARTUP): $(INC_DIR)/startup/vector.c
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$(CC) $(CFLAGS) $(DEFS) $(INCLUDE) -o $@ -c $<
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$(VERSION_FILE): *.[ch]
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[ -f $(VERSION_FILE) ] || echo -e "#define BUILD_NUMBER \"0\"\n#define BUILD_DATE \"none\"" > $(VERSION_FILE)
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@echo " Generate version: $(NEXTVER) for date $(BUILDDATE)"
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@sed -i "s/#define BUILD_NUMBER.*/#define BUILD_NUMBER \"$(NEXTVER)\"/" $(VERSION_FILE)
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@sed -i "s/#define BUILD_DATE.*/#define BUILD_DATE \"$(BUILDDATE)\"/" $(VERSION_FILE)
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#$(OBJDIR)/proto.o: proto.c $(VERSION_FILE)
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$(OBJDIR)/%.o: %.c
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@echo " CC $<"
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$(CC) $(CFLAGS) $(DEFS) $(INCLUDE) -o $@ -c $<
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$(BIN): $(ELF)
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@echo " OBJCOPY $(BIN)"
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$(OBJCOPY) -Obinary $(ELF) $(BIN)
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$(HEX): $(ELF)
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@echo " OBJCOPY $(HEX)"
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$(OBJCOPY) -Oihex $(ELF) $(HEX)
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$(LIST): $(ELF)
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@echo " OBJDUMP $(LIST)"
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$(OBJDUMP) -S $(ELF) > $(LIST)
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$(ELF): $(OBJDIR) $(OBJS)
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@echo " LD $(ELF)"
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$(CC) $(LDFLAGS) $(OBJS) $(LDLIBS) -o $(ELF)
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size: $(ELF)
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$(SIZE) $(ELF)
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clean:
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@echo " CLEAN"
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$(RM) $(OBJS) $(DEPS) $(ELF) $(HEX) $(LIST) $(MAP)
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@rmdir $(OBJDIR) 2>/dev/null || true
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flash: $(BIN)
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@echo " FLASH $(BIN)"
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$(STFLASH) write $(BIN) 0x8000000
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boot: $(BIN)
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@echo " LOAD $(BIN) through bootloader"
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$(STBOOT) -b$(BOOTSPEED) $(BOOTPORT) -w $(BIN)
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dfuboot: $(BIN)
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@echo " LOAD $(BIN) THROUGH DFU"
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$(DFUUTIL) -a0 -D $(BIN) -s 0x08000000
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openocd:
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openocd -f openocd.cfg
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dbg:
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arm-none-eabi-gdb $(ELF) -ex 'target remote localhost:3333' -ex 'monitor reset halt'
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.PHONY: size clean flash boot dfuboot openocd dbg
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1
F4:F401/blink/Readme
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1
F4:F401/blink/Readme
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@@ -0,0 +1 @@
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Simple blink with LED on PC13 (Olimex E407 development board)
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BIN
F4:F401/blink/blink.bin
Executable file
BIN
F4:F401/blink/blink.bin
Executable file
Binary file not shown.
49
F4:F401/blink/blink.c
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49
F4:F401/blink/blink.c
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@@ -0,0 +1,49 @@
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/*
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* systick_blink.c
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*
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* Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <stm32f4.h>
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static volatile uint32_t blink_ctr = 0;
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void sys_tick_handler(void){
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++blink_ctr;
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}
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TRUE_INLINE void gpio_setup(void){
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOCEN;
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GPIOC->MODER = GPIO_MODER_MODER13_O;
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GPIOE->MODER = GPIO_MODER_MODER2_O;
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}
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int main(void){
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if(!StartHSE()) StartHSI();
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// system frequency is 144MHz
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SysTick_Config((uint32_t)144000); // 1ms
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gpio_setup();
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uint32_t ctr = blink_ctr;
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while(1){
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if(blink_ctr - ctr > 499){
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ctr = blink_ctr;
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pin_toggle(GPIOE, 1<<2);
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pin_toggle(GPIOC, 1<<13);
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}
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}
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}
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116
F4:F401/blink/openocd.cfg
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116
F4:F401/blink/openocd.cfg
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# script for stm32f4x family
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#
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# stm32 devices support both JTAG and SWD transports.
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#
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source [find interface/stlink-v2-1.cfg]
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32f4x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 32kB (Available RAM in smallest device STM32F410)
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x8000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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# See STM Document RM0090
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# Section 38.6.3 - corresponds to Cortex-M4 r0p1
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set _CPUTAPID 0x4ba00477
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} {
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set _CPUTAPID 0x2ba01477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME bs -irlen 5
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
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if { [info exists QUADSPI] && $QUADSPI } {
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set a [llength [flash list]]
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set _QSPINAME $_CHIPNAME.qspi
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flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
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}
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# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
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#
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# Since we may be running of an RC oscilator, we crank down the speed a
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# bit more to be on the safe side. Perhaps superstition, but if are
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# running off a crystal, we can run closer to the limit. Note
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# that there can be a pretty wide band where things are more or less stable.
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adapter speed 2000
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adapter srst delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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reset_config srst_nogate
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event examine-end {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
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mmw 0xE0042004 0x00000007 0
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# Stop watchdog counters during halt
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# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
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mmw 0xE0042008 0x00001800 0
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0xE0042004 0x00000020 0
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}
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$_TARGETNAME configure -event reset-init {
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# Configure PLL to boost clock to HSI x 4 (64 MHz)
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mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
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mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
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mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
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sleep 10 ;# Wait for PLL to lock
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mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
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mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
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# Boost JTAG frequency
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adapter speed 8000
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}
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$_TARGETNAME configure -event reset-start {
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# Reduce speed since CPU speed will slow down to 16MHz with the reset
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adapter speed 2000
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}
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