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https://github.com/eddyem/stm32samples.git
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add modbus (not tested yet)
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238
F1:F103/FX3U/modbusrtu.c
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238
F1:F103/FX3U/modbusrtu.c
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/*
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* This file is part of the fx3u project.
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* Copyright 2024 Edward V. Emelianov <edward.emelianoff@gmail.com>.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "modbusrtu.h"
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#include "flash.h"
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#include "strfunc.h"
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#ifdef EBUG
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#include "usart.h"
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#endif
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#include <stm32f1.h>
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#include <string.h> // memcpy
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static volatile int modbus_txrdy = 1;
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static volatile int idatalen[2] = {0,0}; // received data line length (including '\n')
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static volatile int modbus_rdy = 0 // received data ready
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,dlen = 0 // length of data (including '\n') in current buffer
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,bufovr = 0 // input buffer overfull
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;
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static int rbufno = 0, tbufno = 0; // current rbuf/tbuf numbers
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static uint8_t rbuf[2][MODBUSBUFSZI], tbuf[2][MODBUSBUFSZO]; // receive & transmit buffers
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static uint8_t *recvdata = NULL;
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#define packCRC(d, l) *((uint16_t*) &d[l])
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// calculate CRC for given data
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static uint16_t getCRC(uint8_t *data, int l){
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uint16_t crc = 0xFFFF;
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for(int pos = 0; pos < l; ++pos){
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crc ^= (uint16_t)data[pos];
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for(int i = 8; i; --i){
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if((crc & 1)){
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crc >>= 1;
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crc ^= 0xA001;
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}else crc >>= 1;
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}
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}
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// CRC have swapped bytes, so we can just send it as *((uint16_t*)&data[x]) = CRC
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return crc;
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}
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/**
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* return length of received data without CRC or -1 if buffer overflow or bad CRC
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*/
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int modbus_receive(uint8_t **packet){
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if(!modbus_rdy) return 0;
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if(bufovr){
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DBG("Modbus buffer overflow\n");
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bufovr = 0;
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modbus_rdy = 0;
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return -1;
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}
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*packet = recvdata;
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modbus_rdy = 0;
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int x = dlen - 2;
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dlen = 0;
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uint16_t chk = getCRC(recvdata, x);
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if(packCRC(recvdata, x) != chk){
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DBG("Bad CRC\n");
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return -1;
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}
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return x;
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}
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// send current tbuf
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static int senddata(int l){
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uint32_t tmout = 1600000;
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while(!modbus_txrdy){
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IWDG->KR = IWDG_REFRESH;
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if(--tmout == 0) return 0;
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}; // wait for previos buffer transmission
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modbus_txrdy = 0;
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DMA2_Channel5->CCR &= ~DMA_CCR_EN;
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DMA2_Channel5->CMAR = (uint32_t) tbuf[tbufno]; // mem
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DMA2_Channel5->CNDTR = l + 2; // + CRC
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DMA2_Channel5->CCR |= DMA_CCR_EN;
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tbufno = !tbufno;
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return l;
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}
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// transmit raw data with length l; amount of bytes (without CRC) sent
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int modbus_send(uint8_t *data, int l){
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if(l < 1) return 0;
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if(l > MODBUSBUFSZO - 2) return -1;
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memcpy(tbuf[tbufno], data, l);
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packCRC(tbuf[tbufno], l) = getCRC(data, l);
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return senddata(l);
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}
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// send request: return the same as modbus_receive()
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int modbus_send_request(modbus_request *r){
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uint8_t *curbuf = tbuf[tbufno];
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int n = 6;
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*curbuf++ = r->ID;
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*curbuf++ = r->Fcode;
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*curbuf++ = r->startreg >> 8; // H
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*curbuf++ = (uint8_t) r->startreg; // L
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*curbuf++ = r->regno >> 8; // H
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*curbuf = (uint8_t) r->regno; // L
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// if r->datalen == 0 - this is responce for request with fcode > 4
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if((r->Fcode == MC_WRITE_MUL_COILS || r->Fcode == MC_WRITE_MUL_REGS) && r->datalen){ // request with data
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*(++curbuf) = r->datalen;
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memcpy(curbuf, r->data, r->datalen);
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n += r->datalen;
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}
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return senddata(n);
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}
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// return -1 in case of error, 0 if no data received, 1 if got good packet
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int modbus_get_request(modbus_request* r){
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if(!r) return -1;
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uint8_t *pack;
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int l = modbus_receive(&pack);
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if(l < 1) return l;
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if(l < 6) return -1; // not a request
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// check "broadcasting" and common requests
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if(*pack && *pack != the_conf.modbusID) return 0; // alien request
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r->ID = *pack++;
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r->Fcode = *pack++;
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r->startreg = pack[0] << 8 | pack[1];
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r->regno = pack[2] << 8 | pack[3];
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if(l > 6){ // request with data
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if(r->Fcode != MC_WRITE_MUL_COILS && r->Fcode != MC_WRITE_MUL_REGS) return -1; // bad request
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r->datalen = pack[4];
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if(r->datalen > l-6) r->datalen = l-6; // fix if data bytes less than field
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r->data = pack + 5;
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}else{
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r->datalen = 0;
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r->data = NULL;
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}
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return 1;
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}
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// send responce: return the same as modbus_receive()
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int modbus_send_response(modbus_response *r){
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uint8_t *curbuf = tbuf[tbufno];
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int len = 3; // packet data length without CRC
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*curbuf++ = r->ID;
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*curbuf++ = r->Fcode;
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*curbuf++ = r->datalen;
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if(0 == (r->Fcode & MODBUS_RESPONSE_ERRMARK)){ // data
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len += r->datalen;
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if(len > MODBUSBUFSZO - 2) return -1; // too much data
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memcpy(curbuf, r->data, r->datalen);
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}
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return senddata(len);
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}
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// get recponce; warning: all data is a pointer to last rbuf, it could be corrupted after next reading
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int modbus_get_response(modbus_response* r){
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if(!r) return -1;
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uint8_t *pack;
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int l = modbus_receive(&pack);
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if(l < 1) return l;
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if(l < 3) return -1; // not a responce
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r->ID = *pack++;
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r->Fcode = *pack++;
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r->datalen = *pack++;
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// error
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if(r->Fcode & MODBUS_RESPONSE_ERRMARK) r->data = NULL;
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else{
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// wrong datalen - fix
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if(r->datalen != l-3){ r->datalen = l-3; }
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r->data = pack;
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}
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return 1;
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}
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// USART4: PC10 - Tx, PC11 - Rx
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void modbus_setup(uint32_t speed){
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uint32_t tmout = 16000000;
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// PA9 - Tx, PA10 - Rx
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RCC->APB1ENR |= RCC_APB1ENR_UART4EN;
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RCC->AHBENR |= RCC_AHBENR_DMA2EN;
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GPIOA->CRH = (GPIOA->CRH & ~(CRH(9,0xf)|CRH(10,0xf))) |
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CRH(9, CNF_AFPP|MODE_NORMAL) | CRH(10, CNF_FLINPUT|MODE_INPUT);
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// UART4 Tx DMA - Channel5 (Rx - channel 3)
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DMA2_Channel5->CPAR = (uint32_t) &UART4->DR; // periph
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DMA2_Channel5->CCR |= DMA_CCR_MINC | DMA_CCR_DIR | DMA_CCR_TCIE; // 8bit, mem++, mem->per, transcompl irq
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// Tx CNDTR set @ each transmission due to data size
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NVIC_SetPriority(DMA2_Channel4_5_IRQn, 2);
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NVIC_EnableIRQ(DMA2_Channel4_5_IRQn);
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NVIC_SetPriority(UART4_IRQn, 2);
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// setup uart4
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UART4->BRR = 36000000 / speed; // APB1 is 36MHz
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UART4->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; // 1start,8data,nstop; enable Rx,Tx,USART
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while(!(UART4->SR & USART_SR_TC)){if(--tmout == 0) break;} // polling idle frame Transmission
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UART4->SR = 0; // clear flags
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UART4->CR1 |= USART_CR1_RXNEIE | USART_CR1_IDLEIE; // allow Rx and IDLE IRQ
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UART4->CR3 = USART_CR3_DMAT; // enable DMA Tx
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NVIC_EnableIRQ(UART4_IRQn);
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}
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void uart4_isr(){
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if(UART4->SR & USART_SR_IDLE){ // idle - end of frame
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modbus_rdy = 1;
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dlen = idatalen[rbufno];
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recvdata = rbuf[rbufno];
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// prepare other buffer
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rbufno = !rbufno;
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idatalen[rbufno] = 0;
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(void) UART4->DR; // clear IDLE flag by reading DR
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}
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if(UART4->SR & USART_SR_RXNE){ // RX not emty - receive next char
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uint8_t rb = UART4->DR; // clear RXNE flag
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if(idatalen[rbufno] < MODBUSBUFSZI){ // put next char into buf
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rbuf[rbufno][idatalen[rbufno]++] = rb;
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}else{ // buffer overrun
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bufovr = 1;
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idatalen[rbufno] = 0;
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}
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}
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}
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void dma2_channel4_5_isr(){
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if(DMA2->ISR & DMA_ISR_TCIF5){ // Tx
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DMA2->IFCR = DMA_IFCR_CTCIF5; // clear TC flag
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modbus_txrdy = 1;
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}
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}
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