From 17c4367b9c70f1d406e1ffefed0a1acf7c620230 Mon Sep 17 00:00:00 2001 From: Edward Emelianov Date: Fri, 6 Jan 2023 17:44:26 +0300 Subject: [PATCH] blink for G0 works --- G0:G070/blink/Makefile | 10 +++- G0:G070/blink/README | 4 +- G0:G070/blink/blink.bin | Bin 1092 -> 880 bytes G0:G070/blink/openocd.cfg | 89 ++++++++++++++++++++++++++++++++++ G0:G070/blink/systick_blink.c | 57 +++++++++++----------- G0:G070/inc/Fx/stm32g0.h | 56 +++++++++++++++++---- G0:G070/inc/cm/core_cm0plus.h | 2 +- G0:G070/inc/ld/stm32g070xb.ld | 2 - G0:G070/inc/startup/vector.c | 3 -- 9 files changed, 175 insertions(+), 48 deletions(-) create mode 100644 G0:G070/blink/openocd.cfg diff --git a/G0:G070/blink/Makefile b/G0:G070/blink/Makefile index a93f0a3..9835964 100644 --- a/G0:G070/blink/Makefile +++ b/G0:G070/blink/Makefile @@ -5,7 +5,7 @@ BOOTSPEED ?= 115200 FAMILY = G0 # MCU code MCU = G070xx -DEFS = -DEBUG -g +DEFS = -DEBUG -g3 # change this linking script depending on particular MCU model, # for example, if you have STM32F103VBT6, you should write: LDSCRIPT = stm32g070xb.ld @@ -134,4 +134,10 @@ boot: $(BIN) @echo " LOAD $(BIN) through bootloader" $(STBOOT) -b$(BOOTSPEED) $(BOOTPORT) -w $(BIN) -.PHONY: clean flash boot +openocd: + openocd -f openocd.cfg +dbg: + arm-none-eabi-gdb $(ELF) -ex 'target remote localhost:3333' -ex 'monitor reset halt' + + +.PHONY: clean flash boot openocd dbg diff --git a/G0:G070/blink/README b/G0:G070/blink/README index 3494a6a..221b0c6 100644 --- a/G0:G070/blink/README +++ b/G0:G070/blink/README @@ -1,3 +1,3 @@ Toggle LED on STM32G070-pill depending on user button: -- not pressed - 'SOS' in Morze -- pressed - blink with period of 1 second +- pressed - 'SOS' in Morze +- not pressed - blink with period of 1 second diff --git a/G0:G070/blink/blink.bin b/G0:G070/blink/blink.bin index 8fa372b3bd6181a5593dc1a8a471c8e001615d3e..68908371e3479ba0c3d5055d41ff901b15605123 100755 GIT binary patch literal 880 zcma)4PiWIn82^&g(Kd=*bLk(2G!@p;lg&Y8Y}UlRu6b^Z7IdzlZ|#J%^^l{NLC<=T z^|bcpjvfSMAmX9kJSG)H3Q9aky$Igas*Uf}Rf|k9@bM+T@Av(_U*7xRF39hA@V}+; zng;yiVVp^sy+4EBJ*@YzVEn`I$*jNC{uk#B$>datSotoZqvVhKZ_pLAik6UttwPLn z_k+0@X(~~3$2Y6_?VAPO<<3D`u)8Q?hP2O4Q@MeQeAEo;2RxqgoXVd(yO}H-;@6cJ?*&NP3VS>FRqkGrXHAy^YNglXDX0v5rLkBk1S$N z?x00{=F%=&z-L$5C|QeWIj1{!e&#WPxnXi!fy7g!u9l&#Np^|r#5&N4bU1Flv=n@m zM-8IZneM!3f^ubjnufe+tfZbQ_+m_Xk5-ZE45su5tpO zEHsE%50AY`x=6iI4K+hBiklHlU}p(?n~w(LTzN2{ij{EsrNb2a4s-W#K<_ie=RD6F zjXV#)f}9W%vLN$0UI6gXyQbT?_Rah5gUf{r5$j=l#KJnzqDwDtQ(%k6bbe01uW>)| O>CEtH-lXq6_5A||m+V;p literal 1092 zcma))Pe>F|9LL}MVRdKMm{uZPlh&C)H$Ax?bOl@A*mHMYS+0jftj5h^){|637iqy$ z3_<0g)I<017IrX%4KG0jvpW&uA@*jMz*BA(PQUkL$%91$Kjt&P_x=9n_kQo8$0+th zMD>p#9zvjhJWNwtX8acY@i6aE!SqMvYybM&+W+Q7v(Xk3jn?dNk-)EF)zvTL3K=2i z$t0c3MD5C|l8Radt=WDmAIJ6Xct)%UeJC!uMbc!exLPV`qckfv+lmpjw({jb@Y5wz zZ39&jon@-cynw5&s-RH9bW^e4kC4+0x7E)?_wEP95+?gS~u;+fl)GJ^sUF`|ful6z&< z=?RMxOj_(H?r>Lfo%vJvySvx^08tWYYqHT!wVEXkDvz(>Mz@u=rpFASe;$W7i|r@U zcPwe<9Pg>$kf0~1mq=JAkwHQ@0M*vFSEg9S&!rDQueV|Ts+jV9e}CWiQDa2DCBkiy z;Y{GxTvjWn^5RVcLf=q@ozpJ~)t`PjggSJDz=QU|&(5%*A2XNHXg*|&O@%WJ)WLyr z*i`Qe-A%JXViEr+DO52Ruv|uM&5&8ZKTH0u>@$C@Hmg4*^Sc^@7Gg*<>K%O7lY$Pu z?n#P+hde3d;0{j;JGjB~wV)VTV=Q`+NKm}#vejk}Rf5U}kl?+SiqY)gJZFcq!I^Sq zYQYO}-hk?$7rCCZ!`a|WIkOHx&-r6{1G)l-z#W_&&IV`7nRN~h&Ks~7&?Bzr>~Lm# z6g. * - * Copyright 2017 Edward V. Emelianoff - * - * This program is free software; you can redistribute it and/or modify + * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or + * the Free Software Foundation, either version 3 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -14,15 +13,13 @@ * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. + * along with this program. If not, see . */ #include "stm32g0.h" // KEY (intpullup->0) - PC0 -// LED - PC7 +// LED - PC8 static volatile uint32_t blink_ctr = 0; @@ -34,44 +31,48 @@ void sys_tick_handler(void){ /* * Set up timer to fire every x milliseconds */ -static void systick_setup(uint32_t xms){ // xms < 1864!!! +static void systick_setup(uint32_t xms){ // xms < 2098!!! static uint32_t curms = 0; if(curms == xms) return; - // 9MHz - HCLK/8 + // 8MHz - HCLK/8 // this function also clears counter so it starts right away - SysTick_Config(9000 * xms); // arg should be < 0xffffff, so ms should be < 1864 + SysTick_Config(8000 * xms); // arg should be < 0xffffff, so ms should be < 2098 curms = xms; } static void gpio_setup(void){ RCC->IOPENR = RCC_IOPENR_GPIOCEN; // enable PC - // set PC7 as opendrain output, PC0 is pullup input - GPIOC->MODER = GPIO_MODER_MODER7_O; - GPIOC->PUPDR = GPIO_PUPDR_PUPD0; - GPIOC->OTYPER = GPIO_OTYPER_OT7; + // set PC8 as opendrain output, PC0 is pullup input, other as default (AIN) + GPIOC->MODER = (0xffffffff & ~(GPIO_MODER_MODE8 | GPIO_MODER_MODE0)) | GPIO_MODER_MODER8_O; + GPIOC->PUPDR = GPIO_PUPDR0_PU; // pullup + GPIOC->OTYPER = GPIO_OTYPER_OT8; // open drain } static const uint32_t L[] = {125,100,125,100,125,200, 350,100,350,100,350,200, 125,100,125,100,125, 1000}; int main(void){ StartHSE(); - //StartHSI48(); gpio_setup(); - /* 500ms ticks => 1000ms period => 1Hz blinks */ - systick_setup(100); + systick_setup(500); + uint32_t M = 0; + int pressed = 0; /* Do nothing in main loop */ while (1){ - if(pin_read(GPIOC, 1<<7)){ // key not pressed - 'sos' - uint32_t T = blink_ctr % 18; - systick_setup(L[T]); - if(T & 1) pin_clear(GPIOC, 1<<7); - else pin_set(GPIOC, 1<<7); + if(pin_read(GPIOC, 1<<0) == 0){ // key not pressed - 'sos' + pressed = 1; + systick_setup(L[M]); + if(M & 1) pin_set(GPIOC, 1<<8); + else pin_clear(GPIOC, 1<<8); + if(++M == 18) M = 0; }else{ // key pressed - blink with period of 1s - systick_setup(500); - if(blink_ctr & 1) pin_clear(GPIOC, 1<<7); - else pin_set(GPIOC, 1<<7); - + if(pressed){ + M = 0; + pressed = 0; + systick_setup(500); + } + if(blink_ctr & 1) pin_set(GPIOC, 1<<8); + else pin_clear(GPIOC, 1<<8); } } } diff --git a/G0:G070/inc/Fx/stm32g0.h b/G0:G070/inc/Fx/stm32g0.h index ec0b039..d88853d 100644 --- a/G0:G070/inc/Fx/stm32g0.h +++ b/G0:G070/inc/Fx/stm32g0.h @@ -29,8 +29,9 @@ /************************* RCC *************************/ // reset clocking registers -TRUE_INLINE void sysreset(void){ // do nothing +/* TRUE_INLINE void sysreset(void){ // do nothing } +*/ /* * R=2..8, Q=2..8, P=2..32; N=8..86, M=1..8 @@ -40,23 +41,58 @@ TRUE_INLINE void sysreset(void){ // do nothing * fpllp = fvco/P (<=122MHz) -> P(72)=2 * fpllq = fvco/Q (<=128MHz) -> Q(48)=3 * fpllr = fvco/R (<=64MHz) -> R(48)=3 - * AHB prescaler (72MHz) = 144/72 = 2 - * APB prescaler (72MHz) = 72/72 = 1 + * AHB prescaler (36MHz) = 72/36 = 2 + * APB prescaler (36MHz) = 36/36 = 1 + * + * fp=fq=fr=fsys=64MHz => M=1, N=8, P=1, Q=1, R=1 */ +#ifndef PLLN +#define PLLN 16 +#endif +#ifndef PLLM +#define PLLM 1 +#endif +#ifndef PLLP +#define PLLP 2 +#endif +#ifndef PLLQ +#define PLLQ 2 +#endif +#ifndef PLLR +#define PLLR 2 +#endif + #define WAITWHILE(x) do{StartUpCounter = 0; while((x) && (++StartUpCounter < 0xffffff)){nop();}}while(0) -TRUE_INLINE void StartHSE(){ +TRUE_INLINE void StartHSEHSI(int isHSE){ uint32_t StartUpCounter; RCC->CR &= ~RCC_CR_PLLON; // disable PLL WAITWHILE(RCC->CR & RCC_CR_PLLRDY); // wait while PLL on - RCC->CR |= RCC_CR_HSEON; - WAITWHILE(!(RCC->CIFR & RCC_CIFR_HSERDYF)); // wait while HSE isn't on - RCC->CICR = RCC_CICR_HSERDYC; // clear rdy flag + if(isHSE){ + RCC->CR |= RCC_CR_HSEON; + WAITWHILE(!(RCC->CR & RCC_CR_HSERDY)); // wait while HSE isn't on + }else RCC->CR |= RCC_CR_HSION; + RCC->APBENR1 |= RCC_APBENR1_PWREN; + // Enable high performance mode + PWR->CR1 = PWR_CR1_VOS_0; + WAITWHILE(PWR->SR2 & PWR_SR2_VOSF); + if(isHSE){ + RCC->PLLCFGR = ((PLLR-1)<<29) | ((PLLQ-1)<<25) | ((PLLP-1)<<17) | (PLLN<<8) | ((PLLM-1)<<4) + | RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLPEN /* | RCC_PLLCFGR_PLLQEN */ + | RCC_PLLCFGR_PLLSRC_HSE; + }else{ // 64MHz from HSI16 + RCC->PLLCFGR = (8<<8) | (1<<4) + | RCC_PLLCFGR_PLLREN | RCC_PLLCFGR_PLLPEN /* | RCC_PLLCFGR_PLLQEN */ + | RCC_PLLCFGR_PLLSRC_HSI; + } RCC->CR |= RCC_CR_PLLON; - RCC->PLLCFGR = (3<<29) | (3<<25) | (2<<17) | (18<<8) | (1<<4) | RCC_PLLCFGR_PLLSRC_HSE; - RCC->CFGR = RCC_CFGR_HPRE_3 | RCC_CFGR_SW_1; // set sysclk switch to pll, set prescalers - WAITWHILE((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1); // wait until status changed + WAITWHILE(!(RCC->CR & RCC_CR_PLLRDY)); + FLASH->ACR |= FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_1; + RCC->CFGR = RCC_CFGR_SW_1; // set sysclk switch to pll } +#define StartHSE() do{StartHSEHSI(1);}while(0) +#define StartHSI() do{StartHSEHSI(0);}while(0) + /************************* GPIO *************************/ /******************* Bit definition for GPIO_MODER register *****************/ diff --git a/G0:G070/inc/cm/core_cm0plus.h b/G0:G070/inc/cm/core_cm0plus.h index 4d7facf..fb760f8 100644 --- a/G0:G070/inc/cm/core_cm0plus.h +++ b/G0:G070/inc/cm/core_cm0plus.h @@ -800,7 +800,7 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) SysTick->LOAD = ticks - 1; /* set reload register */ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick->CTRL = //SysTick_CTRL_CLKSOURCE_Msk | // clk/8 SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0); /* Function successful */ diff --git a/G0:G070/inc/ld/stm32g070xb.ld b/G0:G070/inc/ld/stm32g070xb.ld index 2c3b0f8..557dc2b 100644 --- a/G0:G070/inc/ld/stm32g070xb.ld +++ b/G0:G070/inc/ld/stm32g070xb.ld @@ -1,5 +1,3 @@ -/* Linker script for STM32F030f4, 16K flash, 4K RAM. */ - /* Define memory regions. */ MEMORY { diff --git a/G0:G070/inc/startup/vector.c b/G0:G070/inc/startup/vector.c index 04dfbb6..f4080b4 100644 --- a/G0:G070/inc/startup/vector.c +++ b/G0:G070/inc/startup/vector.c @@ -148,9 +148,6 @@ void WEAK __attribute__ ((naked)) __attribute__ ((noreturn)) reset_handler(void) char *dst = &_sdata; char *src = &_ldata; - // enable 8-byte stack alignment to comply with AAPCS - //SCB->CCR |= 0x00000200; - // copy initialized variables data while ( dst < &_edata ) { *dst++ = *src++; }