mirror of
https://github.com/eddyem/stm32samples.git
synced 2026-03-22 01:31:21 +03:00
Modified F0: testbrd, CDC, pl2303 and HID
This commit is contained in:
eddyem
1
F0-nolib/inc/F0
Symbolic link
1
F0-nolib/inc/F0
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@@ -0,0 +1 @@
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/home/eddy/Yandex.Disk/Projects/stm32samples/F0-nolib/inc/Fx
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@@ -1,229 +0,0 @@
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/*
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* stm32f0.h
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*
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* Copyright 2017 Edward V. Emelianoff <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#pragma once
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#ifndef __STM32F0_H__
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#define __STM32F0_H__
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#include <stdint.h>
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#include "stm32f0xx.h"
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#ifndef TRUE_INLINE
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#define TRUE_INLINE __attribute__((always_inline)) static inline
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#endif
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#ifndef NULL
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#define NULL (0)
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#endif
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// some good things from CMSIS
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#define nop() __NOP()
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/************************* RCC *************************/
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// reset clocking registers
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TRUE_INLINE void sysreset(void){
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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#if defined (STM32F051x8) || defined (STM32F058x8)
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/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
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RCC->CFGR &= (uint32_t)0xF8FFB80C;
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#else
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/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
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RCC->CFGR &= (uint32_t)0x08FFB80C;
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#endif /* STM32F051x8 or STM32F058x8 */
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
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RCC->CFGR &= (uint32_t)0xFFC0FFFF;
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/* Reset PREDIV[3:0] bits */
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RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
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#if defined (STM32F072xB) || defined (STM32F078xB)
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/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
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#elif defined (STM32F071xB)
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/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
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#elif defined (STM32F091xC) || defined (STM32F098xx)
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/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
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#elif defined (STM32F030x4) || defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
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/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
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#elif defined (STM32F051x8) || defined (STM32F058xx)
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/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
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#elif defined (STM32F042x6) || defined (STM32F048xx)
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/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
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#elif defined (STM32F070x6) || defined (STM32F070xB)
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/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
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/* Set default USB clock to PLLCLK, since there is no HSI48 */
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RCC->CFGR3 |= (uint32_t)0x00000080;
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#else
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#error "No target selected"
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#endif
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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/* Reset HSI14 bit */
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RCC->CR2 &= (uint32_t)0xFFFFFFFE;
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// Enable Prefetch Buffer and set Flash Latency
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FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
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/* HCLK = SYSCLK */
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RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
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/* PCLK = HCLK */
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RCC->CFGR |= RCC_CFGR_PPRE_DIV1;
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/* PLL configuration = (HSI/2) * 12 = ~48 MHz */
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RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
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RCC->CFGR |= RCC_CFGR_PLLMUL12;
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/* Enable PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CR & RCC_CR_PLLRDY) == 0){}
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/* Select PLL as system clock source */
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RCC->CFGR &= ~RCC_CFGR_SW;
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL){}
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}
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/* wrong
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TRUE_INLINE void StartHSE(){
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// disable PLL
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RCC->CR &= ~RCC_CR_PLLON;
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RCC->CR |= RCC_CR_HSEON;
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while ((RCC->CIR & RCC_CIR_HSERDYF) == 0);
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RCC->CIR |= RCC_CIR_HSERDYC; // clear rdy flag
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// PLL configuration = (HSE) * 12 = ~48 MHz
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RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
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RCC->CFGR |= RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLMUL12;
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RCC->CR |= RCC_CR_PLLON;
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL){}
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} */
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#if defined (STM32F042x6) || defined (STM32F072xb)
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TRUE_INLINE void StartHSI48(){
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RCC->APB1ENR |= RCC_APB1ENR_CRSEN | RCC_APB1ENR_USBEN; // enable CRS (hsi48 sync) & USB
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RCC->CFGR3 &= ~RCC_CFGR3_USBSW; // reset USB
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RCC->CR2 |= RCC_CR2_HSI48ON; // turn ON HSI48
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uint32_t tmout = 16000000;
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while(!(RCC->CR2 & RCC_CR2_HSI48RDY)){if(--tmout == 0) break;}
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FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
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CRS->CFGR &= ~CRS_CFGR_SYNCSRC;
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CRS->CFGR |= CRS_CFGR_SYNCSRC_1; // USB SOF selected as sync source
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CRS->CR |= CRS_CR_AUTOTRIMEN; // enable auto trim
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CRS->CR |= CRS_CR_CEN; // enable freq counter & block CRS->CFGR as read-only
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RCC->CFGR |= RCC_CFGR_SW;
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}
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#endif
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/************************* GPIO *************************/
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/******************* Bit definition for GPIO_MODER register *****************/
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// _AI - analog inpt, _O - general output, _AF - alternate function
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#define GPIO_MODER_MODER0_AI ((uint32_t)0x00000003)
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#define GPIO_MODER_MODER0_O ((uint32_t)0x00000001)
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#define GPIO_MODER_MODER0_AF ((uint32_t)0x00000002)
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#define GPIO_MODER_MODER1_AI ((uint32_t)0x0000000C)
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#define GPIO_MODER_MODER1_O ((uint32_t)0x00000004)
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#define GPIO_MODER_MODER1_AF ((uint32_t)0x00000008)
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#define GPIO_MODER_MODER2_AI ((uint32_t)0x00000030)
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#define GPIO_MODER_MODER2_O ((uint32_t)0x00000010)
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#define GPIO_MODER_MODER2_AF ((uint32_t)0x00000020)
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#define GPIO_MODER_MODER3_AI ((uint32_t)0x000000C0)
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#define GPIO_MODER_MODER3_O ((uint32_t)0x00000040)
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#define GPIO_MODER_MODER3_AF ((uint32_t)0x00000080)
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#define GPIO_MODER_MODER4_AI ((uint32_t)0x00000300)
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#define GPIO_MODER_MODER4_O ((uint32_t)0x00000100)
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#define GPIO_MODER_MODER4_AF ((uint32_t)0x00000200)
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#define GPIO_MODER_MODER5_AI ((uint32_t)0x00000C00)
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#define GPIO_MODER_MODER5_O ((uint32_t)0x00000400)
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#define GPIO_MODER_MODER5_AF ((uint32_t)0x00000800)
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#define GPIO_MODER_MODER6_AI ((uint32_t)0x00003000)
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#define GPIO_MODER_MODER6_O ((uint32_t)0x00001000)
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#define GPIO_MODER_MODER6_AF ((uint32_t)0x00002000)
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#define GPIO_MODER_MODER7_AI ((uint32_t)0x0000C000)
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#define GPIO_MODER_MODER7_O ((uint32_t)0x00004000)
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#define GPIO_MODER_MODER7_AF ((uint32_t)0x00008000)
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#define GPIO_MODER_MODER8_AI ((uint32_t)0x00030000)
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#define GPIO_MODER_MODER8_O ((uint32_t)0x00010000)
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#define GPIO_MODER_MODER8_AF ((uint32_t)0x00020000)
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#define GPIO_MODER_MODER9_AI ((uint32_t)0x000C0000)
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#define GPIO_MODER_MODER9_O ((uint32_t)0x00040000)
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#define GPIO_MODER_MODER9_AF ((uint32_t)0x00080000)
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#define GPIO_MODER_MODER10_AI ((uint32_t)0x00300000)
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#define GPIO_MODER_MODER10_O ((uint32_t)0x00100000)
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#define GPIO_MODER_MODER10_AF ((uint32_t)0x00200000)
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#define GPIO_MODER_MODER11_AI ((uint32_t)0x00C00000)
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#define GPIO_MODER_MODER11_O ((uint32_t)0x00400000)
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#define GPIO_MODER_MODER11_AF ((uint32_t)0x00800000)
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#define GPIO_MODER_MODER12_AI ((uint32_t)0x03000000)
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#define GPIO_MODER_MODER12_O ((uint32_t)0x01000000)
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#define GPIO_MODER_MODER12_AF ((uint32_t)0x02000000)
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#define GPIO_MODER_MODER13_AI ((uint32_t)0x0C000000)
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#define GPIO_MODER_MODER13_O ((uint32_t)0x04000000)
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#define GPIO_MODER_MODER13_AF ((uint32_t)0x08000000)
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#define GPIO_MODER_MODER14_AI ((uint32_t)0x30000000)
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#define GPIO_MODER_MODER14_O ((uint32_t)0x10000000)
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#define GPIO_MODER_MODER14_AF ((uint32_t)0x20000000)
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#define GPIO_MODER_MODER15_AI ((uint32_t)0xC0000000)
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#define GPIO_MODER_MODER15_O ((uint32_t)0x40000000)
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#define GPIO_MODER_MODER15_AF ((uint32_t)0x80000000)
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#define pin_toggle(gpioport, gpios) do{ \
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register uint32_t __port = gpioport->ODR; \
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gpioport->BSRR = ((__port & gpios) << 16) | (~__port & gpios);}while(0)
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#define pin_set(gpioport, gpios) do{gpioport->BSRR = gpios;}while(0)
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#define pin_clear(gpioport, gpios) do{gpioport->BRR = gpios;}while(0)
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#define pin_read(gpioport, gpios) ((gpioport->IDR & gpios) ? 1 : 0)
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#define pin_write(gpioport, gpios) do{gpioport->ODR = gpios;}while(0)
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|
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/************************* ADC *************************/
|
||||
/* inner termometer calibration values
|
||||
* Temp = (V30 - Vsense)/Avg_Slope + 30
|
||||
* Avg_Slope = (V30 - V110) / (110 - 30)
|
||||
*/
|
||||
#define TEMP110_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7C2))
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#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7B8))
|
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// VDDA_Actual = 3.3V * VREFINT_CAL / average vref value
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#define VREFINT_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FFFF7BA))
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#define VDD_CALIB ((uint16_t) (330))
|
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#define VDD_APPLI ((uint16_t) (300))
|
||||
|
||||
/************************* USART *************************/
|
||||
|
||||
#define USART_CR2_ADD_SHIFT 24
|
||||
// set address/character match value
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||||
#define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT)
|
||||
|
||||
/************************* IWDG *************************/
|
||||
#define IWDG_REFRESH (uint32_t)(0x0000AAAA)
|
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#define IWDG_WRITE_ACCESS (uint32_t)(0x00005555)
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||||
#define IWDG_START (uint32_t)(0x0000CCCC)
|
||||
|
||||
|
||||
//#define do{}while(0)
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|
||||
|
||||
|
||||
|
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#endif // __STM32F0_H__
|
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@@ -1,247 +0,0 @@
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/**
|
||||
******************************************************************************
|
||||
* @file stm32f0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 05-December-2014
|
||||
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32F0xx device used in the target application
|
||||
* - To use or not the peripheral's drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral's registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f0xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __STM32F0xx_H
|
||||
#define __STM32F0xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if !defined (STM32F030x4) && !defined (STM32F030x6) && !defined (STM32F030x8) && \
|
||||
!defined (STM32F031x6) && !defined (STM32F038xx) && \
|
||||
!defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
|
||||
!defined (STM32F051x8) && !defined (STM32F058xx) && \
|
||||
!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
|
||||
!defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
|
||||
#error "Define STM32 family, for example -DSTM32F042x6"
|
||||
#endif
|
||||
|
||||
#ifndef WEAK
|
||||
#define WEAK __attribute__((weak))
|
||||
#endif
|
||||
|
||||
void WEAK reset_handler(void);
|
||||
void WEAK nmi_handler(void);
|
||||
void WEAK hard_fault_handler(void);
|
||||
void WEAK sv_call_handler(void);
|
||||
void WEAK pend_sv_handler(void);
|
||||
void WEAK sys_tick_handler(void);
|
||||
|
||||
void WEAK wwdg_isr(void);
|
||||
void WEAK pvd_isr(void);
|
||||
void WEAK rtc_isr(void);
|
||||
void WEAK flash_isr(void);
|
||||
void WEAK rcc_isr(void);
|
||||
void WEAK exti0_1_isr(void);
|
||||
void WEAK exti2_3_isr(void);
|
||||
void WEAK exti4_15_isr(void);
|
||||
void WEAK tsc_isr(void);
|
||||
void WEAK dma1_channel1_isr(void);
|
||||
void WEAK dma1_channel2_3_isr(void);
|
||||
void WEAK dma1_channel4_5_isr(void);
|
||||
void WEAK adc_comp_isr(void);
|
||||
void WEAK tim1_brk_up_trg_com_isr(void);
|
||||
void WEAK tim1_cc_isr(void);
|
||||
void WEAK tim2_isr(void);
|
||||
void WEAK tim3_isr(void);
|
||||
void WEAK tim6_dac_isr(void);
|
||||
void WEAK tim7_isr(void);
|
||||
void WEAK tim14_isr(void);
|
||||
void WEAK tim15_isr(void);
|
||||
void WEAK tim16_isr(void);
|
||||
void WEAK tim17_isr(void);
|
||||
void WEAK i2c1_isr(void);
|
||||
void WEAK i2c2_isr(void);
|
||||
void WEAK spi1_isr(void);
|
||||
void WEAK spi2_isr(void);
|
||||
void WEAK usart1_isr(void);
|
||||
void WEAK usart2_isr(void);
|
||||
void WEAK usart3_4_isr(void);
|
||||
void WEAK cec_can_isr(void);
|
||||
void WEAK usb_isr(void);
|
||||
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V2.2.0
|
||||
*/
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|
||||
|(__CMSIS_DEVICE_HAL_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
|
||||
// arch-dependent defines
|
||||
#if defined(STM32F030x4)
|
||||
#include "stm32f030x6.h"
|
||||
#elif defined(STM32F030x6)
|
||||
#include "stm32f030x6.h"
|
||||
#elif defined(STM32F030x8)
|
||||
#include "stm32f030x8.h"
|
||||
#elif defined(STM32F031x6)
|
||||
#include "stm32f031x6.h"
|
||||
#elif defined(STM32F038xx)
|
||||
#include "stm32f038xx.h"
|
||||
#elif defined(STM32F042x6)
|
||||
#include "stm32f042x6.h"
|
||||
#elif defined(STM32F048xx)
|
||||
#include "stm32f048xx.h"
|
||||
#elif defined(STM32F051x8)
|
||||
#include "stm32f051x8.h"
|
||||
#elif defined(STM32F058xx)
|
||||
#include "stm32f058xx.h"
|
||||
#elif defined(STM32F070x6)
|
||||
#include "stm32f070x6.h"
|
||||
#elif defined(STM32F070xB)
|
||||
#include "stm32f070xb.h"
|
||||
#elif defined(STM32F071xB)
|
||||
#include "stm32f071xb.h"
|
||||
#elif defined(STM32F072xB)
|
||||
#include "stm32f072xb.h"
|
||||
#elif defined(STM32F078xx)
|
||||
#include "stm32f078xx.h"
|
||||
#elif defined(STM32F091xC)
|
||||
#include "stm32f091xc.h"
|
||||
#elif defined(STM32F098xx)
|
||||
#include "stm32f098xx.h"
|
||||
#elif defined(STM32F030xC)
|
||||
#include "stm32f030xc.h"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ERROR = 0,
|
||||
SUCCESS = !ERROR
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Exported_macros
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32F0xx_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Reference in New Issue
Block a user