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568 lines
20 KiB
C
568 lines
20 KiB
C
/*
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* stm8l.h
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*
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* Copyright 2014 Edward V. Emelianoff <eddy@sao.ru>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#pragma once
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#ifndef __STM8L_H__
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#define __STM8L_H__
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typedef unsigned char U8;
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typedef unsigned int U16;
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typedef unsigned long U32;
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#define NULL (void*)0
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/* functions */
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#define enableInterrupts() {__asm__("rim\n");} // enable interrupts
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#define disableInterrupts() {__asm__("sim\n");} // disable interrupts
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#define iret() {__asm__("iret\n");} // Interrupt routine return
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#define pop_ccr() {__asm__("pop cc\n");} // Pop CCR from the stack
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#define push_ccr() {__asm__("push cc\n");}// Push CCR on the stack
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#define rim() {__asm__("rim\n");} // enable interrupts
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#define sim() {__asm__("sim\n");} // disable interrupts
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#define nop() {__asm__("nop\n");} // No Operation
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#define trap() {__asm__("trap\n");} // Trap (soft IT)
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#define wfi() {__asm__("wfi\n");} // Wait For Interrupt
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#define halt() {__asm__("halt\n");} // Halt
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/*
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* Registers map is shown in short datasheet, page 26
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*/
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/* GPIO */
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#define PA_ODR *(unsigned char*)0x5000
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#define PA_IDR *(unsigned char*)0x5001
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#define PA_DDR *(unsigned char*)0x5002
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#define PA_CR1 *(unsigned char*)0x5003
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#define PA_CR2 *(unsigned char*)0x5004
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#define PB_ODR *(unsigned char*)0x5005
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#define PB_IDR *(unsigned char*)0x5006
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#define PB_DDR *(unsigned char*)0x5007
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#define PB_CR1 *(unsigned char*)0x5008
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#define PB_CR2 *(unsigned char*)0x5009
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#define PC_ODR *(unsigned char*)0x500A
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#define PC_IDR *(unsigned char*)0x500B
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#define PC_DDR *(unsigned char*)0x500C
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#define PC_CR1 *(unsigned char*)0x500D
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#define PC_CR2 *(unsigned char*)0x500E
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#define PD_ODR *(unsigned char*)0x500F
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#define PD_IDR *(unsigned char*)0x5010
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#define PD_DDR *(unsigned char*)0x5011
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#define PD_CR1 *(unsigned char*)0x5012
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#define PD_CR2 *(unsigned char*)0x5013
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#define PE_ODR *(unsigned char*)0x5014
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#define PE_IDR *(unsigned char*)0x5015
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#define PE_DDR *(unsigned char*)0x5016
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#define PE_CR1 *(unsigned char*)0x5017
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#define PE_CR2 *(unsigned char*)0x5018
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#define PF_ODR *(unsigned char*)0x5019
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#define PF_IDR *(unsigned char*)0x501A
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#define PF_DDR *(unsigned char*)0x501B
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#define PF_CR1 *(unsigned char*)0x501C
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#define PF_CR2 *(unsigned char*)0x501D
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#ifdef STM8S105
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#define PG_ODR *(unsigned char*)0x501E
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#define PG_IDR *(unsigned char*)0x501F
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#define PG_DDR *(unsigned char*)0x5020
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#define PG_CR1 *(unsigned char*)0x5021
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#define PG_CR2 *(unsigned char*)0x5022
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#define PH_ODR *(unsigned char*)0x5023
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#define PH_IDR *(unsigned char*)0x5024
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#define PH_DDR *(unsigned char*)0x5025
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#define PH_CR1 *(unsigned char*)0x5026
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#define PH_CR2 *(unsigned char*)0x5027
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#define PI_ODR *(unsigned char*)0x5028
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#define PI_IDR *(unsigned char*)0x5029
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#define PI_DDR *(unsigned char*)0x502A
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#define PI_CR1 *(unsigned char*)0x502B
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#define PI_CR2 *(unsigned char*)0x502C
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#endif // STM8S105
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/* GPIO bits */
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#define GPIO_PIN0 (1 << 0)
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#define GPIO_PIN1 (1 << 1)
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#define GPIO_PIN2 (1 << 2)
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#define GPIO_PIN3 (1 << 3)
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#define GPIO_PIN4 (1 << 4)
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#define GPIO_PIN5 (1 << 5)
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#define GPIO_PIN6 (1 << 6)
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#define GPIO_PIN7 (1 << 7)
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/* -------------------- FLASH/EEPROM -------------------- */
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#define FLASH_CR1 *(unsigned char*)0x505A
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#define FLASH_CR2 *(unsigned char*)0x505B
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#define FLASH_NCR2 *(unsigned char*)0x505C
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#define FLASH_FPR *(unsigned char*)0x505D
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#define FLASH_NFPR *(unsigned char*)0x505E
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#define FLASH_IAPSR *(unsigned char*)0x505F
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#define FLASH_PUKR *(unsigned char*)0x5062 // progmem unprotection
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#define FLASH_DUKR *(unsigned char*)0x5064 // EEPROM unprotection
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#define EEPROM_KEY1 0xAE // keys to manage EEPROM's write access
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#define EEPROM_KEY2 0x56
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#define EEPROM_START_ADDR (unsigned char*)0x4000
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/* ------------------- interrupts ------------------- */
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#define EXTI_CR1 *(unsigned char*)0x50A0
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#define EXTI_CR2 *(unsigned char*)0x50A1
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#define INTERRUPT_HANDLER(fn, num) void fn() __interrupt(num)
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#define INTERRUPT_DEFINITION(fn, num) extern void fn() __interrupt(num)
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// Reset status register
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#define RST_SR *(unsigned char*)0x50B3
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/* ------------------- CLOCK ------------------- */
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#define CLK_ICKR *(unsigned char*)0x50C0
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#define CLK_ECKR *(unsigned char*)0x50C1
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#define CLK_CMSR *(unsigned char*)0x50C3
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#define CLK_SWR *(unsigned char*)0x50C4
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#define CLK_SWCR *(unsigned char*)0x50C5
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#define CLK_CKDIVR *(unsigned char*)0x50C6
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#define CLK_SPCKENR1 *(unsigned char*)0x50C7
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#define CLK_CSSR *(unsigned char*)0x50C8
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#define CLK_CCOR *(unsigned char*)0x50C9
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#define CLK_PCKENR2 *(unsigned char*)0x50CA
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#define CLK_HSITRIMR *(unsigned char*)0x50CC
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#define CLK_SWIMCCR *(unsigned char*)0x50CD
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/* ------------------- Watchdog ------------------ */
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#define WWDG_CR *(unsigned char*)0x50D1
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#define WWDG_WR *(unsigned char*)0x50D2
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#define IWDG_KR *(unsigned char*)0x50E0
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#define IWDG_PR *(unsigned char*)0x50E1
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#define IWDG_RLR *(unsigned char*)0x50E2
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// enable Watchdog
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#define KEY_ENABLE (0xCC)
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// refresh Watchdog from IWDG_RLR
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#define KEY_REFRESH (0xAA)
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// modify IWDG_PR and IWDG_RLR
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#define KEY_ACCESS (0x55)
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/* ------------------- AWU, BEEP ------------------- */
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#define AWU_CSR1 *(unsigned char*)0x50F0
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#define AWU_APR *(unsigned char*)0x50F1
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#define AWU_TBR *(unsigned char*)0x50F2
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#define BEEP_CSR *(unsigned char*)0x50F3
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/* ------------------- SPI ------------------- */
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#define SPI_CR1 *(unsigned char*)0x5200
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#define SPI_CR2 *(unsigned char*)0x5201
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#define SPI_ICR *(unsigned char*)0x5202
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#define SPI_SR *(unsigned char*)0x5203
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#define SPI_DR *(unsigned char*)0x5204
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#define SPI_CRCPR *(unsigned char*)0x5205
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#define SPI_RXCRCR *(unsigned char*)0x5206
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#define SPI_TXCRCR *(unsigned char*)0x5207
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// SPI_CR1 (page 271): | LSBFIRST | SPE | BR[2:0] | MSTR | CPOL | CPHA |
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#define SPI_CR1_LSBFIRST (1<<7)
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#define SPI_CR1_SPE (1<<6)
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#define SPI_CR1_BRMASK (0x38)
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#define SPI_CR1_MSTR (1<<2)
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#define SPI_CR1_CPOL (1<<1)
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#define SPI_CR1_CPHA (1)
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// SPI_CR2 (page 272): | BDM | BDOE | CRCEN | CRCNEXT | - | RXONLY | SSM | SSI |
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#define SPI_CR2_BDM (1<<7)
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#define SPI_CR2_BDOE (1<<6)
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#define SPI_CR2_CRCEN (1<<5)
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#define SPI_CR2_CRCNEXT (1<<4)
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#define SPI_CR2_RXONLY (1<<2)
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#define SPI_CR2_SSM (1<<1)
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#define SPI_CR2_SSI (1)
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// SPI_ICR (page 273): | TXIE | RXIE | ERRIE | WKIE | - | - | - | - |
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#define SPI_ICR_TXIE (1<<7)
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#define SPI_ICR_RXIE (1<<6)
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#define SPI_ICR_ERRIE (1<<5)
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#define SPI_ICR_WKIE (1<<4)
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// SPI_SR (page 274): | BSY | OVR | MODF | CRCERR | WKUP | - | TXE | RXNE |
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#define SPI_SR_BSY (1<<7)
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#define SPI_SR_OVR (1<<6)
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#define SPI_SR_MODF (1<<5)
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#define SPI_SR_CRCERR (1<<4)
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#define SPI_SR_WKUP (1<<3)
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#define SPI_SR_TXE (1<<1)
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#define SPI_SR_RXNE (1)
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/* ------------------- I2C ------------------- */
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#define I2C_CR1 *(unsigned char*)0x5210
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#define I2C_CR2 *(unsigned char*)0x5211
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#define I2C_FREQR *(unsigned char*)0x5212
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#define I2C_OARL *(unsigned char*)0x5213
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#define I2C_OARH *(unsigned char*)0x5214
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#define I2C_DR *(unsigned char*)0x5216
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#define I2C_SR1 *(unsigned char*)0x5217
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#define I2C_SR2 *(unsigned char*)0x5218
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#define I2C_SR3 *(unsigned char*)0x5219
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#define I2C_ITR *(unsigned char*)0x521A
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#define I2C_CCRL *(unsigned char*)0x521B
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#define I2C_CCRH *(unsigned char*)0x521C
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#define I2C_TRISER *(unsigned char*)0x521D
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#define I2C_PECR *(unsigned char*)0x521E
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/* ------------------- UART ------------------- */
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#ifdef STM8S003
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#define UART1_SR *(unsigned char*)0x5230
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#define UART1_DR *(unsigned char*)0x5231
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#define UART1_BRR1 *(unsigned char*)0x5232
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#define UART1_BRR2 *(unsigned char*)0x5233
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#define UART1_CR1 *(unsigned char*)0x5234
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#define UART1_CR2 *(unsigned char*)0x5235
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#define UART1_CR3 *(unsigned char*)0x5236
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#define UART1_CR4 *(unsigned char*)0x5237
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#define UART1_CR5 *(unsigned char*)0x5238
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#define UART1_GTR *(unsigned char*)0x5239
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#define UART1_PSCR *(unsigned char*)0x523A
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#endif // STM8S003
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#ifdef STM8S105
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#define UART2_SR *(unsigned char*)0x5240
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#define UART2_DR *(unsigned char*)0x5241
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#define UART2_BRR1 *(unsigned char*)0x5242
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#define UART2_BRR2 *(unsigned char*)0x5243
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#define UART2_CR1 *(unsigned char*)0x5244
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#define UART2_CR2 *(unsigned char*)0x5245
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#define UART2_CR3 *(unsigned char*)0x5246
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#define UART2_CR4 *(unsigned char*)0x5247
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#define UART2_CR5 *(unsigned char*)0x5248
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#define UART2_CR6 *(unsigned char*)0x5249
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#define UART2_GTR *(unsigned char*)0x524A
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#define UART2_PSCR *(unsigned char*)0x524B
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#endif // STM8S105
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/* UART_CR1 bits */
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#define UART_CR1_R8 (1 << 7)
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#define UART_CR1_T8 (1 << 6)
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#define UART_CR1_UARTD (1 << 5)
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#define UART_CR1_M (1 << 4)
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#define UART_CR1_WAKE (1 << 3)
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#define UART_CR1_PCEN (1 << 2)
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#define UART_CR1_PS (1 << 1)
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#define UART_CR1_PIEN (1 << 0)
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/* UART_CR2 bits */
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#define UART_CR2_TIEN (1 << 7)
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#define UART_CR2_TCIEN (1 << 6)
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#define UART_CR2_RIEN (1 << 5)
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#define UART_CR2_ILIEN (1 << 4)
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#define UART_CR2_TEN (1 << 3)
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#define UART_CR2_REN (1 << 2)
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#define UART_CR2_RWU (1 << 1)
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#define UART_CR2_SBK (1 << 0)
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/* USART_CR3 bits */
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#define UART_CR3_LINEN (1 << 6)
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#define UART_CR3_STOP2 (1 << 5)
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#define UART_CR3_STOP1 (1 << 4)
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#define UART_CR3_CLKEN (1 << 3)
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#define UART_CR3_CPOL (1 << 2)
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#define UART_CR3_CPHA (1 << 1)
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#define UART_CR3_LBCL (1 << 0)
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/* UART_SR bits */
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#define UART_SR_TXE (1 << 7)
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#define UART_SR_TC (1 << 6)
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#define UART_SR_RXNE (1 << 5)
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#define UART_SR_IDLE (1 << 4)
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#define UART_SR_OR (1 << 3)
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#define UART_SR_NF (1 << 2)
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#define UART_SR_FE (1 << 1)
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#define UART_SR_PE (1 << 0)
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/* ------------------- TIMERS ------------------- */
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/* TIM1 */
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#define TIM1_CR1 *(unsigned char*)0x5250
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#define TIM1_CR2 *(unsigned char*)0x5251
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#define TIM1_SMCR *(unsigned char*)0x5252
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#define TIM1_ETR *(unsigned char*)0x5253
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#define TIM1_IER *(unsigned char*)0x5254
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#define TIM1_SR1 *(unsigned char*)0x5255
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#define TIM1_SR2 *(unsigned char*)0x5256
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#define TIM1_EGR *(unsigned char*)0x5257
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#define TIM1_CCMR1 *(unsigned char*)0x5258
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#define TIM1_CCMR2 *(unsigned char*)0x5259
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#define TIM1_CCMR3 *(unsigned char*)0x525A
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#define TIM1_CCMR4 *(unsigned char*)0x525B
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#define TIM1_CCER1 *(unsigned char*)0x525C
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#define TIM1_CCER2 *(unsigned char*)0x525D
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#define TIM1_CNTRH *(unsigned char*)0x525E
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#define TIM1_CNTRL *(unsigned char*)0x525F
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#define TIM1_PSCRH *(unsigned char*)0x5260
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#define TIM1_PSCRL *(unsigned char*)0x5261
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#define TIM1_ARRH *(unsigned char*)0x5262
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#define TIM1_ARRL *(unsigned char*)0x5263
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#define TIM1_RCR *(unsigned char*)0x5264
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#define TIM1_CCR1H *(unsigned char*)0x5265
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#define TIM1_CCR1L *(unsigned char*)0x5266
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#define TIM1_CCR2H *(unsigned char*)0x5267
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#define TIM1_CCR2L *(unsigned char*)0x5268
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#define TIM1_CCR3H *(unsigned char*)0x5269
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#define TIM1_CCR3L *(unsigned char*)0x526A
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#define TIM1_CCR4H *(unsigned char*)0x526B
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#define TIM1_CCR4L *(unsigned char*)0x526C
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#define TIM1_BKR *(unsigned char*)0x526D
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#define TIM1_DTR *(unsigned char*)0x526E
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#define TIM1_OISR *(unsigned char*)0x526F
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/* TIM_IER bits */
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#define TIM_IER_BIE (1 << 7)
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#define TIM_IER_TIE (1 << 6)
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#define TIM_IER_COMIE (1 << 5)
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#define TIM_IER_CC4IE (1 << 4)
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#define TIM_IER_CC3IE (1 << 3)
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#define TIM_IER_CC2IE (1 << 2)
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#define TIM_IER_CC1IE (1 << 1)
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#define TIM_IER_UIE (1 << 0)
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/* TIM_CR1 bits */
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#define TIM_CR1_APRE (1 << 7)
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#define TIM_CR1_CMSH (1 << 6)
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#define TIM_CR1_CMSL (1 << 5)
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#define TIM_CR1_DIR (1 << 4)
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#define TIM_CR1_OPM (1 << 3)
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#define TIM_CR1_URS (1 << 2)
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#define TIM_CR1_UDIS (1 << 1)
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#define TIM_CR1_CEN (1 << 0)
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/* TIM_SR1 bits */
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#define TIM_SR1_BIF (1 << 7)
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#define TIM_SR1_TIF (1 << 6)
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#define TIM_SR1_COMIF (1 << 5)
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#define TIM_SR1_CC4IF (1 << 4)
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#define TIM_SR1_CC3IF (1 << 3)
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#define TIM_SR1_CC2IF (1 << 2)
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#define TIM_SR1_CC1IF (1 << 1)
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#define TIM_SR1_UIF (1 << 0)
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/* TIM_EGR bits */
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#define TIM_EGR_BG (1 << 7)
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#define TIM_EGR_TG (1 << 6)
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#define TIM_EGR_COMG (1 << 5)
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#define TIM_EGR_CC4G (1 << 4)
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#define TIM_EGR_CC3G (1 << 3)
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#define TIM_EGR_CC2G (1 << 2)
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#define TIM_EGR_CC1G (1 << 1)
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#define TIM_EGR_UG (1 << 0)
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/* TIM2 */
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#define TIM2_CR1 *(unsigned char*)0x5300
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#if defined STM8S105 || defined STM8S103
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#define TIM2_IER *(unsigned char*)0x5301
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#define TIM2_SR1 *(unsigned char*)0x5302
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#define TIM2_SR2 *(unsigned char*)0x5303
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#define TIM2_EGR *(unsigned char*)0x5304
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#define TIM2_CCMR1 *(unsigned char*)0x5305
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#define TIM2_CCMR2 *(unsigned char*)0x5306
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#define TIM2_CCMR3 *(unsigned char*)0x5307
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#define TIM2_CCER1 *(unsigned char*)0x5308
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#define TIM2_CCER2 *(unsigned char*)0x5309
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#define TIM2_CNTRH *(unsigned char*)0x530A
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#define TIM2_CNTRL *(unsigned char*)0x530B
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#define TIM2_PSCR *(unsigned char*)0x530C
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#define TIM2_ARRH *(unsigned char*)0x530D
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#define TIM2_ARRL *(unsigned char*)0x530E
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#define TIM2_CCR1H *(unsigned char*)0x530F
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#define TIM2_CCR1L *(unsigned char*)0x5310
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#define TIM2_CCR2H *(unsigned char*)0x5311
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#define TIM2_CCR2L *(unsigned char*)0x5312
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#define TIM2_CCR3H *(unsigned char*)0x5313
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#define TIM2_CCR3L *(unsigned char*)0x5314
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#elif defined STM8S003
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#define TIM2_IER *(unsigned char*)0x5303
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#define TIM2_SR1 *(unsigned char*)0x5304
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#define TIM2_SR2 *(unsigned char*)0x5305
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#define TIM2_EGR *(unsigned char*)0x5306
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#define TIM2_CCMR1 *(unsigned char*)0x5307
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#define TIM2_CCMR2 *(unsigned char*)0x5308
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#define TIM2_CCMR3 *(unsigned char*)0x5309
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#define TIM2_CCER1 *(unsigned char*)0x530A
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#define TIM2_CCER2 *(unsigned char*)0x530B
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#define TIM2_CNTRH *(unsigned char*)0x530C
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#define TIM2_CNTRL *(unsigned char*)0x530D
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#define TIM2_PSCR *(unsigned char*)0x530E
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#define TIM2_ARRH *(unsigned char*)0x530F
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#define TIM2_ARRL *(unsigned char*)0x5310
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#define TIM2_CCR1H *(unsigned char*)0x5311
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#define TIM2_CCR1L *(unsigned char*)0x5312
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#define TIM2_CCR2H *(unsigned char*)0x5313
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#define TIM2_CCR2L *(unsigned char*)0x5314
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#define TIM2_CCR3H *(unsigned char*)0x5315
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#define TIM2_CCR3L *(unsigned char*)0x5316
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#endif
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/* TIM3 */
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#if defined STM8S105 || defined STM8S103
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#define TIM3_CR1 *(unsigned char*)0x5320
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#define TIM3_IER *(unsigned char*)0x5321
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#define TIM3_SR1 *(unsigned char*)0x5322
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#define TIM3_SR2 *(unsigned char*)0x5323
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#define TIM3_EGR *(unsigned char*)0x5324
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#define TIM3_CCMR1 *(unsigned char*)0x5325
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#define TIM3_CCMR2 *(unsigned char*)0x5326
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#define TIM3_CCER1 *(unsigned char*)0x5327
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#define TIM3_CNTRH *(unsigned char*)0x5328
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#define TIM3_CNTRL *(unsigned char*)0x5329
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#define TIM3_PSCR *(unsigned char*)0x532A
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#define TIM3_ARRH *(unsigned char*)0x532B
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#define TIM3_ARRL *(unsigned char*)0x532C
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#define TIM3_CCR1H *(unsigned char*)0x532D
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#define TIM3_CCR1L *(unsigned char*)0x532E
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#define TIM3_CCR2H *(unsigned char*)0x532F
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#define TIM3_CCR2L *(unsigned char*)0x5330
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#endif
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|
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/* TIM4 */
|
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#define TIM4_CR1 *(unsigned char*)0x5340
|
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#if defined STM8S105 || defined STM8S103
|
|
#define TIM4_IER *(unsigned char*)0x5341
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#define TIM4_SR *(unsigned char*)0x5342
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#define TIM4_EGR *(unsigned char*)0x5343
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#define TIM4_CNTR *(unsigned char*)0x5344
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#define TIM4_PSCR *(unsigned char*)0x5345
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#define TIM4_ARR *(unsigned char*)0x5346
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#elif defined STM8S003
|
|
#define TIM4_IER *(unsigned char*)0x5343
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|
#define TIM4_SR *(unsigned char*)0x5344
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|
#define TIM4_EGR *(unsigned char*)0x5345
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#define TIM4_CNTR *(unsigned char*)0x5346
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#define TIM4_PSCR *(unsigned char*)0x5347
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#define TIM4_ARR *(unsigned char*)0x5348
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#endif
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/* ------------------- ADC ------------------- */
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|
#define ADC_DB0RH *(unsigned char*)0x53E0
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#define ADC_DB0RL *(unsigned char*)0x53E1
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#define ADC_DB1RH *(unsigned char*)0x53E2
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|
#define ADC_DB1RL *(unsigned char*)0x53E3
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#define ADC_DB2RH *(unsigned char*)0x53E4
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#define ADC_DB2RL *(unsigned char*)0x53E5
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#define ADC_DB3RH *(unsigned char*)0x53E6
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#define ADC_DB3RL *(unsigned char*)0x53E7
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#define ADC_DB4RH *(unsigned char*)0x53E8
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#define ADC_DB4RL *(unsigned char*)0x53E9
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#define ADC_DB5RH *(unsigned char*)0x53EA
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#define ADC_DB5RL *(unsigned char*)0x53EB
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#define ADC_DB6RH *(unsigned char*)0x53EC
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#define ADC_DB6RL *(unsigned char*)0x53ED
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#define ADC_DB7RH *(unsigned char*)0x53EE
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|
#define ADC_DB7RL *(unsigned char*)0x53EF
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#define ADC_DB8RH *(unsigned char*)0x53F0
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#define ADC_DB8RL *(unsigned char*)0x53F1
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#define ADC_DB9RH *(unsigned char*)0x53F2
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#define ADC_DB9RL *(unsigned char*)0x53F3
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#define ADC_CSR *(unsigned char*)0x5400
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|
#define ADC_CR1 *(unsigned char*)0x5401
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#define ADC_CR2 *(unsigned char*)0x5402
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|
#define ADC_CR3 *(unsigned char*)0x5403
|
|
#define ADC_DRH *(unsigned char*)0x5404
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|
#define ADC_DRL *(unsigned char*)0x5405
|
|
#define ADC_TDRH *(unsigned char*)0x5406
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|
#define ADC_TDRL *(unsigned char*)0x5407
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|
#define ADC_HTRH *(unsigned char*)0x5408
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|
#define ADC_HTRL *(unsigned char*)0x5409
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|
#define ADC_LTRH *(unsigned char*)0x540A
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|
#define ADC_LTRL *(unsigned char*)0x540B
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|
#define ADC_AWSRH *(unsigned char*)0x540C
|
|
#define ADC_AWSRL *(unsigned char*)0x540D
|
|
#define ADC_AWCRH *(unsigned char*)0x540E
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|
#define ADC_AWCRL *(unsigned char*)0x540F
|
|
|
|
/* ------------------- swim control ------------------- */
|
|
#define CFG_GCR *(unsigned char*)0x7F60
|
|
#define SWIM_CSR *(unsigned char*)0x7F80
|
|
|
|
/* ------------------- ITC ------------------- */
|
|
#define ITC_SPR1 *(unsigned char*)0x7F70
|
|
#define ITC_SPR2 *(unsigned char*)0x7F71
|
|
#define ITC_SPR3 *(unsigned char*)0x7F72
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|
#define ITC_SPR4 *(unsigned char*)0x7F73
|
|
#define ITC_SPR5 *(unsigned char*)0x7F74
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|
#define ITC_SPR6 *(unsigned char*)0x7F75
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|
#define ITC_SPR7 *(unsigned char*)0x7F76
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|
#define ITC_SPR8 *(unsigned char*)0x7F77
|
|
|
|
|
|
/* -------------------- UNIQUE ID -------------------- */
|
|
#if defined STM8S105 || defined STM8S103 // maybe some other MCU have this too???
|
|
#define U_ID00 (unsigned char*)0x48CD
|
|
#define U_ID01 (unsigned char*)0x48CE
|
|
#define U_ID02 (unsigned char*)0x48CF
|
|
#define U_ID03 (unsigned char*)0x48D0
|
|
#define U_ID04 (unsigned char*)0x48D1
|
|
#define U_ID05 (unsigned char*)0x48D2
|
|
#define U_ID06 (unsigned char*)0x48D3
|
|
#define U_ID07 (unsigned char*)0x48D4
|
|
#define U_ID08 (unsigned char*)0x48D5
|
|
#define U_ID09 (unsigned char*)0x48D6
|
|
#define U_ID10 (unsigned char*)0x48D7
|
|
#define U_ID11 (unsigned char*)0x48D8
|
|
#endif // defined STM8S105 || defined STM8S103
|
|
|
|
// CCR REGISTER: bits 3&5 should be 1 if you wanna change EXTI_CRx
|
|
#define CCR *(unsigned char*)0x7F0A
|
|
|
|
/* -------------------- OPTION BYTES -------------------- */
|
|
#if defined STM8S105
|
|
// readout protection
|
|
#define OPT0 *(unsigned char*)0x4800
|
|
// user boot code
|
|
#define OPT1 *(unsigned char*)0x4801
|
|
#define NOPT1 *(unsigned char*)0x4802
|
|
// alternate functions remapping
|
|
// | AFR7 | ... | AFR0 |
|
|
// AFR7 - PD4 = BEEP; AFR6 - PB4/PB5 = I2C; AFR5 - PB0..3 - TIM1
|
|
// AFR4 - PD7 = TIM1_CH4; AFR3 - PD0 = TIM1_BKIN
|
|
// AFR2 - PD0 = CLK_CCO; AFR1 - PA3 = TIM3_CH1, PD2 = TIM2_CH3
|
|
// AFR0 - PD3 = ADC_ETR
|
|
#define OPT2 *(unsigned char*)0x4803
|
|
#define NOPT2 *(unsigned char*)0x4804
|
|
// trim, watchdog
|
|
#define OPT3 *(unsigned char*)0x4805
|
|
#define NOPT3 *(unsigned char*)0x4806
|
|
// extclc, awu
|
|
#define OPT4 *(unsigned char*)0x4807
|
|
#define NOPT4 *(unsigned char*)0x4808
|
|
// HSE stab time
|
|
#define OPT5 *(unsigned char*)0x4809
|
|
#define NOPT5 *(unsigned char*)0x480a
|
|
// none
|
|
#define OPT6 *(unsigned char*)0x480b
|
|
#define NOPT6 *(unsigned char*)0x480c
|
|
// none
|
|
#define OPT7 *(unsigned char*)0x480d
|
|
#define NOPT7 *(unsigned char*)0x480e
|
|
// bootloader opt byte
|
|
#define OPTBL *(unsigned char*)0x487e
|
|
#define NOPTBL *(unsigned char*)0x487f
|
|
|
|
#endif
|
|
|
|
#endif // __STM8L_H__
|
|
|
|
// #define *(unsigned char*)0x
|