mirror of
https://github.com/eddyem/STM8_samples.git
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143 lines
5.1 KiB
Plaintext
143 lines
5.1 KiB
Plaintext
EESchema-LIBRARY Version 2.4
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#encoding utf-8
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#
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# STM8S003K3T
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#
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DEF STM8S003K3T IC 0 40 Y Y 1 F N
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F0 "IC" -800 1150 60 H V C CNN
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F1 "STM8S003K3T" 550 -1100 60 H V C CNN
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F2 "" 0 0 60 H V C CNN
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F3 "" 0 0 60 H V C CNN
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$FPLIST
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LQFP32*
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$ENDFPLIST
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DRAW
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S -850 1100 850 -1050 0 1 10 f
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X NRST 1 -1000 1000 149 R 40 40 1 1 I
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X PB6 10 1000 50 149 L 40 40 1 1 B
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X I2C_SDA/PB5 11 1000 150 149 L 40 40 1 1 B
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X I2C_SCL/PB4 12 1000 250 149 L 40 40 1 1 B
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X TIM1_ETR/AIN3/PB3 13 1000 350 149 L 40 40 1 1 B
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X TIM1_CH3N/AIN2/PB2 14 1000 450 149 L 40 40 1 1 B
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X TIM1_CH2N/AIN1/PB1 15 1000 550 149 L 40 40 1 1 B
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X TIM1_CH1N/AIN0/PB0 16 1000 650 149 L 40 40 1 1 B
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X PE5/SPI_NSS 17 -1000 -200 148 R 40 40 1 1 B
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X UART1_CK/TIM1_CH1/PC1 18 1000 -200 149 L 40 40 1 1 B
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X TIM1_CH2/PC2 19 1000 -300 149 L 40 40 1 1 B
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X OSCI/PA1 2 1000 1000 149 L 40 40 1 1 B
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X TIM1_CH3/PC3 20 1000 -400 149 L 40 40 1 1 B
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X CLK_CCO/TIM1_CH4/PC4 21 1000 -500 149 L 40 40 1 1 B
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X SPI_SCK/PC5 22 1000 -600 149 L 40 40 1 1 B
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X PI_MOSI/PC6 23 1000 -700 149 L 40 40 1 1 B
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X PI_MISO/PC7 24 1000 -800 149 L 40 40 1 1 B
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X PD0/TIM1_BKIN[CLK_CCO] 25 -1000 650 148 R 40 40 1 1 B
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X PD1/SWIM 26 -1000 550 149 R 40 40 1 1 B
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X PD2[TIM2_CH3] 27 -1000 450 149 R 40 40 1 1 B
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X PD3/ADC_ETR/TIM2_CH2 28 -1000 350 149 R 40 40 1 1 B
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X PD4/BEEP/TIM2_CH1 29 -1000 250 149 R 40 40 1 1 B
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X OSCOUT/PA2 3 1000 900 149 L 40 40 1 1 B
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X PD5/UART1_TX 30 -1000 150 149 R 40 40 1 1 B
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X PD6/UART1_RX 31 -1000 50 149 R 40 40 1 1 B
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X PD7/TLI[TIM1_CH4] 32 -1000 -50 148 R 40 40 1 1 B
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X VSS 4 0 -1200 149 U 40 40 1 1 W
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X Vcap 5 -1000 -950 149 R 40 40 1 1 I
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X VDD 6 0 1250 149 D 40 40 1 1 W
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X [SPI_NSS]TIM2_CH3/PA3 7 1000 800 149 L 40 40 1 1 B
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X PF4 8 -1000 -350 149 R 40 40 1 1 B
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X PB7 9 1000 -50 149 L 40 40 1 1 B
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ENDDRAW
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ENDDEF
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#
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# STM8S105K4T6C
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#
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DEF STM8S105K4T6C U 0 40 Y Y 1 F N
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F0 "U" 0 1050 60 H V C CNN
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F1 "STM8S105K4T6C" 50 -850 60 H V C CNN
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F2 "" 0 0 60 H V C CNN
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F3 "" 0 0 60 H V C CNN
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ALIAS stm8s105*
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$FPLIST
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lqfp32*
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$ENDFPLIST
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DRAW
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S -1100 950 1100 -750 0 1 0 N
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X NRST 1 -1400 850 300 R 50 50 1 1 I
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X VSSA 10 -1400 -50 300 R 50 50 1 1 W
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X PB5/AIN5[I2X_SDA] 11 -1400 -150 300 R 50 50 1 1 T
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X PB4/AIN4[I2C_SCL] 12 -1400 -250 300 R 50 50 1 1 T
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X PB3/AIN3[TIM1_ETR] 13 -1400 -350 300 R 50 50 1 1 T
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X PB2/AIN2[TIM1_CH3N] 14 -1400 -450 300 R 50 50 1 1 T
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X PB1/AIN1_[TIM1_CH2N] 15 -1400 -550 300 R 50 50 1 1 T
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X PB0/AIN0_[TIM1_CH1N] 16 -1400 -650 300 R 50 50 1 1 T
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X PE5/SPI_NSS 17 1400 -650 300 L 50 50 1 1 T
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X PC1(HS)/TIM1_CH1 18 1400 -550 300 L 50 50 1 1 T
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X PC2(HS)/TIM1_CH2 19 1400 -450 300 L 50 50 1 1 T
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X OSCIN/PA1 2 -1400 750 300 R 50 50 1 1 T
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X PC3(HS)/TIM1_CH3 20 1400 -350 300 L 50 50 1 1 T
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X PC4(HS)/TIM1_CH4 21 1400 -250 300 L 50 50 1 1 T
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X PC5(HS)/SPI_SCK 22 1400 -150 300 L 50 50 1 1 T
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X PC6(HS)/SPI_MOSI 23 1400 -50 300 L 50 50 1 1 T
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X PC7(HS)/SPI_MISO 24 1400 50 300 L 50 50 1 1 T
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X PD0(HS)/TIM3_CH2[TIM1_BKIN][CLK_CCO] 25 1400 150 300 L 50 50 1 1 T
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X PD1(HS)/SWIM 26 1400 250 300 L 50 50 1 1 T
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X PD2(HS)/TIM3_CH1[TIM2_CH3] 27 1400 350 300 L 50 50 1 1 T
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X PD3(HS)/TIM2_CH2[ADC_ETR] 28 1400 450 300 L 50 50 1 1 T
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X PD4(HS)/TIM2_CH1[BEEP] 29 1400 550 300 L 50 50 1 1 T
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X OSCOUT/PA2 3 -1400 650 300 R 50 50 1 1 T
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X PD5/UART2_TX 30 1400 650 300 L 50 50 1 1 T
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X PD6/UART2_RX 31 1400 750 300 L 50 50 1 1 T
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X PD7/TLI[TIM1_CH4] 32 1400 850 300 L 50 50 1 1 T
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X VSS 4 -1400 550 300 R 50 50 1 1 W
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X VCAP 5 -1400 450 300 R 50 50 1 1 P
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X VDD(3.3-5v) 6 -1400 350 300 R 50 50 1 1 W
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X VDDio 7 -1400 250 300 R 50 50 1 1 W
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X PF4/AIN12 8 -1400 150 300 R 50 50 1 1 T
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X VDDA 9 -1400 50 300 R 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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# stm8s105board
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#
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DEF stm8s105board X 0 40 Y Y 1 F N
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F0 "X" 0 1050 60 H V C CNN
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F1 "stm8s105board" 0 -650 60 H V C CNN
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F2 "devboard_pins-9-14" 0 0 60 H I C CNN
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F3 "" 0 0 60 H V C CNN
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$FPLIST
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stm8s105board
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$ENDFPLIST
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DRAW
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S -1100 950 1100 -550 0 1 0 N
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X VDD(3.3-5v) 1 -1400 850 300 R 50 50 1 1 W
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X PB2/AIN2[TIM1_CH3N] 10 -1400 -50 300 R 50 50 1 1 T
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X PB1/AIN1_[TIM1_CH2N] 11 -1400 -150 300 R 50 50 1 1 T
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X PB0/AIN0_[TIM1_CH1N] 12 -1400 -250 300 R 50 50 1 1 T
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X PE5/SPI_NSS 13 -1400 -350 300 R 50 50 1 1 T
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X PC1(HS)/TIM1_CH1 14 -1400 -450 300 R 50 50 1 1 T
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X PC2(HS)/TIM1_CH2 15 1400 -450 300 L 50 50 1 1 T
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X PC3(HS)/TIM1_CH3 16 1400 -350 300 L 50 50 1 1 T
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X PC4(HS)/TIM1_CH4 17 1400 -250 300 L 50 50 1 1 T
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X PC5(HS)/SPI_SCK 18 1400 -150 300 L 50 50 1 1 T
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X PC6(HS)/SPI_MOSI 19 1400 -50 300 L 50 50 1 1 T
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X GND 2 -1400 750 300 R 50 50 1 1 W
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X PC7(HS)/SPI_MISO 20 1400 50 300 L 50 50 1 1 T
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X PD0(HS)/TIM3_CH2[TIM1_BKIN][CLK_CCO] 21 1400 150 300 L 50 39 1 1 T
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X PD1(HS)/SWIM 22 1400 250 300 L 50 50 1 1 T
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X PD2(HS)/TIM3_CH1[TIM2_CH3] 23 1400 350 300 L 50 50 1 1 T
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X PD3(HS)/TIM2_CH2[ADC_ETR] 24 1400 450 300 L 50 50 1 1 T
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X PD4(HS)/TIM2_CH1[BEEP] 25 1400 550 300 L 50 50 1 1 T
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X PD5/UART2_TX 26 1400 650 300 L 50 50 1 1 T
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X PD6/UART2_RX 27 1400 750 300 L 50 50 1 1 T
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X PD7/TLI[TIM1_CH4] 28 1400 850 300 L 50 50 1 1 T
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X NRST 3 -1400 650 300 R 50 50 1 1 I
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X OSCIN/PA1 4 -1400 550 300 R 50 50 1 1 T
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X OSCOUT/PA2 5 -1400 450 300 R 50 50 1 1 T
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X PF4/AIN12 6 -1400 350 300 R 50 50 1 1 T
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X PB5/AIN5[I2X_SDA] 7 -1400 250 300 R 50 50 1 1 T
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X PB4/AIN4[I2C_SCL] 8 -1400 150 300 R 50 50 1 1 T
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X PB3/AIN3[TIM1_ETR] 9 -1400 50 300 R 50 50 1 1 T
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ENDDRAW
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ENDDEF
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#
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#End Library
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