mirror of
https://github.com/eddyem/STM8_samples.git
synced 2025-12-06 10:45:12 +03:00
modified DRUM schematics
This commit is contained in:
Eddy
parent
64d8bfdb78
commit
cb0a628165
@ -32,6 +32,7 @@ LIBS:valves
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LIBS:stm8s105k4t6c
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LIBS:tda2822
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LIBS:CD74HC154
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LIBS:transistors_gaui
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LIBS:drum-cache
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EELAYER 27 0
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EELAYER END
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@ -39,7 +40,7 @@ $Descr A4 11693 8268
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Sheet 2 3
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Title ""
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Date "28 jul 2014"
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Date "20 sep 2014"
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Rev ""
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Comp ""
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Comment1 ""
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@ -48,10 +49,10 @@ Comment3 ""
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||||
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||||
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||||
F 2 "" H 3950 1750 60 0000 C CNN
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||||
F 3 "" H 3950 1750 60 0000 C CNN
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@ -59,10 +60,10 @@ F 3 "" H 3950 1750 60 0000 C CNN
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F 3 "" H 3750 2950 60 0000 C CNN
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||||
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||||
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||||
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||||
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||||
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@ -92,10 +93,10 @@ F 3 "" H 1900 3600 60 0000 C CNN
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@ -103,10 +104,10 @@ F 3 "" H 1900 3900 60 0000 C CNN
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||||
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||||
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||||
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||||
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||||
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@ -114,10 +115,10 @@ F 3 "" H 1900 4200 60 0000 C CNN
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F 2 "" H 1900 4500 60 0000 C CNN
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F 3 "" H 1900 4500 60 0000 C CNN
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@ -125,10 +126,10 @@ F 3 "" H 1900 4500 60 0000 C CNN
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||||
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L LED D9
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F 1 "LED" H 1900 4700 50 0000 C CNN
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F 2 "" H 1900 4800 60 0000 C CNN
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F 3 "" H 1900 4800 60 0000 C CNN
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@ -136,10 +137,10 @@ F 3 "" H 1900 4800 60 0000 C CNN
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-1 0 0 -1
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||||
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L LED D10
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||||
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F 2 "" H 1900 5100 60 0000 C CNN
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F 3 "" H 1900 5100 60 0000 C CNN
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@ -147,10 +148,10 @@ F 3 "" H 1900 5100 60 0000 C CNN
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-1 0 0 -1
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||||
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||||
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L BATTERY BT1
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F 2 "" H 3050 900 60 0000 C CNN
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F 3 "" H 3050 900 60 0000 C CNN
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@ -158,10 +159,10 @@ F 3 "" H 3050 900 60 0000 C CNN
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1 0 0 -1
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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F 2 "" H 3350 1000 60 0000 C CNN
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F 3 "" H 3350 1000 60 0000 C CNN
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@ -195,10 +196,10 @@ Wire Wire Line
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Wire Wire Line
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1700 5100 1500 5100
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L SPST SW6
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||||
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||||
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F 2 "" H 2150 900 60 0000 C CNN
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F 3 "" H 2150 900 60 0000 C CNN
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@ -210,10 +211,10 @@ VCC
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Wire Wire Line
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1500 900 1650 900
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||||
$Comp
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||||
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F 1 "GND" H 3550 2030 30 0001 C CNN
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F 2 "" H 3550 2100 60 0000 C CNN
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F 3 "" H 3550 2100 60 0000 C CNN
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@ -231,10 +232,10 @@ Wire Wire Line
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Wire Wire Line
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4050 2500 4050 3150
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$Comp
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||||
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L GND #PWR31
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||||
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||||
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F 3 "" H 4050 3150 60 0000 C CNN
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@ -251,10 +252,10 @@ Wire Wire Line
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Wire Wire Line
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3450 2950 3350 2950
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||||
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||||
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||||
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F 2 "" H 1950 1750 60 0000 C CNN
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@ -262,10 +263,10 @@ F 3 "" H 1950 1750 60 0000 C CNN
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||||
1 0 0 -1
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||||
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||||
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@ -273,10 +274,10 @@ F 3 "" H 1950 2100 60 0000 C CNN
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1 0 0 -1
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||||
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||||
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||||
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@ -284,10 +285,10 @@ F 3 "" H 1950 2500 60 0000 C CNN
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1 0 0 -1
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||||
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||||
L SW_PUSH SW?
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L SW_PUSH SW5
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||||
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||||
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||||
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F 1 "SW_PUSH" H 1950 2770 50 0000 C CNN
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F 2 "" H 1950 2850 60 0000 C CNN
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F 3 "" H 1950 2850 60 0000 C CNN
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@ -318,10 +319,10 @@ Wire Wire Line
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Wire Wire Line
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1500 2850 1650 2850
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$Comp
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||||
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L GND #PWR27
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U 1 1 53D6A2BE
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F 0 "#PWR?" H 1650 1200 30 0001 C CNN
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@ -351,10 +352,10 @@ Connection ~ 2100 5100
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Wire Wire Line
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||||
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@ -379,10 +380,10 @@ Break here\nand connect to GROUND!
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||||
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F 2 "" H 2100 1400 60 0000 C CNN
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F 3 "" H 2100 1400 60 0000 C CNN
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@ -32,6 +32,7 @@ LIBS:valves
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LIBS:stm8s105k4t6c
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LIBS:tda2822
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LIBS:CD74HC154
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LIBS:transistors_gaui
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LIBS:drum-cache
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EELAYER 27 0
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||||
EELAYER END
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@ -39,7 +40,7 @@ $Descr A4 11693 8268
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encoding utf-8
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Sheet 3 3
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Title ""
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Date "28 jul 2014"
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Date "20 sep 2014"
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Rev ""
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Comp ""
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Comment1 ""
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@ -48,21 +49,10 @@ Comment3 ""
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1 1700 2050
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@ -71,78 +61,6 @@ F 3 "" H 1450 4300 60 0000 C CNN
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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BTN0a
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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1600 5100 1200 5100
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
1 1750 2350
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1200 2250 1400 2250
|
||||
Wire Wire Line
|
||||
1400 2850 1200 2850
|
||||
$Comp
|
||||
L CONN_2 P7
|
||||
U 1 1 541D2C5F
|
||||
P 1750 2750
|
||||
F 0 "P7" V 1700 2750 40 0000 C CNN
|
||||
F 1 "CONN_2" V 1800 2750 40 0000 C CNN
|
||||
F 2 "" H 1750 2750 60 0000 C CNN
|
||||
F 3 "" H 1750 2750 60 0000 C CNN
|
||||
1 1750 2750
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1200 2650 1400 2650
|
||||
Wire Wire Line
|
||||
1400 3250 1200 3250
|
||||
$Comp
|
||||
L CONN_2 P8
|
||||
U 1 1 541D2C67
|
||||
P 1750 3150
|
||||
F 0 "P8" V 1700 3150 40 0000 C CNN
|
||||
F 1 "CONN_2" V 1800 3150 40 0000 C CNN
|
||||
F 2 "" H 1750 3150 60 0000 C CNN
|
||||
F 3 "" H 1750 3150 60 0000 C CNN
|
||||
1 1750 3150
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1200 3050 1400 3050
|
||||
Wire Wire Line
|
||||
1400 3650 1200 3650
|
||||
$Comp
|
||||
L CONN_2 P9
|
||||
U 1 1 541D2C6F
|
||||
P 1750 3550
|
||||
F 0 "P9" V 1700 3550 40 0000 C CNN
|
||||
F 1 "CONN_2" V 1800 3550 40 0000 C CNN
|
||||
F 2 "" H 1750 3550 60 0000 C CNN
|
||||
F 3 "" H 1750 3550 60 0000 C CNN
|
||||
1 1750 3550
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
1200 3450 1400 3450
|
||||
Text Notes 900 1500 0 60 ~ 0
|
||||
Buttons' contacts mark:\n"a" - inner circle;\n"b" - outern ring
|
||||
$EndSCHEMATC
|
||||
|
||||
101
DRUM/schematics/drum.kicad_pcb
Normal file
101
DRUM/schematics/drum.kicad_pcb
Normal file
@ -0,0 +1,101 @@
|
||||
(kicad_pcb (version 3) (host pcbnew "(2013-may-18)-stable")
|
||||
|
||||
(general
|
||||
(links 0)
|
||||
(no_connects 0)
|
||||
(area 0 0 0 0)
|
||||
(thickness 1.6)
|
||||
(drawings 0)
|
||||
(tracks 0)
|
||||
(zones 0)
|
||||
(modules 0)
|
||||
(nets 1)
|
||||
)
|
||||
|
||||
(page A3)
|
||||
(layers
|
||||
(15 F.Cu signal)
|
||||
(0 B.Cu signal)
|
||||
(16 B.Adhes user)
|
||||
(17 F.Adhes user)
|
||||
(18 B.Paste user)
|
||||
(19 F.Paste user)
|
||||
(20 B.SilkS user)
|
||||
(21 F.SilkS user)
|
||||
(22 B.Mask user)
|
||||
(23 F.Mask user)
|
||||
(24 Dwgs.User user)
|
||||
(25 Cmts.User user)
|
||||
(26 Eco1.User user)
|
||||
(27 Eco2.User user)
|
||||
(28 Edge.Cuts user)
|
||||
)
|
||||
|
||||
(setup
|
||||
(last_trace_width 0.254)
|
||||
(trace_clearance 0.254)
|
||||
(zone_clearance 0.508)
|
||||
(zone_45_only no)
|
||||
(trace_min 0.254)
|
||||
(segment_width 0.2)
|
||||
(edge_width 0.1)
|
||||
(via_size 0.889)
|
||||
(via_drill 0.635)
|
||||
(via_min_size 0.889)
|
||||
(via_min_drill 0.508)
|
||||
(uvia_size 0.508)
|
||||
(uvia_drill 0.127)
|
||||
(uvias_allowed no)
|
||||
(uvia_min_size 0.508)
|
||||
(uvia_min_drill 0.127)
|
||||
(pcb_text_width 0.3)
|
||||
(pcb_text_size 1.5 1.5)
|
||||
(mod_edge_width 0.15)
|
||||
(mod_text_size 1 1)
|
||||
(mod_text_width 0.15)
|
||||
(pad_size 1.5 1.5)
|
||||
(pad_drill 0.6)
|
||||
(pad_to_mask_clearance 0)
|
||||
(aux_axis_origin 0 0)
|
||||
(visible_elements FFFFFFBF)
|
||||
(pcbplotparams
|
||||
(layerselection 3178497)
|
||||
(usegerberextensions true)
|
||||
(excludeedgelayer true)
|
||||
(linewidth 0.150000)
|
||||
(plotframeref false)
|
||||
(viasonmask false)
|
||||
(mode 1)
|
||||
(useauxorigin false)
|
||||
(hpglpennumber 1)
|
||||
(hpglpenspeed 20)
|
||||
(hpglpendiameter 15)
|
||||
(hpglpenoverlay 2)
|
||||
(psnegative false)
|
||||
(psa4output false)
|
||||
(plotreference true)
|
||||
(plotvalue true)
|
||||
(plotothertext true)
|
||||
(plotinvisibletext false)
|
||||
(padsonsilk false)
|
||||
(subtractmaskfromsilk false)
|
||||
(outputformat 1)
|
||||
(mirror false)
|
||||
(drillshape 1)
|
||||
(scaleselection 1)
|
||||
(outputdirectory ""))
|
||||
)
|
||||
|
||||
(net 0 "")
|
||||
|
||||
(net_class Default "This is the default net class."
|
||||
(clearance 0.254)
|
||||
(trace_width 0.254)
|
||||
(via_dia 0.889)
|
||||
(via_drill 0.635)
|
||||
(uvia_dia 0.508)
|
||||
(uvia_drill 0.127)
|
||||
(add_net "")
|
||||
)
|
||||
|
||||
)
|
||||
@ -1,5 +1,5 @@
|
||||
update=Пн 28 июл 2014 17:50:54
|
||||
last_client=eeschema
|
||||
update=Сб 20 сен 2014 10:42:55
|
||||
last_client=pcbnew
|
||||
[general]
|
||||
version=1
|
||||
[eeschema]
|
||||
@ -44,3 +44,42 @@ LibName30=valves
|
||||
LibName31=stm8s105k4t6c
|
||||
LibName32=tda2822
|
||||
LibName33=CD74HC154
|
||||
LibName34=transistors_gaui
|
||||
[pcbnew]
|
||||
version=1
|
||||
LastNetListRead=
|
||||
UseCmpFile=1
|
||||
PadDrill=" 0.600000"
|
||||
PadDrillOvalY=" 0.600000"
|
||||
PadSizeH=" 1.500000"
|
||||
PadSizeV=" 1.500000"
|
||||
PcbTextSizeV=" 1.500000"
|
||||
PcbTextSizeH=" 1.500000"
|
||||
PcbTextThickness=" 0.300000"
|
||||
ModuleTextSizeV=" 1.000000"
|
||||
ModuleTextSizeH=" 1.000000"
|
||||
ModuleTextSizeThickness=" 0.150000"
|
||||
SolderMaskClearance=" 0.000000"
|
||||
SolderMaskMinWidth=" 0.000000"
|
||||
DrawSegmentWidth=" 0.200000"
|
||||
BoardOutlineThickness=" 0.100000"
|
||||
ModuleOutlineThickness=" 0.150000"
|
||||
[pcbnew/libraries]
|
||||
LibDir=
|
||||
LibName1=sockets
|
||||
LibName2=connect
|
||||
LibName3=discret
|
||||
LibName4=pin_array
|
||||
LibName5=divers
|
||||
LibName6=smd_capacitors
|
||||
LibName7=smd_resistors
|
||||
LibName8=smd_crystal&oscillator
|
||||
LibName9=smd_dil
|
||||
LibName10=smd_transistors
|
||||
LibName11=libcms
|
||||
LibName12=display
|
||||
LibName13=led
|
||||
LibName14=dip_sockets
|
||||
LibName15=pga_sockets
|
||||
LibName16=valves
|
||||
LibName17=transistors_gaui
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user