mirror of
https://github.com/eddyem/STM8_samples.git
synced 2025-12-06 10:45:12 +03:00
1st code for "220"
This commit is contained in:
eddyem
parent
a73d83c640
commit
5f969490b3
BIN
220controlled_socket/src/220socket.bin
Normal file
BIN
220controlled_socket/src/220socket.bin
Normal file
Binary file not shown.
45
220controlled_socket/src/220socket.geany
Normal file
45
220controlled_socket/src/220socket.geany
Normal file
@ -0,0 +1,45 @@
|
|||||||
|
[editor]
|
||||||
|
line_wrapping=false
|
||||||
|
line_break_column=100
|
||||||
|
auto_continue_multiline=true
|
||||||
|
|
||||||
|
[file_prefs]
|
||||||
|
final_new_line=true
|
||||||
|
ensure_convert_new_lines=true
|
||||||
|
strip_trailing_spaces=true
|
||||||
|
replace_tabs=true
|
||||||
|
|
||||||
|
[indentation]
|
||||||
|
indent_width=4
|
||||||
|
indent_type=0
|
||||||
|
indent_hard_tab_width=4
|
||||||
|
detect_indent=false
|
||||||
|
detect_indent_width=false
|
||||||
|
indent_mode=3
|
||||||
|
|
||||||
|
[project]
|
||||||
|
name=220socket
|
||||||
|
base_path=/Big/Data/00__Electronics/STM8/220controlled_socket/src
|
||||||
|
|
||||||
|
[long line marker]
|
||||||
|
long_line_behaviour=1
|
||||||
|
long_line_column=100
|
||||||
|
|
||||||
|
[files]
|
||||||
|
current_page=0
|
||||||
|
FILE_NAME_0=333;Make;0;EUTF-8;1;1;0;%2FBig%2FData%2F00__Electronics%2FSTM8%2F220controlled_socket%2Fsrc%2FMakefile;0;4
|
||||||
|
FILE_NAME_1=5695;C;0;EUTF-8;0;1;0;%2FBig%2FData%2F00__Electronics%2FSTM8%2F220controlled_socket%2Fsrc%2Finterrupts.c;0;4
|
||||||
|
FILE_NAME_2=983;C;0;EUTF-8;0;1;0;%2FBig%2FData%2F00__Electronics%2FSTM8%2F220controlled_socket%2Fsrc%2Finterrupts.h;0;4
|
||||||
|
FILE_NAME_3=977;C;0;EUTF-8;0;1;0;%2FBig%2FData%2F00__Electronics%2FSTM8%2F220controlled_socket%2Fsrc%2Fhardware.c;0;4
|
||||||
|
FILE_NAME_4=2172;C;0;EUTF-8;0;1;0;%2FBig%2FData%2F00__Electronics%2FSTM8%2F220controlled_socket%2Fsrc%2Fhardware.h;0;4
|
||||||
|
FILE_NAME_5=3759;C;0;EUTF-8;0;1;0;%2FBig%2FData%2F00__Electronics%2FSTM8%2F220controlled_socket%2Fsrc%2Fmain.c;0;4
|
||||||
|
FILE_NAME_6=1897;C;0;EUTF-8;0;1;0;%2FBig%2FData%2F00__Electronics%2FSTM8%2F220controlled_socket%2Fsrc%2Fuart.c;0;4
|
||||||
|
FILE_NAME_7=1275;C;0;EUTF-8;0;1;0;%2FBig%2FData%2F00__Electronics%2FSTM8%2F220controlled_socket%2Fsrc%2Fuart.h;0;4
|
||||||
|
FILE_NAME_8=880;C;0;EUTF-8;0;1;0;%2FBig%2FData%2F00__Electronics%2FSTM8%2F220controlled_socket%2Fsrc%2Fstm8s.h;0;4
|
||||||
|
FILE_NAME_9=2641;C;0;EUTF-8;0;1;0;%2Fhome%2Feddy%2FDropbox%2FProjects%2FSTM8_samples%2Fvoltmeters%2Fsrc%2F3-digit%2Fmain.c;0;4
|
||||||
|
FILE_NAME_10=1285;C;0;EUTF-8;0;1;0;%2Fhome%2Feddy%2FDropbox%2FProjects%2FSTM8_samples%2Fvoltmeters%2Fsrc%2F3-digit%2Finterrupts.c;0;4
|
||||||
|
FILE_NAME_11=887;C;0;EUTF-8;0;1;0;%2Fhome%2Feddy%2FDropbox%2FProjects%2FSTM8_samples%2Fvoltmeters%2Fsrc%2F3-digit%2Finterrupts.h;0;4
|
||||||
|
FILE_NAME_12=1968;C;0;EUTF-8;0;1;0;%2Fhome%2Feddy%2FDropbox%2FProjects%2FSTM8_samples%2Fstepper_independent_bin%2Fmain.c;0;4
|
||||||
|
|
||||||
|
[VTE]
|
||||||
|
last_dir=/home/eddy/Docs/SAO/Cameras/FLI_camera/my/Mytakepic
|
||||||
98
220controlled_socket/src/220socket.ihx
Normal file
98
220controlled_socket/src/220socket.ihx
Normal file
@ -0,0 +1,98 @@
|
|||||||
|
:2080A00080808080808080808080808080805204AE5230F66B027B02A520274AAE5231F6FD
|
||||||
|
:2080C0006B017B02A4804D27FDAE52317B01F7AE00021F03C6002197725C00214F9572FBEE
|
||||||
|
:2080E000037B01F7C60020C10021260FC600204CC70020A1082604725F0020C60021A108A0
|
||||||
|
:208100002604725F00215B0480803501001FAE5400F6A43FF780AE5344F644241B90CE0021
|
||||||
|
:1E8120002472A90001C60023A90097C60022A9009590CF0024CF002235005344808072
|
||||||
|
:018B760000FE
|
||||||
|
:20813E00AE5230F64D2AF9AE52317B03F781AE5230F64D2AF9350A523181160390F64D2778
|
||||||
|
:20815E0018AE5230F64D2AF9AE5235F6AA08F790F6905CAE5231F720E3815202C60021C165
|
||||||
|
:20817E00002026034F20241605AE00021F01C6002097725C00204F9572FB01F690F7C6001A
|
||||||
|
:20819E0020A1082604725F0020A6015B028152255F1F031F017B2AA1042303CC82927B2A4B
|
||||||
|
:2081BE00A1032603CC82920D2A2603CC8292961C00051F124F5F9772FB127F4CA10C25F576
|
||||||
|
:2081DE001E12A60AE70A7B2AA101270E7B2AA10227197B2AA104272E20451E28F66B1F4F93
|
||||||
|
:2081FE005F6B031F017B1F6B042034162817201E20FE1F18161817240F230F22162417030F
|
||||||
|
:20821E001622170120191628171A1E1AE6036B17E6026B16FE1F141616170316141701A6DD
|
||||||
|
:20823E00096B114B0A5F894B001E07891E0789CD89FE5B08517B110A115F9772FB12909F64
|
||||||
|
:20825E00AB30F74B0A5F894B001E07891E0789CD8A955B081F0317011E0326041E0127062A
|
||||||
|
:20827E007B11A1FF2CBD7B114C5F9772FB1289CD81585B025B258152100F01965C5C1F0F03
|
||||||
|
:20829E001E0F1C000B7F0D132A14161590504F1214974F12139517151F13A6016B01A60B4D
|
||||||
|
:2082BE006B0E4B0A5F894B001E19891E1989CD89D95B089F0A0E5F417B0E4172FB0FAB3015
|
||||||
|
:2082DE00F74B0A5F894B001E19891E1989CD8A6E5B081F1517137B0EA1002C034F2002A68B
|
||||||
|
:2082FE00011E1526041E1327034D26B6417B0E414D27140D0127107B0E4A97905F619F61EC
|
||||||
|
:20831E0072F90FA62D90F74F9572FB0F89CD81585B12815217CE00241F09CE00221F075FF6
|
||||||
|
:20833E001F051F030F0E0F0C0F0B961C000D89CD81785B026B170D1727717B0DA12D260E54
|
||||||
|
:20835E001E05260A1E032606A6016B0E205D7B0DA13025797B0DA1392273A6016B0C1E0593
|
||||||
|
:20837E00891E05894B0A5F894B00CD8AEF5B081F1517137B0D0F115F90977B11909572F9D1
|
||||||
|
:20839E00159F19140219139572A200309FA20002A2009517051F03AE7FFF13054F12044F27
|
||||||
|
:2083BE00120324075F1F051F030F0B90CE002472F209C60023120895C6002212079790A34E
|
||||||
|
:2083DE0027109EA2009FA2002403CC83480D0B26040D0C26034F2014160517010D0E270588
|
||||||
|
:2083FE001E01501F011E1A1601FFA6015B1781AE848489CD81585B021E0389CD81585B02F9
|
||||||
|
:20841E004B0ACD813E84817B03A40F6B037B03887B04A10A842406AB306B032004AB576B01
|
||||||
|
:20843E00037B0381AE848D89CD81585B027B034EA40F88CD84255B0188CD813E847B03885A
|
||||||
|
:20845E00CD84255B0188CD813E8481AE5011F6AA20F7AE5012F6AA20F735685232350352DB
|
||||||
|
:12847E0033352C5235810A4552524F523A2000307800BA
|
||||||
|
:028B77000000FC
|
||||||
|
:2084900072107F60350050C635075347357D53483501534335855340350C5002350E5003BB
|
||||||
|
:2084B000352050073530500835F8500C35F8500D35045011350450123524540035105407AE
|
||||||
|
:0D84D0003508540235715401357154018195
|
||||||
|
:208000008200808382000000820080A0820080A1820080A2820080A3820080A4820080A57E
|
||||||
|
:20802000820080A6820080A78200000082000000820080A8820080A9820080AA820080AB3D
|
||||||
|
:20804000820080AC8200000082000000820080AD820080AE820081098200000082000000FF
|
||||||
|
:208060008200810A820081168200813D820000008200000082000000820000008200000010
|
||||||
|
:1D808300AE001E2707724F00005A26F9AE00072709D68B75D7001E5A26F7CC8080B9
|
||||||
|
:03808000CC873872
|
||||||
|
:2084DD005238AE000D1F0F1E0F5C5C1F371E37FE160F72A90004170D160D90FE17271327ED
|
||||||
|
:2084FD00230FCF000A1E371627FF1E0D90CE000AFF1E0F1C00081F0B1E0BFE160F72A9004F
|
||||||
|
:20851D000A172B162B90FE17211321230FCF000A1E0B1621FF1E2B90CE000AFF1E0F1C0054
|
||||||
|
:20853D000E1F171E17FE160F72A90010171F161F90FE17111311230FCF000A1E171611FFAC
|
||||||
|
:20855D001E1F90CE000AFF1E0FFE163790FE17011301230FCF000A1E0F1601FF1E3790CE27
|
||||||
|
:20857D00000AFF1E0F1C00061F091E09FE160B90FE171B131B230FCF000A1E09161BFF1EAA
|
||||||
|
:20859D000B90CE000AFF1E0F1C000C1F2D1E2DFE161790FE17031303230FCF000A1E2D160B
|
||||||
|
:2085BD0003FF1E1790CE000AFF1E37FE160D90FE17351335230FCF000A1E371635FF1E0D93
|
||||||
|
:2085DD0090CE000AFF1E0BFE162B90FE17131313230FCF000A1E0B1613FF1E2B90CE000AC4
|
||||||
|
:2085FD00FF1E17FE161F90FE17231323230FCF000A1E171623FF1E1F90CE000AFF1E0FFEB2
|
||||||
|
:20861D00160990FE17051305230FCF000A1E0F1605FF1E0990CE000AFF1E2BFE161F90FE72
|
||||||
|
:20863D00172F132F230FCF000A1E2B162FFF1E1F90CE000AFF1E0BFE161790FE17311331EB
|
||||||
|
:20865D00230FCF000A1E0B1631FF1E1790CE000AFF1E09FE162D90FE17191319230FCF0094
|
||||||
|
:20867D000A1E091619FF1E2D90CE000AFF1E37FE160B90FE17291329230FCF000A1E3716D8
|
||||||
|
:20869D0029FF1E0B90CE000AFF1E0DFE162B90FE17251325230FCF000A1E0D1625FF1E2BE0
|
||||||
|
:2086BD0090CE000AFF1E0BFE161790FE171D131D230FCF000A1E0B161DFF1E1790CE000AED
|
||||||
|
:2086DD00FF1E0BFE160D90FE17331333230FCF000A1E0B1633FF1E0D90CE000AFF1E2DFEBF
|
||||||
|
:2086FD00160B90FE17071307230FCF000A1E2D1607FF1E0B90CE000AFF1E0BFE160D90FE9C
|
||||||
|
:20871D0017151315230FCF000A1E0B1615FF1E0D90CE000AFF1E0BFE5B388152165F1F07D0
|
||||||
|
:20873D001F05AEFFFF1F035F1F0C5F1F155F1F0ACD8490CD84699A725D001F274AAE000D36
|
||||||
|
:20875D001F135FC6000C975872FB1390CE0001FFC6000C4CC7000CA1092624725F000C1EEC
|
||||||
|
:20877D000A5C1F0ACD84DD1F017B0D891102857B0C8912018524021F0C130324021F03728D
|
||||||
|
:20879D005F001F35715401CE002472F0071F10C6002312066B0FC6002212056B0EAE00C751
|
||||||
|
:2087BD0013104F120F4F120E2420CE00241F07CE00221F055F1F0A1E0C2707160C72F203C1
|
||||||
|
:2087DD0017155F1F0CAEFFFF1F03961C000989CD81785B024D2603CC87547B096B127B12E6
|
||||||
|
:2087FD00A143277C7B12A14827397B12A149273F7B12A1522603CC890D7B12A1532603CCA1
|
||||||
|
:20881D0088CC7B12A16327587B12A16827157B12A1722603CC890D7B12A1732603CC88CCF0
|
||||||
|
:20883D00CC8754AE895189CD81585B02CC87541E15541F01AE89B789CD81585B02965C4B5B
|
||||||
|
:20885D000289CD81AC5B03AE89C289CD81585B021E0A4B0289CD81AC5B03CD814CCC8754FC
|
||||||
|
:20887D00AE89CA89CD81585B027B09A1632604A6302002A63188CD813E844B3DCD813E849D
|
||||||
|
:20889D007B09A1632610AE5006F6A5102604A6312012A630200EAE5001F6A5022604A6317A
|
||||||
|
:2088BD002002A63088CD813E84CD814CCC87547B09A1732604A6302002A631AE89CD888924
|
||||||
|
:2088DD00CD81585B02CD813E84AE89D189CD81585B02AE5000F6887B0AA173842609AA085A
|
||||||
|
:2088FD00AE5000F7CC8754AA04AE5000F7CC87547B09A1722604A6302002A631AE89CD8859
|
||||||
|
:20891D0089CD81585B02CD813E84AE89D589CD81585B02AE5000F6887B0AA172842609A49B
|
||||||
|
:20893D00F7AE5000F7CC8754A4FBAE5000F7CC87545B16810A50524F544F3A0A632F432083
|
||||||
|
:20895D002D20636865636B20696E302F310A49202D2073686F772063757272656E74206103
|
||||||
|
:20897D006D706C2E2028414455290A732F53202D206163746976617465206F7574302F3153
|
||||||
|
:20899D000A722F52202D2064656163746976617465206F7574302F310A00496D617828412C
|
||||||
|
:1C89BD004455293D002C204E7074733D00496E004F7574003D310A003D300A0093
|
||||||
|
:048B790000000000F8
|
||||||
|
:2089D9001E0916072A03CD8B6B8990891E0916072A03CD8B6B899089CD89FE5B087B032A73
|
||||||
|
:2089F90003CD8B6B8152030F030F017B0A484F494D262E160C1E0A905859170C1F0A1E089D
|
||||||
|
:208A1900130C7B07120B7B06120A240D160C1E0A549056170C1F0A20080C017B016B0320A2
|
||||||
|
:208A3900CA7B036B021E0872F00C7B07120B90977B06120A25061F0890951706160C1E0A93
|
||||||
|
:208A5900549056170C1F0A7B020A024D26D71E0816065B03811E0916072A03CD8B6B899036
|
||||||
|
:208A7900891E0916072A03CD8B6B899089CD8A955B087B0318072A03CD8B6B8152065F1F4B
|
||||||
|
:208A9900051F03A6206B027B09484F496B01160B1E09905859170B1F0916051E0390585943
|
||||||
|
:208AB90017051F030D0127067B06AA016B061E0572F00F7B04120E90977B03120D250C1F40
|
||||||
|
:208AD90005909517037B0CAA016B0C0A0226B81E0B16095B06815F89897B0A977B0E421F05
|
||||||
|
:208AF900037B09977B0E4272FB021F024FA9006B017B0A977B0D4272FB021F024F19016B36
|
||||||
|
:208B1900017B0A977B0C4272FB011F017B09977B0D4272FB011F017B08977B0E4272FB0102
|
||||||
|
:208B39001F017B07977B0E429F1B016B017B0A977B0B429F1B016B017B09977B0C429F1B48
|
||||||
|
:1D8B5900016B017B08977B0D429F1B016B019085858190535D2703535C81905C8165
|
||||||
|
:00000001FF
|
||||||
37
220controlled_socket/src/Makefile
Normal file
37
220controlled_socket/src/Makefile
Normal file
@ -0,0 +1,37 @@
|
|||||||
|
NAME=220socket
|
||||||
|
SDCC=sdcc
|
||||||
|
|
||||||
|
CCFLAGS=-DSTM8S003 -I../ -I/usr/share/sdcc/include -mstm8 --out-fmt-ihx
|
||||||
|
LDFLAGS= -mstm8 --out-fmt-ihx -lstm8
|
||||||
|
FLASHFLAGS=-cstlinkv2 -pstm8s003
|
||||||
|
|
||||||
|
SRC=$(wildcard *.c)
|
||||||
|
|
||||||
|
OBJ=$(SRC:%.c=%.rel)
|
||||||
|
TRASH=$(OBJ) $(SRC:%.c=%.rst) $(SRC:%.c=%.asm) $(SRC:%.c=%.lst)
|
||||||
|
TRASH+=$(SRC:%.c=%.sym) $(NAME).lk $(NAME).map $(NAME).cdb
|
||||||
|
INDEPENDENT_HEADERS=../stm8l.h ports_definition.h Makefile
|
||||||
|
|
||||||
|
all: $(NAME).ihx
|
||||||
|
|
||||||
|
#$(SRC) : %.c : %.h $(INDEPENDENT_HEADERS)
|
||||||
|
# @touch $@
|
||||||
|
#
|
||||||
|
#%.h: ;
|
||||||
|
|
||||||
|
clean:
|
||||||
|
rm -f $(TRASH)
|
||||||
|
|
||||||
|
load: $(NAME).ihx
|
||||||
|
stm8flash $(FLASHFLAGS) -w $(NAME).ihx
|
||||||
|
|
||||||
|
%.rel: %.c
|
||||||
|
$(SDCC) $(CCFLAGS) -c $<
|
||||||
|
|
||||||
|
bin: $(NAME).ihx
|
||||||
|
objcopy -I ihex -O binary $< $(NAME).bin
|
||||||
|
|
||||||
|
$(NAME).ihx: $(OBJ)
|
||||||
|
$(SDCC) $(LDFLAGS) $(OBJ) -o $(NAME).ihx
|
||||||
|
|
||||||
|
.PHONY: clean load
|
||||||
80
220controlled_socket/src/hardware.c
Normal file
80
220controlled_socket/src/hardware.c
Normal file
@ -0,0 +1,80 @@
|
|||||||
|
/*
|
||||||
|
* geany_encoding=koi8-r
|
||||||
|
* hardware.c
|
||||||
|
*
|
||||||
|
* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301, USA.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#include "hardware.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* HW:
|
||||||
|
* PA1 - ~IN1 - PULLUP IN, optocouple input, 0 active
|
||||||
|
* PA2 - OUT1 - PUSHPULL OUT, optocouple output, 1 active
|
||||||
|
* PA3 - OUT0 - PUSHPULL OUT, optocouple output, 1 active
|
||||||
|
* PB4 - ~IN0 - PULLUP IN, direct input
|
||||||
|
* PB5 - PKEY1 - PUSHPULL OUT, 0 active
|
||||||
|
* PC3 - NKEY2 - PUSHPULL OUT, TIM1_CH3, 1 active
|
||||||
|
* PC4 - Relay1 - PUSHPULL OUT, turn ON relay 1, 1 active
|
||||||
|
* PC5 - NKEY1 - PUSHPULL OUT, TIM2_CH1, 1 active
|
||||||
|
* PC6 - Triac1 - PUSHPULL OUT, turn ON triac 1, 1 active
|
||||||
|
* PC7 - Relay0 - PUSHPULL OUT, turn ON relay 0, 1 active
|
||||||
|
* PD1 - swim - Not used
|
||||||
|
* PD2 - Triac0 - PUSHPULL OUT, turn ON triac 0, 1 active
|
||||||
|
* PD3 - Cur0 - AIN, channel 0 current measurement
|
||||||
|
* PD4 - NC - NC
|
||||||
|
* PD5 - Tx \ UART
|
||||||
|
* PD6 - Rx /
|
||||||
|
*/
|
||||||
|
|
||||||
|
void hw_init(){
|
||||||
|
CFG_GCR |= 1; // disable SWIM
|
||||||
|
// Configure clocking
|
||||||
|
CLK_CKDIVR = 0; // F_HSI = 16MHz, f_CPU = 16MHz
|
||||||
|
// Timer 4 (8 bit) used as system tick timer
|
||||||
|
// prescaler == 128 (2^7), Tfreq = 125kHz
|
||||||
|
// period = 1ms, so ARR = 125
|
||||||
|
TIM4_PSCR = 7;
|
||||||
|
TIM4_ARR = 125;
|
||||||
|
// interrupts: update
|
||||||
|
TIM4_IER = TIM_IER_UIE;
|
||||||
|
// auto-reload + interrupt on overflow + enable
|
||||||
|
TIM4_CR1 = TIM_CR1_APRE | TIM_CR1_URS | TIM_CR1_CEN;
|
||||||
|
|
||||||
|
// PA: 1 - PU IN, 2,3 - PP OUT
|
||||||
|
PA_DDR = GPIO_PIN2 | GPIO_PIN3;
|
||||||
|
PA_CR1 = GPIO_PIN1 | GPIO_PIN2 | GPIO_PIN3;
|
||||||
|
// PB: 4 - PU IN, 5 - PP OUT with 1 in default state
|
||||||
|
PB_DDR = GPIO_PIN5;
|
||||||
|
PB_CR1 = GPIO_PIN4 | GPIO_PIN5;
|
||||||
|
// PC: 3-7 - PP OUT
|
||||||
|
PC_DDR = GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7;
|
||||||
|
PC_CR1 = GPIO_PIN3 | GPIO_PIN4 | GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7;
|
||||||
|
// PD: 2 - PP OUT, 3 - AIN
|
||||||
|
PD_DDR = GPIO_PIN2;
|
||||||
|
PD_CR1 = GPIO_PIN2;
|
||||||
|
// configure ADC
|
||||||
|
// select PD3[AIN4] & enable interrupt for EOC
|
||||||
|
ADC_CSR = 0x24; // 0x24 - AIN4
|
||||||
|
ADC_TDRL = 0x10; // disable Schmitt triger for AIN4
|
||||||
|
// right alignment
|
||||||
|
ADC_CR2 = 0x08; // don't forget: first read ADC_DRL!
|
||||||
|
// f_{ADC} = f/18 & continuous non-buffered conversion & wake it up
|
||||||
|
ADC_CR1 = 0x71; // 0x71 - single, 0x73 - continuous
|
||||||
|
ADC_CR1 = 0x71; // turn on ADC (this needs second write operation)
|
||||||
|
}
|
||||||
67
220controlled_socket/src/hardware.h
Normal file
67
220controlled_socket/src/hardware.h
Normal file
@ -0,0 +1,67 @@
|
|||||||
|
/*
|
||||||
|
* ports_definition.h - definition of ports pins & so on
|
||||||
|
*
|
||||||
|
* Copyright 2018 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301, USA.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#pragma once
|
||||||
|
#ifndef __PORTS_DEFINITION_H__
|
||||||
|
#define __PORTS_DEFINITION_H__
|
||||||
|
|
||||||
|
#include "stm8s.h"
|
||||||
|
|
||||||
|
// macro for using in port constructions like PORT(LED_PORT, ODR) = xx
|
||||||
|
#define FORMPORT(a, b) a ## _ ## b
|
||||||
|
#define PORT(a, b) FORMPORT(a , b)
|
||||||
|
#define CONCAT(a, b) a ## b
|
||||||
|
|
||||||
|
/**
|
||||||
|
* HW:
|
||||||
|
* PA1 - ~IN1 - PULLUP IN, optocouple input, 0 active
|
||||||
|
* PA2 - OUT1 - PUSHPULL OUT, optocouple output, 1 active
|
||||||
|
* PA3 - OUT0 - PUSHPULL OUT, optocouple output, 1 active
|
||||||
|
* PB4 - ~IN0 - PULLUP IN, direct input, 0 active
|
||||||
|
* PB5 - PKEY1 - PUSHPULL OUT, 0 active
|
||||||
|
* PC3 - NKEY2 - PUSHPULL OUT, TIM1_CH3, 1 active
|
||||||
|
* PC4 - Relay1 - PUSHPULL OUT, turn ON relay 1, 1 active
|
||||||
|
* PC5 - NKEY1 - PUSHPULL OUT, TIM2_CH1, 1 active
|
||||||
|
* PC6 - Triac1 - PUSHPULL OUT, turn ON triac 1, 1 active
|
||||||
|
* PC7 - Relay0 - PUSHPULL OUT, turn ON relay 0, 1 active
|
||||||
|
* PD1 - swim - Not used
|
||||||
|
* PD2 - Triac0 - PUSHPULL OUT, turn ON triac 0, 1 active
|
||||||
|
* PD3 - Cur0 - AIN, channel 0 current measurement
|
||||||
|
* PD4 - NC - NC
|
||||||
|
* PD5 - Tx \ UART
|
||||||
|
* PD6 - Rx /
|
||||||
|
*/
|
||||||
|
// getters: 1 active, 0 inactive
|
||||||
|
#define CHK_IN0() ((PB_IDR & GPIO_PIN4) == 0)
|
||||||
|
#define CHK_IN1() ((PA_IDR & GPIO_PIN1) == 0)
|
||||||
|
#define SET_OUT0() PA_ODR |= GPIO_PIN3
|
||||||
|
#define SET_OUT1() PA_ODR |= GPIO_PIN2
|
||||||
|
#define RESET_OUT0() PA_ODR &= ~GPIO_PIN3
|
||||||
|
#define RESET_OUT1() PA_ODR &= ~GPIO_PIN2
|
||||||
|
|
||||||
|
// UART2_TX
|
||||||
|
#define UART_PORT PD
|
||||||
|
#define UART_TX_PIN GPIO_PIN5
|
||||||
|
|
||||||
|
|
||||||
|
void hw_init();
|
||||||
|
|
||||||
|
#endif // __PORTS_DEFINITION_H__
|
||||||
199
220controlled_socket/src/interrupts.c
Normal file
199
220controlled_socket/src/interrupts.c
Normal file
@ -0,0 +1,199 @@
|
|||||||
|
/*
|
||||||
|
* interrupts.c
|
||||||
|
*
|
||||||
|
* Copyright 2018 Edward V. Emelianoff <eddy@sao.ru>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301, USA.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "hardware.h"
|
||||||
|
#include "uart.h"
|
||||||
|
|
||||||
|
// Top Level Interrupt
|
||||||
|
INTERRUPT_HANDLER(TLI_IRQHandler, 0){}
|
||||||
|
|
||||||
|
// Auto Wake Up Interrupt
|
||||||
|
INTERRUPT_HANDLER(AWU_IRQHandler, 1){}
|
||||||
|
|
||||||
|
// Clock Controller Interrupt
|
||||||
|
INTERRUPT_HANDLER(CLK_IRQHandler, 2){}
|
||||||
|
|
||||||
|
// External Interrupt PORTA
|
||||||
|
INTERRUPT_HANDLER(EXTI_PORTA_IRQHandler, 3){}
|
||||||
|
|
||||||
|
// External Interrupt PORTB
|
||||||
|
INTERRUPT_HANDLER(EXTI_PORTB_IRQHandler, 4){}
|
||||||
|
|
||||||
|
// External Interrupt PORTC
|
||||||
|
INTERRUPT_HANDLER(EXTI_PORTC_IRQHandler, 5){
|
||||||
|
}
|
||||||
|
|
||||||
|
// External Interrupt PORTD
|
||||||
|
INTERRUPT_HANDLER(EXTI_PORTD_IRQHandler, 6){
|
||||||
|
}
|
||||||
|
|
||||||
|
// External Interrupt PORTE
|
||||||
|
INTERRUPT_HANDLER(EXTI_PORTE_IRQHandler, 7){}
|
||||||
|
|
||||||
|
#ifdef STM8S903
|
||||||
|
// External Interrupt PORTF
|
||||||
|
INTERRUPT_HANDLER(EXTI_PORTF_IRQHandler, 8){}
|
||||||
|
#endif // STM8S903
|
||||||
|
|
||||||
|
#if defined (STM8S208) || defined (STM8AF52Ax)
|
||||||
|
// CAN RX Interrupt routine.
|
||||||
|
INTERRUPT_HANDLER(CAN_RX_IRQHandler, 8){}
|
||||||
|
|
||||||
|
// CAN TX Interrupt routine.
|
||||||
|
INTERRUPT_HANDLER(CAN_TX_IRQHandler, 9){}
|
||||||
|
#endif // STM8S208 || STM8AF52Ax
|
||||||
|
|
||||||
|
// SPI Interrupt routine.
|
||||||
|
INTERRUPT_HANDLER(SPI_IRQHandler, 10){}
|
||||||
|
|
||||||
|
// Timer1 Update/Overflow/Trigger/Break Interrupt
|
||||||
|
INTERRUPT_HANDLER(TIM1_UPD_OVF_TRG_BRK_IRQHandler, 11){
|
||||||
|
}
|
||||||
|
|
||||||
|
// Timer1 Capture/Compare Interrupt routine.
|
||||||
|
INTERRUPT_HANDLER(TIM1_CAP_COM_IRQHandler, 12){}
|
||||||
|
|
||||||
|
#ifdef STM8S903
|
||||||
|
// Timer5 Update/Overflow/Break/Trigger Interrupt
|
||||||
|
INTERRUPT_HANDLER(TIM5_UPD_OVF_BRK_TRG_IRQHandler, 13){}
|
||||||
|
|
||||||
|
// Timer5 Capture/Compare Interrupt
|
||||||
|
INTERRUPT_HANDLER(TIM5_CAP_COM_IRQHandler, 14){}
|
||||||
|
|
||||||
|
#else // STM8S208, STM8S207, STM8S105 or STM8S103 or STM8AF62Ax or STM8AF52Ax or STM8AF626x
|
||||||
|
|
||||||
|
// Timer2 Update/Overflow/Break Interrupt
|
||||||
|
INTERRUPT_HANDLER(TIM2_UPD_OVF_BRK_IRQHandler, 13){
|
||||||
|
}
|
||||||
|
|
||||||
|
// Timer2 Capture/Compare Interrupt
|
||||||
|
// manage with sending/receiving
|
||||||
|
INTERRUPT_HANDLER(TIM2_CAP_COM_IRQHandler, 14){
|
||||||
|
/* TIM2_SR1 &= ~TIM_SR1_CC1IF;
|
||||||
|
onewire_gotlen = TIM2_CCR1H << 8;
|
||||||
|
onewire_gotlen |= TIM2_CCR1L;
|
||||||
|
if(onewire_tick_ctr){ // there's some more data to transmit / receive
|
||||||
|
--onewire_tick_ctr;
|
||||||
|
if(is_receiver){// receive bits
|
||||||
|
ow_data >>= 1;
|
||||||
|
if(onewire_gotlen < ONE_ZERO_BARRIER){ // this is 1
|
||||||
|
ow_data |= 0x80; // LSbit first!
|
||||||
|
}
|
||||||
|
// in receiver mode we don't need to send byte after ctr is zero!
|
||||||
|
if(onewire_tick_ctr == 0){
|
||||||
|
TIM2_CR1 &= ~TIM_CR1_CEN;
|
||||||
|
}
|
||||||
|
}else{// transmit bits
|
||||||
|
// update CCR2 registers with new values
|
||||||
|
if(ow_data & 1){ // transmit 1
|
||||||
|
TIM2REG(CCR2, BIT_ONE_P);
|
||||||
|
}else{ // transmit 0
|
||||||
|
TIM2REG(CCR2, BIT_ZERO_P);
|
||||||
|
}
|
||||||
|
ow_data >>= 1;
|
||||||
|
}
|
||||||
|
}else{ // end: turn off timer
|
||||||
|
TIM2_CR1 &= ~TIM_CR1_CEN;
|
||||||
|
}*/
|
||||||
|
}
|
||||||
|
#endif // STM8S903
|
||||||
|
|
||||||
|
#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
|
||||||
|
defined(STM8S005) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8AF626x)
|
||||||
|
// Timer3 Update/Overflow/Break Interrupt
|
||||||
|
INTERRUPT_HANDLER(TIM3_UPD_OVF_BRK_IRQHandler, 15){}
|
||||||
|
|
||||||
|
// Timer3 Capture/Compare Interrupt
|
||||||
|
INTERRUPT_HANDLER(TIM3_CAP_COM_IRQHandler, 16){}
|
||||||
|
#endif // STM8S208, STM8S207 or STM8S105 or STM8AF62Ax or STM8AF52Ax or STM8AF626x
|
||||||
|
|
||||||
|
#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S103) || \
|
||||||
|
defined(STM8S003) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8S903)
|
||||||
|
// UART1 TX Interrupt
|
||||||
|
INTERRUPT_HANDLER(UART1_TX_IRQHandler, 17){}
|
||||||
|
|
||||||
|
// UART1 RX Interrupt
|
||||||
|
INTERRUPT_HANDLER(UART1_RX_IRQHandler, 18){
|
||||||
|
U8 rb;
|
||||||
|
if(UART1_SR & UART_SR_RXNE){ // data received
|
||||||
|
rb = UART1_DR; // read received byte & clear RXNE flag
|
||||||
|
while(!(UART1_SR & UART_SR_TXE));
|
||||||
|
UART1_DR = rb; // echo received symbol
|
||||||
|
UART_rx[UART_rx_cur_i++] = rb; // put received byte into cycled buffer
|
||||||
|
if(UART_rx_cur_i == UART_rx_start_i){ // Oops: buffer overflow! Just forget old data
|
||||||
|
UART_rx_start_i++;
|
||||||
|
check_UART_pointer(UART_rx_start_i);
|
||||||
|
}
|
||||||
|
check_UART_pointer(UART_rx_cur_i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif // STM8S208 or STM8S207 or STM8S103 or STM8S903 or STM8AF62Ax or STM8AF52Ax
|
||||||
|
|
||||||
|
// I2C Interrupt
|
||||||
|
INTERRUPT_HANDLER(I2C_IRQHandler, 19){}
|
||||||
|
|
||||||
|
#if defined(STM8S105) || defined(STM8S005) || defined (STM8AF626x)
|
||||||
|
// UART2 TX interrupt
|
||||||
|
INTERRUPT_HANDLER(UART2_TX_IRQHandler, 20){}
|
||||||
|
|
||||||
|
// UART2 RX interrupt
|
||||||
|
INTERRUPT_HANDLER(UART2_RX_IRQHandler, 21){
|
||||||
|
}
|
||||||
|
#endif // STM8S105 or STM8AF626x
|
||||||
|
|
||||||
|
#if defined(STM8S207) || defined(STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
|
||||||
|
// UART3 TX interrupt
|
||||||
|
INTERRUPT_HANDLER(UART3_TX_IRQHandler, 20){}
|
||||||
|
|
||||||
|
// UART3 RX interrupt
|
||||||
|
INTERRUPT_HANDLER(UART3_RX_IRQHandler, 21){}
|
||||||
|
#endif // STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax
|
||||||
|
|
||||||
|
#if defined(STM8S207) || defined(STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
|
||||||
|
// ADC2 interrupt
|
||||||
|
INTERRUPT_HANDLER(ADC2_IRQHandler, 22){}
|
||||||
|
#else
|
||||||
|
// ADC1 interrupt
|
||||||
|
volatile U8 ADC_ready = 0;
|
||||||
|
volatile U8 ADC_value;
|
||||||
|
INTERRUPT_HANDLER(ADC1_IRQHandler, 22){ // fill circular buffer
|
||||||
|
int ADC_value = ADC_DRL; // in right-alignment mode we should first read LSB
|
||||||
|
ADC_value |= ADC_DRH << 8;
|
||||||
|
ADC_ready = 1;
|
||||||
|
ADC_CSR &= 0x3f; // clear EOC & AWD flags
|
||||||
|
}
|
||||||
|
#endif // STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax
|
||||||
|
|
||||||
|
#ifdef STM8S903
|
||||||
|
// Timer6 Update/Overflow/Trigger Interrupt
|
||||||
|
INTERRUPT_HANDLER(TIM6_UPD_OVF_TRG_IRQHandler, 23){}
|
||||||
|
#else // STM8S208, STM8S207, STM8S105 or STM8S103 or STM8AF52Ax or STM8AF62Ax or STM8AF626x
|
||||||
|
// Timer4 Update/Overflow Interrupt
|
||||||
|
INTERRUPT_HANDLER(TIM4_UPD_OVF_IRQHandler, 23){
|
||||||
|
if(TIM4_SR & TIM_SR1_UIF){ // update interrupt
|
||||||
|
Global_time++; // increase timer
|
||||||
|
}
|
||||||
|
TIM4_SR = 0; // clear all interrupt flags
|
||||||
|
}
|
||||||
|
#endif // STM8S903
|
||||||
|
|
||||||
|
// Eeprom EEC Interrupt
|
||||||
|
INTERRUPT_HANDLER(EEPROM_EEC_IRQHandler, 24){}
|
||||||
147
220controlled_socket/src/interrupts.h
Normal file
147
220controlled_socket/src/interrupts.h
Normal file
@ -0,0 +1,147 @@
|
|||||||
|
/*
|
||||||
|
* interrupts.h
|
||||||
|
*
|
||||||
|
* Copyright 2014 Edward V. Emelianoff <eddy@sao.ru>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301, USA.
|
||||||
|
*/
|
||||||
|
#pragma once
|
||||||
|
#ifndef __INTERRUPTS_H__
|
||||||
|
#define __INTERRUPTS_H__
|
||||||
|
|
||||||
|
#include "stm8s.h"
|
||||||
|
|
||||||
|
extern volatile U8 ADC_ready; // flag: data ready
|
||||||
|
extern volatile int ADC_value; // value of last ADC measurement
|
||||||
|
|
||||||
|
// Top Level Interrupt
|
||||||
|
INTERRUPT_DEFINITION(TLI_IRQHandler, 0);
|
||||||
|
|
||||||
|
// Auto Wake Up Interrupt
|
||||||
|
INTERRUPT_DEFINITION(AWU_IRQHandler, 1);
|
||||||
|
|
||||||
|
// Clock Controller Interrupt
|
||||||
|
INTERRUPT_DEFINITION(CLK_IRQHandler, 2);
|
||||||
|
|
||||||
|
// External Interrupt PORTA
|
||||||
|
INTERRUPT_DEFINITION(EXTI_PORTA_IRQHandler, 3);
|
||||||
|
|
||||||
|
// External Interrupt PORTB
|
||||||
|
INTERRUPT_DEFINITION(EXTI_PORTB_IRQHandler, 4);
|
||||||
|
|
||||||
|
// External Interrupt PORTC
|
||||||
|
INTERRUPT_DEFINITION(EXTI_PORTC_IRQHandler, 5);
|
||||||
|
|
||||||
|
// External Interrupt PORTD
|
||||||
|
INTERRUPT_DEFINITION(EXTI_PORTD_IRQHandler, 6);
|
||||||
|
|
||||||
|
// External Interrupt PORTE
|
||||||
|
INTERRUPT_DEFINITION(EXTI_PORTE_IRQHandler, 7);
|
||||||
|
|
||||||
|
#ifdef STM8S903
|
||||||
|
// External Interrupt PORTF
|
||||||
|
INTERRUPT_DEFINITION(EXTI_PORTF_IRQHandler, 8);
|
||||||
|
#endif // STM8S903
|
||||||
|
|
||||||
|
#if defined (STM8S208) || defined (STM8AF52Ax)
|
||||||
|
// CAN RX Interrupt routine.
|
||||||
|
INTERRUPT_DEFINITION(CAN_RX_IRQHandler, 8);
|
||||||
|
|
||||||
|
// CAN TX Interrupt routine.
|
||||||
|
INTERRUPT_DEFINITION(CAN_TX_IRQHandler, 9);
|
||||||
|
#endif // STM8S208 || STM8AF52Ax
|
||||||
|
|
||||||
|
// SPI Interrupt routine.
|
||||||
|
INTERRUPT_DEFINITION(SPI_IRQHandler, 10);
|
||||||
|
|
||||||
|
// Timer1 Update/Overflow/Trigger/Break Interrupt
|
||||||
|
INTERRUPT_DEFINITION(TIM1_UPD_OVF_TRG_BRK_IRQHandler, 11);
|
||||||
|
|
||||||
|
// Timer1 Capture/Compare Interrupt routine.
|
||||||
|
INTERRUPT_DEFINITION(TIM1_CAP_COM_IRQHandler, 12);
|
||||||
|
|
||||||
|
#ifdef STM8S903
|
||||||
|
// Timer5 Update/Overflow/Break/Trigger Interrupt
|
||||||
|
INTERRUPT_DEFINITION(TIM5_UPD_OVF_BRK_TRG_IRQHandler, 13);
|
||||||
|
|
||||||
|
// Timer5 Capture/Compare Interrupt
|
||||||
|
INTERRUPT_DEFINITION(TIM5_CAP_COM_IRQHandler, 14);
|
||||||
|
|
||||||
|
#else // STM8S208, STM8S207, STM8S105 or STM8S103 or STM8AF62Ax or STM8AF52Ax or STM8AF626x
|
||||||
|
// Timer2 Update/Overflow/Break Interrupt
|
||||||
|
INTERRUPT_DEFINITION(TIM2_UPD_OVF_BRK_IRQHandler, 13);
|
||||||
|
|
||||||
|
// Timer2 Capture/Compare Interrupt
|
||||||
|
INTERRUPT_DEFINITION(TIM2_CAP_COM_IRQHandler, 14);
|
||||||
|
#endif // STM8S903
|
||||||
|
|
||||||
|
#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \
|
||||||
|
defined(STM8S005) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8AF626x)
|
||||||
|
// Timer3 Update/Overflow/Break Interrupt
|
||||||
|
INTERRUPT_DEFINITION(TIM3_UPD_OVF_BRK_IRQHandler, 15);
|
||||||
|
|
||||||
|
// Timer3 Capture/Compare Interrupt
|
||||||
|
INTERRUPT_DEFINITION(TIM3_CAP_COM_IRQHandler, 16);
|
||||||
|
#endif // STM8S208, STM8S207 or STM8S105 or STM8AF62Ax or STM8AF52Ax or STM8AF626x
|
||||||
|
|
||||||
|
#if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S103) || \
|
||||||
|
defined(STM8S003) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8S903)
|
||||||
|
// UART1 TX Interrupt
|
||||||
|
INTERRUPT_DEFINITION(UART1_TX_IRQHandler, 17);
|
||||||
|
|
||||||
|
// UART1 RX Interrupt
|
||||||
|
INTERRUPT_DEFINITION(UART1_RX_IRQHandler, 18);
|
||||||
|
#endif // STM8S208 or STM8S207 or STM8S103 or STM8S903 or STM8AF62Ax or STM8AF52Ax
|
||||||
|
|
||||||
|
// I2C Interrupt
|
||||||
|
INTERRUPT_DEFINITION(I2C_IRQHandler, 19);
|
||||||
|
|
||||||
|
#if defined(STM8S105) || defined(STM8S005) || defined (STM8AF626x)
|
||||||
|
// UART2 TX interrupt
|
||||||
|
INTERRUPT_DEFINITION(UART2_TX_IRQHandler, 20);
|
||||||
|
|
||||||
|
// UART2 RX interrupt
|
||||||
|
INTERRUPT_DEFINITION(UART2_RX_IRQHandler, 21);
|
||||||
|
#endif // STM8S105 or STM8AF626x
|
||||||
|
|
||||||
|
#if defined(STM8S207) || defined(STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
|
||||||
|
// UART3 TX interrupt
|
||||||
|
INTERRUPT_DEFINITION(UART3_TX_IRQHandler, 20);
|
||||||
|
|
||||||
|
// UART3 RX interrupt
|
||||||
|
INTERRUPT_DEFINITION(UART3_RX_IRQHandler, 21);
|
||||||
|
#endif // STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax
|
||||||
|
|
||||||
|
#if defined(STM8S207) || defined(STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || defined (STM8AF62Ax)
|
||||||
|
// ADC2 interrupt
|
||||||
|
INTERRUPT_DEFINITION(ADC2_IRQHandler, 22);
|
||||||
|
#else // STM8S105, STM8S103 or STM8S903 or STM8AF626x
|
||||||
|
// ADC1 interrupt
|
||||||
|
INTERRUPT_DEFINITION(ADC1_IRQHandler, 22);
|
||||||
|
#endif // STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax
|
||||||
|
|
||||||
|
#ifdef STM8S903
|
||||||
|
// Timer6 Update/Overflow/Trigger Interrupt
|
||||||
|
INTERRUPT_DEFINITION(TIM6_UPD_OVF_TRG_IRQHandler, 23);
|
||||||
|
#else // STM8S208, STM8S207, STM8S105 or STM8S103 or STM8AF52Ax or STM8AF62Ax or STM8AF626x
|
||||||
|
// Timer4 Update/Overflow Interrupt
|
||||||
|
INTERRUPT_DEFINITION(TIM4_UPD_OVF_IRQHandler, 23);
|
||||||
|
#endif // STM8S903
|
||||||
|
|
||||||
|
// Eeprom EEC Interrupt
|
||||||
|
INTERRUPT_DEFINITION(EEPROM_EEC_IRQHandler, 24);
|
||||||
|
|
||||||
|
#endif // __INTERRUPTS_H__
|
||||||
132
220controlled_socket/src/main.c
Normal file
132
220controlled_socket/src/main.c
Normal file
@ -0,0 +1,132 @@
|
|||||||
|
/*
|
||||||
|
* blinky.c
|
||||||
|
*
|
||||||
|
* Copyright 2018 Edward V. Emelianoff <eddy@sao.ru>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301, USA.
|
||||||
|
*/
|
||||||
|
#include "stm8s.h"
|
||||||
|
#include "hardware.h"
|
||||||
|
#include "interrupts.h"
|
||||||
|
#include "uart.h"
|
||||||
|
|
||||||
|
volatile unsigned long Global_time = 0L; // global time in ms
|
||||||
|
|
||||||
|
U16 temp;
|
||||||
|
U8 pidx;
|
||||||
|
#define PIX_SORT(a,b) { if ((a)>(b)) PIX_SWAP((a),(b)); }
|
||||||
|
#define PIX_SWAP(a,b) { temp=(a);(a)=(b);(b)=temp; }
|
||||||
|
U16 p[9]; // buffer for median filtering
|
||||||
|
U16 opt_med9(){
|
||||||
|
PIX_SORT(p[1], p[2]) ; PIX_SORT(p[4], p[5]) ; PIX_SORT(p[7], p[8]) ;
|
||||||
|
PIX_SORT(p[0], p[1]) ; PIX_SORT(p[3], p[4]) ; PIX_SORT(p[6], p[7]) ;
|
||||||
|
PIX_SORT(p[1], p[2]) ; PIX_SORT(p[4], p[5]) ; PIX_SORT(p[7], p[8]) ;
|
||||||
|
PIX_SORT(p[0], p[3]) ; PIX_SORT(p[5], p[8]) ; PIX_SORT(p[4], p[7]) ;
|
||||||
|
PIX_SORT(p[3], p[6]) ; PIX_SORT(p[1], p[4]) ; PIX_SORT(p[2], p[5]) ;
|
||||||
|
PIX_SORT(p[4], p[7]) ; PIX_SORT(p[4], p[2]) ; PIX_SORT(p[6], p[4]) ;
|
||||||
|
PIX_SORT(p[4], p[2]) ; return(p[4]) ;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
int main() {
|
||||||
|
unsigned long Tmeas = 0L;
|
||||||
|
U16 curMin = 0xffff, curMax = 0, curRange = 0; // min, max & range measured of current in ADU
|
||||||
|
U8 rb, ch;
|
||||||
|
U16 curval, npts = 0;
|
||||||
|
hw_init();
|
||||||
|
|
||||||
|
uart_init();
|
||||||
|
|
||||||
|
// enable all interrupts
|
||||||
|
enableInterrupts();
|
||||||
|
|
||||||
|
// Loop
|
||||||
|
do{
|
||||||
|
if(ADC_ready){
|
||||||
|
p[pidx] = ADC_value;
|
||||||
|
if(++pidx == 9){
|
||||||
|
pidx = 0;
|
||||||
|
++npts;
|
||||||
|
// measure max & min values
|
||||||
|
curval = opt_med9();
|
||||||
|
if(curMax < curval) curMax = curval;
|
||||||
|
if(curMin > curval) curMin = curval;
|
||||||
|
}
|
||||||
|
ADC_ready = 0;
|
||||||
|
ADC_CR1 = 0x71;
|
||||||
|
}
|
||||||
|
if(Global_time - Tmeas > 199){ // 10 periods left, make current measurement
|
||||||
|
Tmeas = Global_time;
|
||||||
|
npts = 0;
|
||||||
|
if(curMax) curRange = curMax - curMin;
|
||||||
|
curMax = 0; curMin = 0xffff;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(uart_read_byte(&rb)){ // buffer isn't empty
|
||||||
|
switch(rb){
|
||||||
|
case 'h': // help
|
||||||
|
case 'H':
|
||||||
|
uart_write( "\nPROTO:\n"
|
||||||
|
"c/C - check in0/1\n"
|
||||||
|
"I - show current ampl. (ADU)\n"
|
||||||
|
"s/S - activate out0/1\n"
|
||||||
|
"r/R - deactivate out0/1\n"
|
||||||
|
);
|
||||||
|
break;
|
||||||
|
case 'I': // current amplitude in ADU
|
||||||
|
curval = curRange / 2;
|
||||||
|
uart_write("Imax(ADU)=");
|
||||||
|
printUint((U8*)&curval, 2);
|
||||||
|
uart_write(", Npts=");
|
||||||
|
printUint((U8*)npts, 2);
|
||||||
|
newline();
|
||||||
|
break;
|
||||||
|
case 'c': // check IN0
|
||||||
|
case 'C': // check IN1
|
||||||
|
uart_write("In");
|
||||||
|
ch = (rb == 'c') ? '0' : '1';
|
||||||
|
uart_send_byte(ch);
|
||||||
|
uart_send_byte('=');
|
||||||
|
if(rb == 'c') ch = CHK_IN0() ? '1' : '0';
|
||||||
|
else ch = CHK_IN1() ? '1' : '0';
|
||||||
|
uart_send_byte(ch);
|
||||||
|
newline();
|
||||||
|
break;
|
||||||
|
case 's':
|
||||||
|
case 'S':
|
||||||
|
ch = (rb == 's') ? '0' : '1';
|
||||||
|
uart_write("Out");
|
||||||
|
uart_send_byte(ch);
|
||||||
|
uart_write("=1\n");
|
||||||
|
if(rb == 's') SET_OUT0();
|
||||||
|
else SET_OUT1();
|
||||||
|
break;
|
||||||
|
case 'r':
|
||||||
|
case 'R':
|
||||||
|
ch = (rb == 'r') ? '0' : '1';
|
||||||
|
uart_write("Out");
|
||||||
|
uart_send_byte(ch);
|
||||||
|
uart_write("=0\n");
|
||||||
|
if(rb == 'r') RESET_OUT0();
|
||||||
|
else RESET_OUT1();
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}while(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
561
220controlled_socket/src/stm8s.h
Normal file
561
220controlled_socket/src/stm8s.h
Normal file
@ -0,0 +1,561 @@
|
|||||||
|
/*
|
||||||
|
* stm8l.h
|
||||||
|
*
|
||||||
|
* Copyright 2014 Edward V. Emelianoff <eddy@sao.ru>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301, USA.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#pragma once
|
||||||
|
#ifndef __STM8L_H__
|
||||||
|
#define __STM8L_H__
|
||||||
|
|
||||||
|
typedef unsigned char U8;
|
||||||
|
typedef unsigned int U16;
|
||||||
|
typedef unsigned long U32;
|
||||||
|
#define NULL (void*)0
|
||||||
|
|
||||||
|
/* functions */
|
||||||
|
#define enableInterrupts() {__asm__("rim\n");} // enable interrupts
|
||||||
|
#define disableInterrupts() {__asm__("sim\n");} // disable interrupts
|
||||||
|
#define iret() {__asm__("iret\n");} // Interrupt routine return
|
||||||
|
#define pop_ccr() {__asm__("pop cc\n");} // Pop CCR from the stack
|
||||||
|
#define push_ccr() {__asm__("push cc\n");}// Push CCR on the stack
|
||||||
|
#define rim() {__asm__("rim\n");} // enable interrupts
|
||||||
|
#define sim() {__asm__("sim\n");} // disable interrupts
|
||||||
|
#define nop() {__asm__("nop\n");} // No Operation
|
||||||
|
#define trap() {__asm__("trap\n");} // Trap (soft IT)
|
||||||
|
#define wfi() {__asm__("wfi\n");} // Wait For Interrupt
|
||||||
|
#define halt() {__asm__("halt\n");} // Halt
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Registers map is shown in short datasheet, page 26
|
||||||
|
*/
|
||||||
|
/* GPIO */
|
||||||
|
#define PA_ODR *(unsigned char*)0x5000
|
||||||
|
#define PA_IDR *(unsigned char*)0x5001
|
||||||
|
#define PA_DDR *(unsigned char*)0x5002
|
||||||
|
#define PA_CR1 *(unsigned char*)0x5003
|
||||||
|
#define PA_CR2 *(unsigned char*)0x5004
|
||||||
|
|
||||||
|
#define PB_ODR *(unsigned char*)0x5005
|
||||||
|
#define PB_IDR *(unsigned char*)0x5006
|
||||||
|
#define PB_DDR *(unsigned char*)0x5007
|
||||||
|
#define PB_CR1 *(unsigned char*)0x5008
|
||||||
|
#define PB_CR2 *(unsigned char*)0x5009
|
||||||
|
|
||||||
|
#define PC_ODR *(unsigned char*)0x500A
|
||||||
|
#define PC_IDR *(unsigned char*)0x500B
|
||||||
|
#define PC_DDR *(unsigned char*)0x500C
|
||||||
|
#define PC_CR1 *(unsigned char*)0x500D
|
||||||
|
#define PC_CR2 *(unsigned char*)0x500E
|
||||||
|
|
||||||
|
#define PD_ODR *(unsigned char*)0x500F
|
||||||
|
#define PD_IDR *(unsigned char*)0x5010
|
||||||
|
#define PD_DDR *(unsigned char*)0x5011
|
||||||
|
#define PD_CR1 *(unsigned char*)0x5012
|
||||||
|
#define PD_CR2 *(unsigned char*)0x5013
|
||||||
|
|
||||||
|
#define PE_ODR *(unsigned char*)0x5014
|
||||||
|
#define PE_IDR *(unsigned char*)0x5015
|
||||||
|
#define PE_DDR *(unsigned char*)0x5016
|
||||||
|
#define PE_CR1 *(unsigned char*)0x5017
|
||||||
|
#define PE_CR2 *(unsigned char*)0x5018
|
||||||
|
|
||||||
|
#define PF_ODR *(unsigned char*)0x5019
|
||||||
|
#define PF_IDR *(unsigned char*)0x501A
|
||||||
|
#define PF_DDR *(unsigned char*)0x501B
|
||||||
|
#define PF_CR1 *(unsigned char*)0x501C
|
||||||
|
#define PF_CR2 *(unsigned char*)0x501D
|
||||||
|
|
||||||
|
#ifdef STM8S105
|
||||||
|
#define PG_ODR *(unsigned char*)0x501E
|
||||||
|
#define PG_IDR *(unsigned char*)0x501F
|
||||||
|
#define PG_DDR *(unsigned char*)0x5020
|
||||||
|
#define PG_CR1 *(unsigned char*)0x5021
|
||||||
|
#define PG_CR2 *(unsigned char*)0x5022
|
||||||
|
|
||||||
|
#define PH_ODR *(unsigned char*)0x5023
|
||||||
|
#define PH_IDR *(unsigned char*)0x5024
|
||||||
|
#define PH_DDR *(unsigned char*)0x5025
|
||||||
|
#define PH_CR1 *(unsigned char*)0x5026
|
||||||
|
#define PH_CR2 *(unsigned char*)0x5027
|
||||||
|
|
||||||
|
#define PI_ODR *(unsigned char*)0x5028
|
||||||
|
#define PI_IDR *(unsigned char*)0x5029
|
||||||
|
#define PI_DDR *(unsigned char*)0x502A
|
||||||
|
#define PI_CR1 *(unsigned char*)0x502B
|
||||||
|
#define PI_CR2 *(unsigned char*)0x502C
|
||||||
|
#endif // STM8S105
|
||||||
|
|
||||||
|
/* GPIO bits */
|
||||||
|
#define GPIO_PIN0 (1 << 0)
|
||||||
|
#define GPIO_PIN1 (1 << 1)
|
||||||
|
#define GPIO_PIN2 (1 << 2)
|
||||||
|
#define GPIO_PIN3 (1 << 3)
|
||||||
|
#define GPIO_PIN4 (1 << 4)
|
||||||
|
#define GPIO_PIN5 (1 << 5)
|
||||||
|
#define GPIO_PIN6 (1 << 6)
|
||||||
|
#define GPIO_PIN7 (1 << 7)
|
||||||
|
|
||||||
|
/* -------------------- FLASH/EEPROM -------------------- */
|
||||||
|
#define FLASH_CR1 *(unsigned char*)0x505A
|
||||||
|
#define FLASH_CR2 *(unsigned char*)0x505B
|
||||||
|
#define FLASH_NCR2 *(unsigned char*)0x505C
|
||||||
|
#define FLASH_FPR *(unsigned char*)0x505D
|
||||||
|
#define FLASH_NFPR *(unsigned char*)0x505E
|
||||||
|
#define FLASH_IAPSR *(unsigned char*)0x505F
|
||||||
|
#define FLASH_PUKR *(unsigned char*)0x5062 // progmem unprotection
|
||||||
|
#define FLASH_DUKR *(unsigned char*)0x5064 // EEPROM unprotection
|
||||||
|
|
||||||
|
#define EEPROM_KEY1 0xAE // keys to manage EEPROM's write access
|
||||||
|
#define EEPROM_KEY2 0x56
|
||||||
|
#define EEPROM_START_ADDR (unsigned char*)0x4000
|
||||||
|
|
||||||
|
/* ------------------- interrupts ------------------- */
|
||||||
|
#define EXTI_CR1 *(unsigned char*)0x50A0
|
||||||
|
#define EXTI_CR2 *(unsigned char*)0x50A1
|
||||||
|
#define INTERRUPT_HANDLER(fn, num) void fn() __interrupt(num)
|
||||||
|
#define INTERRUPT_DEFINITION(fn, num) extern void fn() __interrupt(num)
|
||||||
|
|
||||||
|
// Reset status register
|
||||||
|
#define RST_SR *(unsigned char*)0x50B3
|
||||||
|
|
||||||
|
/* ------------------- CLOCK ------------------- */
|
||||||
|
#define CLK_ICKR *(unsigned char*)0x50C0
|
||||||
|
#define CLK_ECKR *(unsigned char*)0x50C1
|
||||||
|
#define CLK_CMSR *(unsigned char*)0x50C3
|
||||||
|
#define CLK_SWR *(unsigned char*)0x50C4
|
||||||
|
#define CLK_SWCR *(unsigned char*)0x50C5
|
||||||
|
#define CLK_CKDIVR *(unsigned char*)0x50C6
|
||||||
|
#define CLK_SPCKENR1 *(unsigned char*)0x50C7
|
||||||
|
#define CLK_CSSR *(unsigned char*)0x50C8
|
||||||
|
#define CLK_CCOR *(unsigned char*)0x50C9
|
||||||
|
#define CLK_PCKENR2 *(unsigned char*)0x50CA
|
||||||
|
#define CLK_HSITRIMR *(unsigned char*)0x50CC
|
||||||
|
#define CLK_SWIMCCR *(unsigned char*)0x50CD
|
||||||
|
|
||||||
|
/* ------------------- Watchdog ------------------ */
|
||||||
|
#define WWDG_CR *(unsigned char*)0x50D1
|
||||||
|
#define WWDG_WR *(unsigned char*)0x50D2
|
||||||
|
#define IWDG_KR *(unsigned char*)0x50E0
|
||||||
|
#define IWDG_PR *(unsigned char*)0x50E1
|
||||||
|
#define IWDG_RLR *(unsigned char*)0x50E2
|
||||||
|
|
||||||
|
/* ------------------- AWU, BEEP ------------------- */
|
||||||
|
#define AWU_CSR1 *(unsigned char*)0x50F0
|
||||||
|
#define AWU_APR *(unsigned char*)0x50F1
|
||||||
|
#define AWU_TBR *(unsigned char*)0x50F2
|
||||||
|
#define BEEP_CSR *(unsigned char*)0x50F3
|
||||||
|
|
||||||
|
/* ------------------- SPI ------------------- */
|
||||||
|
#define SPI_CR1 *(unsigned char*)0x5200
|
||||||
|
#define SPI_CR2 *(unsigned char*)0x5201
|
||||||
|
#define SPI_ICR *(unsigned char*)0x5202
|
||||||
|
#define SPI_SR *(unsigned char*)0x5203
|
||||||
|
#define SPI_DR *(unsigned char*)0x5204
|
||||||
|
#define SPI_CRCPR *(unsigned char*)0x5205
|
||||||
|
#define SPI_RXCRCR *(unsigned char*)0x5206
|
||||||
|
#define SPI_TXCRCR *(unsigned char*)0x5207
|
||||||
|
// SPI_CR1 (page 271): | LSBFIRST | SPE | BR[2:0] | MSTR | CPOL | CPHA |
|
||||||
|
#define SPI_CR1_LSBFIRST (1<<7)
|
||||||
|
#define SPI_CR1_SPE (1<<6)
|
||||||
|
#define SPI_CR1_BRMASK (0x38)
|
||||||
|
#define SPI_CR1_MSTR (1<<2)
|
||||||
|
#define SPI_CR1_CPOL (1<<1)
|
||||||
|
#define SPI_CR1_CPHA (1)
|
||||||
|
// SPI_CR2 (page 272): | BDM | BDOE | CRCEN | CRCNEXT | - | RXONLY | SSM | SSI |
|
||||||
|
#define SPI_CR2_BDM (1<<7)
|
||||||
|
#define SPI_CR2_BDOE (1<<6)
|
||||||
|
#define SPI_CR2_CRCEN (1<<5)
|
||||||
|
#define SPI_CR2_CRCNEXT (1<<4)
|
||||||
|
#define SPI_CR2_RXONLY (1<<2)
|
||||||
|
#define SPI_CR2_SSM (1<<1)
|
||||||
|
#define SPI_CR2_SSI (1)
|
||||||
|
// SPI_ICR (page 273): | TXIE | RXIE | ERRIE | WKIE | - | - | - | - |
|
||||||
|
#define SPI_ICR_TXIE (1<<7)
|
||||||
|
#define SPI_ICR_RXIE (1<<6)
|
||||||
|
#define SPI_ICR_ERRIE (1<<5)
|
||||||
|
#define SPI_ICR_WKIE (1<<4)
|
||||||
|
// SPI_SR (page 274): | BSY | OVR | MODF | CRCERR | WKUP | - | TXE | RXNE |
|
||||||
|
#define SPI_SR_BSY (1<<7)
|
||||||
|
#define SPI_SR_OVR (1<<6)
|
||||||
|
#define SPI_SR_MODF (1<<5)
|
||||||
|
#define SPI_SR_CRCERR (1<<4)
|
||||||
|
#define SPI_SR_WKUP (1<<3)
|
||||||
|
#define SPI_SR_TXE (1<<1)
|
||||||
|
#define SPI_SR_RXNE (1)
|
||||||
|
|
||||||
|
/* ------------------- I2C ------------------- */
|
||||||
|
#define I2C_CR1 *(unsigned char*)0x5210
|
||||||
|
#define I2C_CR2 *(unsigned char*)0x5211
|
||||||
|
#define I2C_FREQR *(unsigned char*)0x5212
|
||||||
|
#define I2C_OARL *(unsigned char*)0x5213
|
||||||
|
#define I2C_OARH *(unsigned char*)0x5214
|
||||||
|
#define I2C_DR *(unsigned char*)0x5216
|
||||||
|
#define I2C_SR1 *(unsigned char*)0x5217
|
||||||
|
#define I2C_SR2 *(unsigned char*)0x5218
|
||||||
|
#define I2C_SR3 *(unsigned char*)0x5219
|
||||||
|
#define I2C_ITR *(unsigned char*)0x521A
|
||||||
|
#define I2C_CCRL *(unsigned char*)0x521B
|
||||||
|
#define I2C_CCRH *(unsigned char*)0x521C
|
||||||
|
#define I2C_TRISER *(unsigned char*)0x521D
|
||||||
|
#define I2C_PECR *(unsigned char*)0x521E
|
||||||
|
|
||||||
|
/* ------------------- UART ------------------- */
|
||||||
|
#ifdef STM8S003
|
||||||
|
#define UART1_SR *(unsigned char*)0x5230
|
||||||
|
#define UART1_DR *(unsigned char*)0x5231
|
||||||
|
#define UART1_BRR1 *(unsigned char*)0x5232
|
||||||
|
#define UART1_BRR2 *(unsigned char*)0x5233
|
||||||
|
#define UART1_CR1 *(unsigned char*)0x5234
|
||||||
|
#define UART1_CR2 *(unsigned char*)0x5235
|
||||||
|
#define UART1_CR3 *(unsigned char*)0x5236
|
||||||
|
#define UART1_CR4 *(unsigned char*)0x5237
|
||||||
|
#define UART1_CR5 *(unsigned char*)0x5238
|
||||||
|
#define UART1_GTR *(unsigned char*)0x5239
|
||||||
|
#define UART1_PSCR *(unsigned char*)0x523A
|
||||||
|
#endif // STM8S003
|
||||||
|
#ifdef STM8S105
|
||||||
|
#define UART2_SR *(unsigned char*)0x5240
|
||||||
|
#define UART2_DR *(unsigned char*)0x5241
|
||||||
|
#define UART2_BRR1 *(unsigned char*)0x5242
|
||||||
|
#define UART2_BRR2 *(unsigned char*)0x5243
|
||||||
|
#define UART2_CR1 *(unsigned char*)0x5244
|
||||||
|
#define UART2_CR2 *(unsigned char*)0x5245
|
||||||
|
#define UART2_CR3 *(unsigned char*)0x5246
|
||||||
|
#define UART2_CR4 *(unsigned char*)0x5247
|
||||||
|
#define UART2_CR5 *(unsigned char*)0x5248
|
||||||
|
#define UART2_CR6 *(unsigned char*)0x5249
|
||||||
|
#define UART2_GTR *(unsigned char*)0x524A
|
||||||
|
#define UART2_PSCR *(unsigned char*)0x524B
|
||||||
|
#endif // STM8S105
|
||||||
|
|
||||||
|
/* UART_CR1 bits */
|
||||||
|
#define UART_CR1_R8 (1 << 7)
|
||||||
|
#define UART_CR1_T8 (1 << 6)
|
||||||
|
#define UART_CR1_UARTD (1 << 5)
|
||||||
|
#define UART_CR1_M (1 << 4)
|
||||||
|
#define UART_CR1_WAKE (1 << 3)
|
||||||
|
#define UART_CR1_PCEN (1 << 2)
|
||||||
|
#define UART_CR1_PS (1 << 1)
|
||||||
|
#define UART_CR1_PIEN (1 << 0)
|
||||||
|
|
||||||
|
/* UART_CR2 bits */
|
||||||
|
#define UART_CR2_TIEN (1 << 7)
|
||||||
|
#define UART_CR2_TCIEN (1 << 6)
|
||||||
|
#define UART_CR2_RIEN (1 << 5)
|
||||||
|
#define UART_CR2_ILIEN (1 << 4)
|
||||||
|
#define UART_CR2_TEN (1 << 3)
|
||||||
|
#define UART_CR2_REN (1 << 2)
|
||||||
|
#define UART_CR2_RWU (1 << 1)
|
||||||
|
#define UART_CR2_SBK (1 << 0)
|
||||||
|
|
||||||
|
/* USART_CR3 bits */
|
||||||
|
#define UART_CR3_LINEN (1 << 6)
|
||||||
|
#define UART_CR3_STOP2 (1 << 5)
|
||||||
|
#define UART_CR3_STOP1 (1 << 4)
|
||||||
|
#define UART_CR3_CLKEN (1 << 3)
|
||||||
|
#define UART_CR3_CPOL (1 << 2)
|
||||||
|
#define UART_CR3_CPHA (1 << 1)
|
||||||
|
#define UART_CR3_LBCL (1 << 0)
|
||||||
|
|
||||||
|
/* UART_SR bits */
|
||||||
|
#define UART_SR_TXE (1 << 7)
|
||||||
|
#define UART_SR_TC (1 << 6)
|
||||||
|
#define UART_SR_RXNE (1 << 5)
|
||||||
|
#define UART_SR_IDLE (1 << 4)
|
||||||
|
#define UART_SR_OR (1 << 3)
|
||||||
|
#define UART_SR_NF (1 << 2)
|
||||||
|
#define UART_SR_FE (1 << 1)
|
||||||
|
#define UART_SR_PE (1 << 0)
|
||||||
|
|
||||||
|
|
||||||
|
/* ------------------- TIMERS ------------------- */
|
||||||
|
/* TIM1 */
|
||||||
|
#define TIM1_CR1 *(unsigned char*)0x5250
|
||||||
|
#define TIM1_CR2 *(unsigned char*)0x5251
|
||||||
|
#define TIM1_SMCR *(unsigned char*)0x5252
|
||||||
|
#define TIM1_ETR *(unsigned char*)0x5253
|
||||||
|
#define TIM1_IER *(unsigned char*)0x5254
|
||||||
|
#define TIM1_SR1 *(unsigned char*)0x5255
|
||||||
|
#define TIM1_SR2 *(unsigned char*)0x5256
|
||||||
|
#define TIM1_EGR *(unsigned char*)0x5257
|
||||||
|
#define TIM1_CCMR1 *(unsigned char*)0x5258
|
||||||
|
#define TIM1_CCMR2 *(unsigned char*)0x5259
|
||||||
|
#define TIM1_CCMR3 *(unsigned char*)0x525A
|
||||||
|
#define TIM1_CCMR4 *(unsigned char*)0x525B
|
||||||
|
#define TIM1_CCER1 *(unsigned char*)0x525C
|
||||||
|
#define TIM1_CCER2 *(unsigned char*)0x525D
|
||||||
|
#define TIM1_CNTRH *(unsigned char*)0x525E
|
||||||
|
#define TIM1_CNTRL *(unsigned char*)0x525F
|
||||||
|
#define TIM1_PSCRH *(unsigned char*)0x5260
|
||||||
|
#define TIM1_PSCRL *(unsigned char*)0x5261
|
||||||
|
#define TIM1_ARRH *(unsigned char*)0x5262
|
||||||
|
#define TIM1_ARRL *(unsigned char*)0x5263
|
||||||
|
#define TIM1_RCR *(unsigned char*)0x5264
|
||||||
|
#define TIM1_CCR1H *(unsigned char*)0x5265
|
||||||
|
#define TIM1_CCR1L *(unsigned char*)0x5266
|
||||||
|
#define TIM1_CCR2H *(unsigned char*)0x5267
|
||||||
|
#define TIM1_CCR2L *(unsigned char*)0x5268
|
||||||
|
#define TIM1_CCR3H *(unsigned char*)0x5269
|
||||||
|
#define TIM1_CCR3L *(unsigned char*)0x526A
|
||||||
|
#define TIM1_CCR4H *(unsigned char*)0x526B
|
||||||
|
#define TIM1_CCR4L *(unsigned char*)0x526C
|
||||||
|
#define TIM1_BKR *(unsigned char*)0x526D
|
||||||
|
#define TIM1_DTR *(unsigned char*)0x526E
|
||||||
|
#define TIM1_OISR *(unsigned char*)0x526F
|
||||||
|
|
||||||
|
|
||||||
|
/* TIM_IER bits */
|
||||||
|
#define TIM_IER_BIE (1 << 7)
|
||||||
|
#define TIM_IER_TIE (1 << 6)
|
||||||
|
#define TIM_IER_COMIE (1 << 5)
|
||||||
|
#define TIM_IER_CC4IE (1 << 4)
|
||||||
|
#define TIM_IER_CC3IE (1 << 3)
|
||||||
|
#define TIM_IER_CC2IE (1 << 2)
|
||||||
|
#define TIM_IER_CC1IE (1 << 1)
|
||||||
|
#define TIM_IER_UIE (1 << 0)
|
||||||
|
|
||||||
|
/* TIM_CR1 bits */
|
||||||
|
#define TIM_CR1_APRE (1 << 7)
|
||||||
|
#define TIM_CR1_CMSH (1 << 6)
|
||||||
|
#define TIM_CR1_CMSL (1 << 5)
|
||||||
|
#define TIM_CR1_DIR (1 << 4)
|
||||||
|
#define TIM_CR1_OPM (1 << 3)
|
||||||
|
#define TIM_CR1_URS (1 << 2)
|
||||||
|
#define TIM_CR1_UDIS (1 << 1)
|
||||||
|
#define TIM_CR1_CEN (1 << 0)
|
||||||
|
|
||||||
|
/* TIM_SR1 bits */
|
||||||
|
#define TIM_SR1_BIF (1 << 7)
|
||||||
|
#define TIM_SR1_TIF (1 << 6)
|
||||||
|
#define TIM_SR1_COMIF (1 << 5)
|
||||||
|
#define TIM_SR1_CC4IF (1 << 4)
|
||||||
|
#define TIM_SR1_CC3IF (1 << 3)
|
||||||
|
#define TIM_SR1_CC2IF (1 << 2)
|
||||||
|
#define TIM_SR1_CC1IF (1 << 1)
|
||||||
|
#define TIM_SR1_UIF (1 << 0)
|
||||||
|
|
||||||
|
/* TIM_EGR bits */
|
||||||
|
#define TIM_EGR_BG (1 << 7)
|
||||||
|
#define TIM_EGR_TG (1 << 6)
|
||||||
|
#define TIM_EGR_COMG (1 << 5)
|
||||||
|
#define TIM_EGR_CC4G (1 << 4)
|
||||||
|
#define TIM_EGR_CC3G (1 << 3)
|
||||||
|
#define TIM_EGR_CC2G (1 << 2)
|
||||||
|
#define TIM_EGR_CC1G (1 << 1)
|
||||||
|
#define TIM_EGR_UG (1 << 0)
|
||||||
|
|
||||||
|
|
||||||
|
/* TIM2 */
|
||||||
|
#define TIM2_CR1 *(unsigned char*)0x5300
|
||||||
|
#if defined STM8S105 || defined STM8S103
|
||||||
|
#define TIM2_IER *(unsigned char*)0x5301
|
||||||
|
#define TIM2_SR1 *(unsigned char*)0x5302
|
||||||
|
#define TIM2_SR2 *(unsigned char*)0x5303
|
||||||
|
#define TIM2_EGR *(unsigned char*)0x5304
|
||||||
|
#define TIM2_CCMR1 *(unsigned char*)0x5305
|
||||||
|
#define TIM2_CCMR2 *(unsigned char*)0x5306
|
||||||
|
#define TIM2_CCMR3 *(unsigned char*)0x5307
|
||||||
|
#define TIM2_CCER1 *(unsigned char*)0x5308
|
||||||
|
#define TIM2_CCER2 *(unsigned char*)0x5309
|
||||||
|
#define TIM2_CNTRH *(unsigned char*)0x530A
|
||||||
|
#define TIM2_CNTRL *(unsigned char*)0x530B
|
||||||
|
#define TIM2_PSCR *(unsigned char*)0x530C
|
||||||
|
#define TIM2_ARRH *(unsigned char*)0x530D
|
||||||
|
#define TIM2_ARRL *(unsigned char*)0x530E
|
||||||
|
#define TIM2_CCR1H *(unsigned char*)0x530F
|
||||||
|
#define TIM2_CCR1L *(unsigned char*)0x5310
|
||||||
|
#define TIM2_CCR2H *(unsigned char*)0x5311
|
||||||
|
#define TIM2_CCR2L *(unsigned char*)0x5312
|
||||||
|
#define TIM2_CCR3H *(unsigned char*)0x5313
|
||||||
|
#define TIM2_CCR3L *(unsigned char*)0x5314
|
||||||
|
#elif defined STM8S003
|
||||||
|
#define TIM2_IER *(unsigned char*)0x5303
|
||||||
|
#define TIM2_SR1 *(unsigned char*)0x5304
|
||||||
|
#define TIM2_SR2 *(unsigned char*)0x5305
|
||||||
|
#define TIM2_EGR *(unsigned char*)0x5306
|
||||||
|
#define TIM2_CCMR1 *(unsigned char*)0x5307
|
||||||
|
#define TIM2_CCMR2 *(unsigned char*)0x5308
|
||||||
|
#define TIM2_CCMR3 *(unsigned char*)0x5309
|
||||||
|
#define TIM2_CCER1 *(unsigned char*)0x530A
|
||||||
|
#define TIM2_CCER2 *(unsigned char*)0x530B
|
||||||
|
#define TIM2_CNTRH *(unsigned char*)0x530C
|
||||||
|
#define TIM2_CNTRL *(unsigned char*)0x530D
|
||||||
|
#define TIM2_PSCR *(unsigned char*)0x530E
|
||||||
|
#define TIM2_ARRH *(unsigned char*)0x530F
|
||||||
|
#define TIM2_ARRL *(unsigned char*)0x5310
|
||||||
|
#define TIM2_CCR1H *(unsigned char*)0x5311
|
||||||
|
#define TIM2_CCR1L *(unsigned char*)0x5312
|
||||||
|
#define TIM2_CCR2H *(unsigned char*)0x5313
|
||||||
|
#define TIM2_CCR2L *(unsigned char*)0x5314
|
||||||
|
#define TIM2_CCR3H *(unsigned char*)0x5315
|
||||||
|
#define TIM2_CCR3L *(unsigned char*)0x5316
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* TIM3 */
|
||||||
|
#if defined STM8S105 || defined STM8S103
|
||||||
|
#define TIM3_CR1 *(unsigned char*)0x5320
|
||||||
|
#define TIM3_IER *(unsigned char*)0x5321
|
||||||
|
#define TIM3_SR1 *(unsigned char*)0x5322
|
||||||
|
#define TIM3_SR2 *(unsigned char*)0x5323
|
||||||
|
#define TIM3_EGR *(unsigned char*)0x5324
|
||||||
|
#define TIM3_CCMR1 *(unsigned char*)0x5325
|
||||||
|
#define TIM3_CCMR2 *(unsigned char*)0x5326
|
||||||
|
#define TIM3_CCER1 *(unsigned char*)0x5327
|
||||||
|
#define TIM3_CNTRH *(unsigned char*)0x5328
|
||||||
|
#define TIM3_CNTRL *(unsigned char*)0x5329
|
||||||
|
#define TIM3_PSCR *(unsigned char*)0x532A
|
||||||
|
#define TIM3_ARRH *(unsigned char*)0x532B
|
||||||
|
#define TIM3_ARRL *(unsigned char*)0x532C
|
||||||
|
#define TIM3_CCR1H *(unsigned char*)0x532D
|
||||||
|
#define TIM3_CCR1L *(unsigned char*)0x532E
|
||||||
|
#define TIM3_CCR2H *(unsigned char*)0x532F
|
||||||
|
#define TIM3_CCR2L *(unsigned char*)0x5330
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* TIM4 */
|
||||||
|
#define TIM4_CR1 *(unsigned char*)0x5340
|
||||||
|
#if defined STM8S105 || defined STM8S103
|
||||||
|
#define TIM4_IER *(unsigned char*)0x5341
|
||||||
|
#define TIM4_SR *(unsigned char*)0x5342
|
||||||
|
#define TIM4_EGR *(unsigned char*)0x5343
|
||||||
|
#define TIM4_CNTR *(unsigned char*)0x5344
|
||||||
|
#define TIM4_PSCR *(unsigned char*)0x5345
|
||||||
|
#define TIM4_ARR *(unsigned char*)0x5346
|
||||||
|
#elif defined STM8S003
|
||||||
|
#define TIM4_IER *(unsigned char*)0x5343
|
||||||
|
#define TIM4_SR *(unsigned char*)0x5344
|
||||||
|
#define TIM4_EGR *(unsigned char*)0x5345
|
||||||
|
#define TIM4_CNTR *(unsigned char*)0x5346
|
||||||
|
#define TIM4_PSCR *(unsigned char*)0x5347
|
||||||
|
#define TIM4_ARR *(unsigned char*)0x5348
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ------------------- ADC ------------------- */
|
||||||
|
#define ADC_DB0RH *(unsigned char*)0x53E0
|
||||||
|
#define ADC_DB0RL *(unsigned char*)0x53E1
|
||||||
|
#define ADC_DB1RH *(unsigned char*)0x53E2
|
||||||
|
#define ADC_DB1RL *(unsigned char*)0x53E3
|
||||||
|
#define ADC_DB2RH *(unsigned char*)0x53E4
|
||||||
|
#define ADC_DB2RL *(unsigned char*)0x53E5
|
||||||
|
#define ADC_DB3RH *(unsigned char*)0x53E6
|
||||||
|
#define ADC_DB3RL *(unsigned char*)0x53E7
|
||||||
|
#define ADC_DB4RH *(unsigned char*)0x53E8
|
||||||
|
#define ADC_DB4RL *(unsigned char*)0x53E9
|
||||||
|
#define ADC_DB5RH *(unsigned char*)0x53EA
|
||||||
|
#define ADC_DB5RL *(unsigned char*)0x53EB
|
||||||
|
#define ADC_DB6RH *(unsigned char*)0x53EC
|
||||||
|
#define ADC_DB6RL *(unsigned char*)0x53ED
|
||||||
|
#define ADC_DB7RH *(unsigned char*)0x53EE
|
||||||
|
#define ADC_DB7RL *(unsigned char*)0x53EF
|
||||||
|
#define ADC_DB8RH *(unsigned char*)0x53F0
|
||||||
|
#define ADC_DB8RL *(unsigned char*)0x53F1
|
||||||
|
#define ADC_DB9RH *(unsigned char*)0x53F2
|
||||||
|
#define ADC_DB9RL *(unsigned char*)0x53F3
|
||||||
|
#define ADC_CSR *(unsigned char*)0x5400
|
||||||
|
#define ADC_CR1 *(unsigned char*)0x5401
|
||||||
|
#define ADC_CR2 *(unsigned char*)0x5402
|
||||||
|
#define ADC_CR3 *(unsigned char*)0x5403
|
||||||
|
#define ADC_DRH *(unsigned char*)0x5404
|
||||||
|
#define ADC_DRL *(unsigned char*)0x5405
|
||||||
|
#define ADC_TDRH *(unsigned char*)0x5406
|
||||||
|
#define ADC_TDRL *(unsigned char*)0x5407
|
||||||
|
#define ADC_HTRH *(unsigned char*)0x5408
|
||||||
|
#define ADC_HTRL *(unsigned char*)0x5409
|
||||||
|
#define ADC_LTRH *(unsigned char*)0x540A
|
||||||
|
#define ADC_LTRL *(unsigned char*)0x540B
|
||||||
|
#define ADC_AWSRH *(unsigned char*)0x540C
|
||||||
|
#define ADC_AWSRL *(unsigned char*)0x540D
|
||||||
|
#define ADC_AWCRH *(unsigned char*)0x540E
|
||||||
|
#define ADC_AWCRL *(unsigned char*)0x540F
|
||||||
|
|
||||||
|
/* ------------------- swim control ------------------- */
|
||||||
|
#define CFG_GCR *(unsigned char*)0x7F60
|
||||||
|
#define SWIM_CSR *(unsigned char*)0x7F80
|
||||||
|
|
||||||
|
/* ------------------- ITC ------------------- */
|
||||||
|
#define ITC_SPR1 *(unsigned char*)0x7F70
|
||||||
|
#define ITC_SPR2 *(unsigned char*)0x7F71
|
||||||
|
#define ITC_SPR3 *(unsigned char*)0x7F72
|
||||||
|
#define ITC_SPR4 *(unsigned char*)0x7F73
|
||||||
|
#define ITC_SPR5 *(unsigned char*)0x7F74
|
||||||
|
#define ITC_SPR6 *(unsigned char*)0x7F75
|
||||||
|
#define ITC_SPR7 *(unsigned char*)0x7F76
|
||||||
|
#define ITC_SPR8 *(unsigned char*)0x7F77
|
||||||
|
|
||||||
|
|
||||||
|
/* -------------------- UNIQUE ID -------------------- */
|
||||||
|
#if defined STM8S105 || defined STM8S103 // maybe some other MCU have this too???
|
||||||
|
#define U_ID00 (unsigned char*)0x48CD
|
||||||
|
#define U_ID01 (unsigned char*)0x48CE
|
||||||
|
#define U_ID02 (unsigned char*)0x48CF
|
||||||
|
#define U_ID03 (unsigned char*)0x48D0
|
||||||
|
#define U_ID04 (unsigned char*)0x48D1
|
||||||
|
#define U_ID05 (unsigned char*)0x48D2
|
||||||
|
#define U_ID06 (unsigned char*)0x48D3
|
||||||
|
#define U_ID07 (unsigned char*)0x48D4
|
||||||
|
#define U_ID08 (unsigned char*)0x48D5
|
||||||
|
#define U_ID09 (unsigned char*)0x48D6
|
||||||
|
#define U_ID10 (unsigned char*)0x48D7
|
||||||
|
#define U_ID11 (unsigned char*)0x48D8
|
||||||
|
#endif // defined STM8S105 || defined STM8S103
|
||||||
|
|
||||||
|
// CCR REGISTER: bits 3&5 should be 1 if you wanna change EXTI_CRx
|
||||||
|
#define CCR *(unsigned char*)0x7F0A
|
||||||
|
|
||||||
|
/* -------------------- OPTION BYTES -------------------- */
|
||||||
|
#if defined STM8S105
|
||||||
|
// readout protection
|
||||||
|
#define OPT0 *(unsigned char*)0x4800
|
||||||
|
// user boot code
|
||||||
|
#define OPT1 *(unsigned char*)0x4801
|
||||||
|
#define NOPT1 *(unsigned char*)0x4802
|
||||||
|
// alternate functions remapping
|
||||||
|
// | AFR7 | ... | AFR0 |
|
||||||
|
// AFR7 - PD4 = BEEP; AFR6 - PB4/PB5 = I2C; AFR5 - PB0..3 - TIM1
|
||||||
|
// AFR4 - PD7 = TIM1_CH4; AFR3 - PD0 = TIM1_BKIN
|
||||||
|
// AFR2 - PD0 = CLK_CCO; AFR1 - PA3 = TIM3_CH1, PD2 = TIM2_CH3
|
||||||
|
// AFR0 - PD3 = ADC_ETR
|
||||||
|
#define OPT2 *(unsigned char*)0x4803
|
||||||
|
#define NOPT2 *(unsigned char*)0x4804
|
||||||
|
// trim, watchdog
|
||||||
|
#define OPT3 *(unsigned char*)0x4805
|
||||||
|
#define NOPT3 *(unsigned char*)0x4806
|
||||||
|
// extclc, awu
|
||||||
|
#define OPT4 *(unsigned char*)0x4807
|
||||||
|
#define NOPT4 *(unsigned char*)0x4808
|
||||||
|
// HSE stab time
|
||||||
|
#define OPT5 *(unsigned char*)0x4809
|
||||||
|
#define NOPT5 *(unsigned char*)0x480a
|
||||||
|
// none
|
||||||
|
#define OPT6 *(unsigned char*)0x480b
|
||||||
|
#define NOPT6 *(unsigned char*)0x480c
|
||||||
|
// none
|
||||||
|
#define OPT7 *(unsigned char*)0x480d
|
||||||
|
#define NOPT7 *(unsigned char*)0x480e
|
||||||
|
// bootloader opt byte
|
||||||
|
#define OPTBL *(unsigned char*)0x487e
|
||||||
|
#define NOPTBL *(unsigned char*)0x487f
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif // __STM8L_H__
|
||||||
|
|
||||||
|
// #define *(unsigned char*)0x
|
||||||
170
220controlled_socket/src/uart.c
Normal file
170
220controlled_socket/src/uart.c
Normal file
@ -0,0 +1,170 @@
|
|||||||
|
/*
|
||||||
|
* blinky.c
|
||||||
|
*
|
||||||
|
* Copyright 2018 Edward V. Emelianoff <eddy@sao.ru>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301, USA.
|
||||||
|
*/
|
||||||
|
#include "hardware.h"
|
||||||
|
#include "uart.h"
|
||||||
|
#include "interrupts.h"
|
||||||
|
|
||||||
|
U8 UART_rx[UART_BUF_LEN]; // cycle buffer for received data
|
||||||
|
U8 UART_rx_start_i = 0; // started index of received data (from which reading starts)
|
||||||
|
U8 UART_rx_cur_i = 0; // index of current first byte in rx array (to which data will be written)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Send one byte through UART
|
||||||
|
* @param byte - data to send
|
||||||
|
*/
|
||||||
|
void uart_send_byte(U8 byte){
|
||||||
|
while(!(UART1_SR & UART_SR_TXE)); // wait until previous byte transmitted
|
||||||
|
UART1_DR = byte;
|
||||||
|
}
|
||||||
|
|
||||||
|
void newline(){
|
||||||
|
while(!(UART1_SR & UART_SR_TXE));
|
||||||
|
UART1_DR = '\n';
|
||||||
|
}
|
||||||
|
|
||||||
|
void uart_write(char *str){
|
||||||
|
while(*str){
|
||||||
|
while(!(UART1_SR & UART_SR_TXE));
|
||||||
|
UART1_CR2 |= UART_CR2_TEN;
|
||||||
|
UART1_DR = *str++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Read one byte from Rx buffer
|
||||||
|
* @param byte - where to store data read
|
||||||
|
* @return 1 in case of non-empty buffer
|
||||||
|
*/
|
||||||
|
U8 uart_read_byte(U8 *byte){
|
||||||
|
if(UART_rx_start_i == UART_rx_cur_i) // buffer is empty
|
||||||
|
return 0;
|
||||||
|
*byte = UART_rx[UART_rx_start_i++];
|
||||||
|
check_UART_pointer(UART_rx_start_i);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void printUint(U8 *val, U8 len){
|
||||||
|
unsigned long Number = 0;
|
||||||
|
U8 i = len;
|
||||||
|
char ch;
|
||||||
|
U8 decimal_buff[12]; // max len of U32 == 10 + \n + \0
|
||||||
|
if(len > 4 || len == 3 || len == 0) return;
|
||||||
|
for(i = 0; i < 12; i++)
|
||||||
|
decimal_buff[i] = 0;
|
||||||
|
decimal_buff[10] = '\n';
|
||||||
|
ch = 9;
|
||||||
|
switch(len){
|
||||||
|
case 1:
|
||||||
|
Number = *((U8*)val);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
Number = *((U16*)val);
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
Number = *((unsigned long*)val);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
do{
|
||||||
|
i = Number % 10L;
|
||||||
|
decimal_buff[ch--] = i + '0';
|
||||||
|
Number /= 10L;
|
||||||
|
}while(Number && ch > -1);
|
||||||
|
uart_write((char*)&decimal_buff[ch+1]);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* print signed long onto terminal
|
||||||
|
* max len = 10 symbols + 1 for "-" + 1 for '\n' + 1 for 0 = 13
|
||||||
|
*/
|
||||||
|
void print_long(long Number){
|
||||||
|
U8 i, L = 0;
|
||||||
|
char ch;
|
||||||
|
char decimal_buff[12];
|
||||||
|
decimal_buff[11] = 0;
|
||||||
|
ch = 11;
|
||||||
|
if(Number < 0){
|
||||||
|
Number = -Number;
|
||||||
|
L = 1;
|
||||||
|
}
|
||||||
|
do{
|
||||||
|
i = Number % 10L;
|
||||||
|
decimal_buff[--ch] = i + '0';
|
||||||
|
Number /= 10L;
|
||||||
|
}while(Number && ch > 0);
|
||||||
|
if(ch > 0 && L) decimal_buff[--ch] = '-';
|
||||||
|
uart_write(&decimal_buff[ch]);
|
||||||
|
}
|
||||||
|
|
||||||
|
U8 readInt(int *val){
|
||||||
|
unsigned long T = Global_time;
|
||||||
|
unsigned long R = 0;
|
||||||
|
int readed;
|
||||||
|
U8 sign = 0, rb, ret = 0, bad = 0;
|
||||||
|
do{
|
||||||
|
if(!uart_read_byte(&rb)) continue;
|
||||||
|
if(rb == '-' && R == 0){ // negative number
|
||||||
|
sign = 1;
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if(rb < '0' || rb > '9') break; // number ends with any non-digit symbol that will be omitted
|
||||||
|
ret = 1; // there's at least one digit
|
||||||
|
R = R * 10L + rb - '0';
|
||||||
|
if(R > 0x7fff){ // bad value
|
||||||
|
R = 0;
|
||||||
|
bad = 0;
|
||||||
|
}
|
||||||
|
}while(Global_time - T < 10000); // wait no longer than 10s
|
||||||
|
if(bad || !ret) return 0;
|
||||||
|
readed = (int) R;
|
||||||
|
if(sign) readed *= -1;
|
||||||
|
*val = readed;
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void error_msg(char *msg){
|
||||||
|
uart_write("\nERROR: ");
|
||||||
|
uart_write(msg);
|
||||||
|
uart_send_byte('\n');
|
||||||
|
}
|
||||||
|
|
||||||
|
U8 U8toHEX(U8 val){
|
||||||
|
val &= 0x0f;
|
||||||
|
if(val < 10) val += '0';
|
||||||
|
else val += 'a' - 10;
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
void printUHEX(U8 val){
|
||||||
|
uart_write("0x");
|
||||||
|
uart_send_byte(U8toHEX(val>>4)); // MSB
|
||||||
|
uart_send_byte(U8toHEX(val)); // LSB
|
||||||
|
}
|
||||||
|
|
||||||
|
void uart_init(){
|
||||||
|
// PD5 - UART1_TX
|
||||||
|
PORT(UART_PORT, DDR) |= UART_TX_PIN;
|
||||||
|
PORT(UART_PORT, CR1) |= UART_TX_PIN;
|
||||||
|
// Configure UART
|
||||||
|
// 8 bit, no parity, 1 stop (UART_CR1/3 = 0 - reset value)
|
||||||
|
// 9600 on 16MHz: DIV=0x0693 -> BRR1=0x68, BRR2=0x03
|
||||||
|
UART1_BRR1 = 0x68; UART1_BRR2 = 0x03;
|
||||||
|
UART1_CR2 = UART_CR2_TEN | UART_CR2_REN | UART_CR2_RIEN; // Allow RX/TX, generate ints on rx
|
||||||
|
}
|
||||||
48
220controlled_socket/src/uart.h
Normal file
48
220controlled_socket/src/uart.h
Normal file
@ -0,0 +1,48 @@
|
|||||||
|
/*
|
||||||
|
* blinky.h
|
||||||
|
*
|
||||||
|
* Copyright 2018 Edward V. Emelianoff <eddy@sao.ru>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||||
|
* MA 02110-1301, USA.
|
||||||
|
*/
|
||||||
|
#pragma once
|
||||||
|
#ifndef __MAIN_H__
|
||||||
|
#define __MAIN_H__
|
||||||
|
|
||||||
|
#include "stm8s.h"
|
||||||
|
|
||||||
|
extern volatile unsigned long Global_time; // global time in ms
|
||||||
|
|
||||||
|
#define UART_BUF_LEN 8 // max 7 bytes transmited in on operation
|
||||||
|
|
||||||
|
extern U8 UART_rx[];
|
||||||
|
extern U8 UART_rx_start_i;
|
||||||
|
extern U8 UART_rx_cur_i;
|
||||||
|
|
||||||
|
|
||||||
|
void uart_send_byte(U8 byte);
|
||||||
|
void uart_write(char *str);
|
||||||
|
void newline();
|
||||||
|
void printUint(U8 *val, U8 len);
|
||||||
|
void print_long(long Number);
|
||||||
|
void error_msg(char *msg);
|
||||||
|
void uart_init();
|
||||||
|
U8 uart_read_byte(U8 *byte);
|
||||||
|
void printUHEX(U8 val);
|
||||||
|
|
||||||
|
#define check_UART_pointer(x) do{if(x == UART_BUF_LEN) x = 0;}while(0)
|
||||||
|
|
||||||
|
#endif // __MAIN_H__
|
||||||
Loading…
x
Reference in New Issue
Block a user