mirror of
https://github.com/eddyem/IR-controller.git
synced 2025-12-06 02:35:14 +03:00
9632 lines
637 KiB
Plaintext
9632 lines
637 KiB
Plaintext
(kicad_pcb (version 3) (host pcbnew "(2013-feb-26)-stable")
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(general
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(links 458)
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(no_connects 0)
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(area 50.849999 56.849999 245.150001 145.150001)
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(thickness 1.6)
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(drawings 26)
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(tracks 1581)
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(zones 0)
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(modules 141)
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(nets 147)
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)
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(page A4)
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(layers
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(15 F.Cu signal)
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(2 ground.Cu power hide)
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(1 power.Cu mixed)
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(0 B.Cu signal)
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(16 B.Adhes user)
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(17 F.Adhes user)
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(18 B.Paste user)
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(19 F.Paste user)
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(20 B.SilkS user)
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(21 F.SilkS user)
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(22 B.Mask user)
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(23 F.Mask user)
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(28 Edge.Cuts user)
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)
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(setup
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(last_trace_width 2.032)
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(user_trace_width 0.254)
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(user_trace_width 0.508)
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(user_trace_width 1.016)
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(user_trace_width 2.032)
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(trace_clearance 0.1)
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(zone_clearance 0.499999)
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(zone_45_only no)
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(trace_min 0.254)
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(segment_width 0.4)
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(edge_width 0.3)
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(via_size 0.9)
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(via_drill 0.6)
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(via_min_size 0.889)
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(via_min_drill 0.508)
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(user_via 1.5 0.8)
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(uvia_size 0.508)
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(uvia_drill 0.127)
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(uvias_allowed no)
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(uvia_min_size 0.508)
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(uvia_min_drill 0.127)
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(pcb_text_width 0.3)
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(pcb_text_size 1.5 1.5)
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(mod_edge_width 0.3)
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(mod_text_size 1.5 1.5)
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(mod_text_width 0.3)
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(pad_size 0.9 0.9)
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(pad_drill 0.9)
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(pad_to_mask_clearance 0.2)
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(aux_axis_origin 51 57)
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(visible_elements FFFFFFBF)
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(pcbplotparams
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(layerselection 284196871)
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(usegerberextensions false)
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(excludeedgelayer false)
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(linewidth 50000)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15)
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(hpglpenoverlay 2)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotothertext true)
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(plotinvisibletext false)
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(padsonsilk true)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 0)
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(scaleselection 1)
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(outputdirectory ""))
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)
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(net 0 "")
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(net 1 +3.3V)
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(net 2 +5V)
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(net 3 /EP0)
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(net 4 /EP1)
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(net 5 /EP2)
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(net 6 /EP3)
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(net 7 "/Filters slit #1/+10V")
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(net 8 "/Filters slit #1/+24V")
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(net 9 "/Filters slit #1/A")
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(net 10 "/Filters slit #1/A*")
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(net 11 "/Filters slit #1/B")
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(net 12 "/Filters slit #1/B*")
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(net 13 "/Filters slit #1/SM_CLK")
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(net 14 "/Filters slit #1/SM_DIR")
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(net 15 "/Filters slit #1/SM_EN")
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(net 16 "/Filters slit #2/A")
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(net 17 "/Filters slit #2/A*")
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(net 18 "/Filters slit #2/B")
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(net 19 "/Filters slit #2/B*")
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(net 20 "/Filters slit #2/SM_DIR")
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(net 21 "/Filters slit #2/SM_EN")
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(net 22 /Hall0)
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(net 23 /Hall1)
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(net 24 /Hall2)
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(net 25 /Hall3)
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(net 26 /Hall4)
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(net 27 /Hall5)
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(net 28 /Hall6)
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(net 29 /Hall7)
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(net 30 /Hall8)
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(net 31 /Hall9)
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(net 32 "/Long stage/A")
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(net 33 "/Long stage/A*")
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(net 34 "/Long stage/B")
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(net 35 "/Long stage/B*")
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(net 36 "/Long stage/SM_CLK")
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(net 37 "/Long stage/SM_DIR")
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(net 38 "/Long stage/SM_EN")
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(net 39 /POW3)
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(net 40 /POW_LOAD)
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(net 41 "/Power MOSFET module 1/GND_OUT")
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(net 42 "/Power MOSFET module 1/ON")
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(net 43 "/Power MOSFET module 2/GND_OUT")
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(net 44 "/Power MOSFET module 2/ON")
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(net 45 "/STM32F103 module/1-WIRE")
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(net 46 "/STM32F103 module/BOOT")
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(net 47 "/STM32F103 module/DG_FEEDBACK")
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(net 48 "/STM32F103 module/EXT0")
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(net 49 "/STM32F103 module/EXT1")
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(net 50 "/STM32F103 module/EXT2")
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(net 51 "/STM32F103 module/EXT3")
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(net 52 "/STM32F103 module/I2C_SCL/CANRX")
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(net 53 "/STM32F103 module/I2C_SDA/CANTX")
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(net 54 "/STM32F103 module/POW3_FEEDBACK")
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(net 55 "/STM32F103 module/RS-232 level converter/UART_RX")
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(net 56 "/STM32F103 module/RS-232 level converter/UART_RX1")
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(net 57 "/STM32F103 module/RS-232 level converter/UART_TX")
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(net 58 "/STM32F103 module/RS-232 level converter/UART_TX1")
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(net 59 "/STM32F103 module/RST")
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(net 60 "/STM32F103 module/SPI1_MISO")
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(net 61 "/STM32F103 module/SPI1_MOSI")
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(net 62 "/STM32F103 module/SPI1_SCK")
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(net 63 "/STM32F103 module/SPI2_MISO")
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(net 64 "/STM32F103 module/SPI2_MOSI")
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(net 65 "/STM32F103 module/SPI2_SCK")
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(net 66 "/STM32F103 module/U10")
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(net 67 "/STM32F103 module/USB input circuit/USB_DISC")
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(net 68 "/STM32F103 module/USB input circuit/USB_DM")
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(net 69 "/STM32F103 module/USB input circuit/USB_DP")
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(net 70 "/STM32F103 module/USB input circuit/USB_POWER")
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(net 71 "/STM32F103 module/VDDA")
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(net 72 "/Short stage/A")
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(net 73 "/Short stage/A*")
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(net 74 "/Short stage/B")
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(net 75 "/Short stage/B*")
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(net 76 "/Short stage/SM_DIR")
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(net 77 "/Short stage/SM_EN")
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(net 78 "/Shutter MOSFET/+36V")
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(net 79 "/Shutter MOSFET/EF")
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(net 80 "/Shutter MOSFET/IN1")
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(net 81 "/Shutter MOSFET/IN2")
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(net 82 "/Shutter MOSFET/OUT1")
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(net 83 "/Shutter MOSFET/OUT2")
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(net 84 "/Shutter MOSFET/Sense")
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(net 85 /T1_0)
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(net 86 /T1_1)
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(net 87 /T1_2)
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(net 88 /T1_3)
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(net 89 /T1_4)
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(net 90 /T1_5)
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(net 91 /T1_6)
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(net 92 /T1_7)
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(net 93 "/Turret slits/A")
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(net 94 "/Turret slits/A*")
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(net 95 "/Turret slits/B")
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(net 96 "/Turret slits/B*")
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(net 97 "/Turret slits/SM_DIR")
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(net 98 "/Turret slits/SM_EN")
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(net 99 GND)
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(net 100 N-00000101)
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(net 101 N-00000105)
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(net 102 N-00000106)
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(net 103 N-00000121)
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(net 104 N-00000122)
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(net 105 N-00000123)
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(net 106 N-00000124)
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(net 107 N-00000125)
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(net 108 N-00000126)
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(net 109 N-00000128)
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(net 110 N-00000129)
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(net 111 N-00000131)
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(net 112 N-00000132)
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(net 113 N-00000133)
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(net 114 N-00000134)
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(net 115 N-00000135)
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(net 116 N-00000136)
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(net 117 N-00000137)
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(net 118 N-00000139)
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(net 119 N-00000140)
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(net 120 N-00000141)
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(net 121 N-00000142)
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(net 122 N-00000144)
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(net 123 N-00000145)
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(net 124 N-00000146)
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(net 125 N-00000147)
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(net 126 N-00000148)
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(net 127 N-00000152)
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(net 128 N-00000153)
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(net 129 N-00000154)
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(net 130 N-00000155)
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(net 131 N-00000156)
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(net 132 N-00000169)
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(net 133 N-0000017)
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(net 134 N-00000170)
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(net 135 N-00000171)
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(net 136 N-00000172)
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(net 137 N-00000173)
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(net 138 N-00000174)
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(net 139 N-00000175)
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(net 140 N-0000037)
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(net 141 N-0000070)
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(net 142 N-0000071)
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(net 143 N-0000072)
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(net 144 N-0000073)
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(net 145 N-0000074)
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(net 146 N-0000095)
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(net_class Default "This is the default net class."
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(clearance 0.1)
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(trace_width 0.254)
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(via_dia 0.9)
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(via_drill 0.6)
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(uvia_dia 0.508)
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(uvia_drill 0.127)
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(add_net "")
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(add_net +3.3V)
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(add_net /EP0)
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(add_net /EP1)
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(add_net /EP2)
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(add_net /EP3)
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(add_net "/Filters slit #1/SM_CLK")
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(add_net "/Filters slit #1/SM_DIR")
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(add_net "/Filters slit #1/SM_EN")
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(add_net "/Filters slit #2/SM_DIR")
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(add_net "/Filters slit #2/SM_EN")
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(add_net /Hall0)
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(add_net /Hall1)
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(add_net /Hall2)
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(add_net /Hall3)
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(add_net /Hall4)
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(add_net /Hall5)
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(add_net /Hall6)
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(add_net /Hall7)
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(add_net /Hall8)
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(add_net /Hall9)
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(add_net "/Long stage/SM_CLK")
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(add_net "/Long stage/SM_DIR")
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(add_net "/Long stage/SM_EN")
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(add_net /POW3)
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(add_net /POW_LOAD)
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(add_net "/Power MOSFET module 1/ON")
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(add_net "/Power MOSFET module 2/ON")
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(add_net "/STM32F103 module/1-WIRE")
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(add_net "/STM32F103 module/BOOT")
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(add_net "/STM32F103 module/DG_FEEDBACK")
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(add_net "/STM32F103 module/EXT0")
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(add_net "/STM32F103 module/EXT1")
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(add_net "/STM32F103 module/EXT2")
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(add_net "/STM32F103 module/EXT3")
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(add_net "/STM32F103 module/I2C_SCL/CANRX")
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(add_net "/STM32F103 module/I2C_SDA/CANTX")
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(add_net "/STM32F103 module/POW3_FEEDBACK")
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(add_net "/STM32F103 module/RS-232 level converter/UART_RX")
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(add_net "/STM32F103 module/RS-232 level converter/UART_RX1")
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(add_net "/STM32F103 module/RS-232 level converter/UART_TX")
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(add_net "/STM32F103 module/RS-232 level converter/UART_TX1")
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(add_net "/STM32F103 module/RST")
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(add_net "/STM32F103 module/SPI1_MISO")
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(add_net "/STM32F103 module/SPI1_MOSI")
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(add_net "/STM32F103 module/SPI1_SCK")
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(add_net "/STM32F103 module/SPI2_MISO")
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(add_net "/STM32F103 module/SPI2_MOSI")
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(add_net "/STM32F103 module/SPI2_SCK")
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(add_net "/STM32F103 module/U10")
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(add_net "/STM32F103 module/USB input circuit/USB_DISC")
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(add_net "/STM32F103 module/USB input circuit/USB_DM")
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(add_net "/STM32F103 module/USB input circuit/USB_DP")
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(add_net "/STM32F103 module/USB input circuit/USB_POWER")
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(add_net "/STM32F103 module/VDDA")
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(add_net "/Short stage/SM_DIR")
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(add_net "/Short stage/SM_EN")
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(add_net "/Shutter MOSFET/EF")
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(add_net "/Shutter MOSFET/IN1")
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(add_net "/Shutter MOSFET/IN2")
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(add_net "/Shutter MOSFET/Sense")
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(add_net /T1_0)
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(add_net /T1_1)
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(add_net /T1_2)
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(add_net /T1_3)
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(add_net /T1_4)
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(add_net /T1_5)
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(add_net /T1_6)
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(add_net /T1_7)
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(add_net "/Turret slits/SM_DIR")
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(add_net "/Turret slits/SM_EN")
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(add_net GND)
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(add_net N-00000101)
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(add_net N-00000105)
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(add_net N-00000106)
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(add_net N-00000121)
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(add_net N-00000122)
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(add_net N-00000123)
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(add_net N-00000124)
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(add_net N-00000125)
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(add_net N-00000126)
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(add_net N-00000128)
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(add_net N-00000129)
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(add_net N-00000131)
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(add_net N-00000132)
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(add_net N-00000133)
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(add_net N-00000134)
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(add_net N-00000135)
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(add_net N-00000136)
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(add_net N-00000137)
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(add_net N-00000139)
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(add_net N-00000140)
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(add_net N-00000141)
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(add_net N-00000142)
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(add_net N-00000144)
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(add_net N-00000145)
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(add_net N-00000146)
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(add_net N-00000147)
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(add_net N-00000148)
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(add_net N-00000152)
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(add_net N-00000153)
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(add_net N-00000154)
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(add_net N-00000155)
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(add_net N-00000156)
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(add_net N-00000169)
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(add_net N-0000017)
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(add_net N-00000170)
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(add_net N-00000171)
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(add_net N-00000172)
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(add_net N-00000173)
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(add_net N-00000174)
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(add_net N-00000175)
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(add_net N-0000037)
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(add_net N-0000070)
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(add_net N-0000071)
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(add_net N-0000072)
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(add_net N-0000073)
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(add_net N-0000074)
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(add_net N-0000095)
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)
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(net_class low_power ""
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(clearance 0.1)
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(trace_width 0.508)
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(via_dia 0.9)
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(via_drill 0.6)
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(uvia_dia 0.508)
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(uvia_drill 0.127)
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(add_net +5V)
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(add_net "/Filters slit #1/+24V")
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)
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|
|
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(net_class power ""
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(clearance 0.254)
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(trace_width 1.016)
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(via_dia 1.5)
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(via_drill 0.8)
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(uvia_dia 0.508)
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(uvia_drill 0.127)
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(add_net "/Filters slit #1/+10V")
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(add_net "/Filters slit #1/A")
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(add_net "/Filters slit #1/A*")
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(add_net "/Filters slit #1/B")
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(add_net "/Filters slit #1/B*")
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(add_net "/Filters slit #2/A")
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(add_net "/Filters slit #2/A*")
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(add_net "/Filters slit #2/B")
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(add_net "/Filters slit #2/B*")
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(add_net "/Long stage/A")
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(add_net "/Long stage/A*")
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(add_net "/Long stage/B")
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(add_net "/Long stage/B*")
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(add_net "/Power MOSFET module 1/GND_OUT")
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(add_net "/Power MOSFET module 2/GND_OUT")
|
|
(add_net "/Short stage/A")
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(add_net "/Short stage/A*")
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(add_net "/Short stage/B")
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(add_net "/Short stage/B*")
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(add_net "/Shutter MOSFET/+36V")
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(add_net "/Shutter MOSFET/OUT1")
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(add_net "/Shutter MOSFET/OUT2")
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(add_net "/Turret slits/A")
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(add_net "/Turret slits/A*")
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(add_net "/Turret slits/B")
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(add_net "/Turret slits/B*")
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)
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(module VASCH10x2 (layer F.Cu) (tedit 54620956) (tstamp 53C7AEFB)
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(at 175.7172 139.9794 180)
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(descr CONNECTOR)
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(tags CONNECTOR)
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(path /53CA50BA)
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(attr virtual)
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(fp_text reference XP7 (at -19.3548 -2.2606 180) (layer F.SilkS)
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(effects (font (size 1.778 1.778) (thickness 0.0889)))
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)
|
|
(fp_text value Power (at -21.0058 1.8034 180) (layer F.SilkS)
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(effects (font (size 1.778 1.778) (thickness 0.0889)))
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)
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(fp_line (start 15.875 3.81) (end 16.51 4.445) (layer F.SilkS) (width 0.254))
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(fp_line (start 15.875 -3.81) (end 16.51 -4.445) (layer F.SilkS) (width 0.254))
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|
(fp_line (start -15.875 3.81) (end -16.51 4.445) (layer F.SilkS) (width 0.254))
|
|
(fp_line (start -16.51 -4.445) (end -15.875 -3.81) (layer F.SilkS) (width 0.254))
|
|
(fp_line (start -15.875 -3.81) (end -15.875 3.81) (layer F.SilkS) (width 0.254))
|
|
(fp_line (start -15.875 3.81) (end -1.905 3.81) (layer F.SilkS) (width 0.254))
|
|
(fp_line (start -1.905 3.81) (end -1.905 4.445) (layer F.SilkS) (width 0.254))
|
|
(fp_line (start -15.875 -3.81) (end 15.875 -3.81) (layer F.SilkS) (width 0.254))
|
|
(fp_line (start 15.875 -3.81) (end 15.875 3.81) (layer F.SilkS) (width 0.254))
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(pad 17 smd rect (at -7.747 1.99898) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 80 "/Shutter MOSFET/IN1")
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)
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(pad 18 smd rect (at -7.747 2.49936) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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)
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(pad 19 smd rect (at -7.747 2.99974) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 99 GND)
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)
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(pad 20 smd rect (at -7.747 3.49758) (size 1.20142 0.30226)
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(layers F.Cu F.Paste F.Mask)
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(net 99 GND)
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)
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(pad 21 smd rect (at -7.747 3.99796) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 71 "/STM32F103 module/VDDA")
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)
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(pad 22 smd rect (at -7.747 4.49834) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 71 "/STM32F103 module/VDDA")
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)
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(pad 23 smd rect (at -7.747 4.99872) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 66 "/STM32F103 module/U10")
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)
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(pad 24 smd rect (at -7.747 5.4991) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 84 "/Shutter MOSFET/Sense")
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)
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(pad 25 smd rect (at -7.747 5.99948) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 45 "/STM32F103 module/1-WIRE")
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)
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(pad 26 smd rect (at -5.99948 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 45 "/STM32F103 module/1-WIRE")
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)
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(pad 27 smd rect (at -5.4991 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 99 GND)
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)
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(pad 28 smd rect (at -4.99872 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 1 +3.3V)
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)
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(pad 29 smd rect (at -4.49834 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 92 /T1_7)
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)
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(pad 30 smd rect (at -3.99796 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 91 /T1_6)
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)
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(pad 31 smd rect (at -3.49758 7.747) (size 0.30226 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 90 /T1_5)
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)
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(pad 32 smd rect (at -2.99974 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 89 /T1_4)
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)
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(pad 33 smd rect (at -2.49936 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 88 /T1_3)
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)
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(pad 34 smd rect (at -1.99898 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 87 /T1_2)
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)
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(pad 35 smd rect (at -1.4986 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 86 /T1_1)
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)
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(pad 36 smd rect (at -0.99822 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 85 /T1_0)
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)
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(pad 37 smd rect (at -0.49784 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 146 N-0000095)
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)
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(pad 38 smd rect (at 0 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 98 "/Turret slits/SM_EN")
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)
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(pad 39 smd rect (at 0.49784 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 15 "/Filters slit #1/SM_EN")
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)
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(pad 40 smd rect (at 0.99822 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 21 "/Filters slit #2/SM_EN")
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)
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(pad 41 smd rect (at 1.4986 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 38 "/Long stage/SM_EN")
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)
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(pad 42 smd rect (at 1.99898 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 77 "/Short stage/SM_EN")
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)
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(pad 43 smd rect (at 2.49936 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 44 "/Power MOSFET module 2/ON")
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)
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(pad 44 smd rect (at 2.99974 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 42 "/Power MOSFET module 1/ON")
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)
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(pad 45 smd rect (at 3.49758 7.747) (size 0.30226 1.20142)
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(layers F.Cu F.Paste F.Mask)
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)
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(pad 46 smd rect (at 3.99796 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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)
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(pad 47 smd rect (at 4.49834 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 57 "/STM32F103 module/RS-232 level converter/UART_TX")
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)
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(pad 48 smd rect (at 4.99872 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 55 "/STM32F103 module/RS-232 level converter/UART_RX")
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)
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(pad 49 smd rect (at 5.4991 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 99 GND)
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)
|
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(pad 50 smd rect (at 5.99948 7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 1 +3.3V)
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)
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(pad 51 smd rect (at 7.747 5.99948) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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)
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(pad 52 smd rect (at 7.747 5.4991) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 65 "/STM32F103 module/SPI2_SCK")
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)
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(pad 53 smd rect (at 7.747 4.99872) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 63 "/STM32F103 module/SPI2_MISO")
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)
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(pad 54 smd rect (at 7.747 4.49834) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 64 "/STM32F103 module/SPI2_MOSI")
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)
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(pad 55 smd rect (at 7.747 3.99796) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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)
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(pad 56 smd rect (at 7.747 3.49758) (size 1.20142 0.30226)
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(layers F.Cu F.Paste F.Mask)
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)
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(pad 57 smd rect (at 7.747 2.99974) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 48 "/STM32F103 module/EXT0")
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)
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(pad 58 smd rect (at 7.747 2.49936) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 49 "/STM32F103 module/EXT1")
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)
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(pad 59 smd rect (at 7.747 1.99898) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 50 "/STM32F103 module/EXT2")
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)
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(pad 60 smd rect (at 7.747 1.4986) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 51 "/STM32F103 module/EXT3")
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)
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(pad 61 smd rect (at 7.747 0.99822) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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)
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(pad 62 smd rect (at 7.747 0.49784) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 36 "/Long stage/SM_CLK")
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)
|
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(pad 63 smd rect (at 7.747 0) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 13 "/Filters slit #1/SM_CLK")
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)
|
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(pad 64 smd rect (at 7.747 -0.49784) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 3 /EP0)
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)
|
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(pad 65 smd rect (at 7.747 -0.99822) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 4 /EP1)
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)
|
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(pad 66 smd rect (at 7.747 -1.4986) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 5 /EP2)
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)
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(pad 67 smd rect (at 7.747 -1.99898) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 6 /EP3)
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)
|
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(pad 68 smd rect (at 7.747 -2.49936) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 58 "/STM32F103 module/RS-232 level converter/UART_TX1")
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)
|
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(pad 69 smd rect (at 7.747 -2.99974) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 56 "/STM32F103 module/RS-232 level converter/UART_RX1")
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)
|
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(pad 70 smd rect (at 7.747 -3.49758) (size 1.20142 0.30226)
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(layers F.Cu F.Paste F.Mask)
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(net 68 "/STM32F103 module/USB input circuit/USB_DM")
|
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)
|
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(pad 71 smd rect (at 7.747 -3.99796) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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(net 69 "/STM32F103 module/USB input circuit/USB_DP")
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)
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(pad 72 smd rect (at 7.747 -4.49834) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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)
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(pad 73 smd rect (at 7.747 -4.99872) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
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)
|
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(pad 74 smd rect (at 7.747 -5.4991) (size 1.20142 0.29972)
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(layers F.Cu F.Paste F.Mask)
|
|
(net 99 GND)
|
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)
|
|
(pad 75 smd rect (at 7.747 -5.99948) (size 1.20142 0.29972)
|
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(layers F.Cu F.Paste F.Mask)
|
|
(net 1 +3.3V)
|
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)
|
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(pad 76 smd rect (at 5.99948 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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)
|
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(pad 77 smd rect (at 5.4991 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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)
|
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(pad 78 smd rect (at 4.99872 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
|
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(net 70 "/STM32F103 module/USB input circuit/USB_POWER")
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)
|
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(pad 79 smd rect (at 4.49834 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 67 "/STM32F103 module/USB input circuit/USB_DISC")
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)
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(pad 80 smd rect (at 3.99796 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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)
|
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(pad 81 smd rect (at 3.49758 -7.747) (size 0.30226 1.20142)
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(layers F.Cu F.Paste F.Mask)
|
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(net 22 /Hall0)
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)
|
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(pad 82 smd rect (at 2.99974 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
|
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(net 23 /Hall1)
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)
|
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(pad 83 smd rect (at 2.49936 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 24 /Hall2)
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)
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(pad 84 smd rect (at 1.99898 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 25 /Hall3)
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)
|
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(pad 85 smd rect (at 1.4986 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 26 /Hall4)
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)
|
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(pad 86 smd rect (at 0.99822 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 27 /Hall5)
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)
|
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(pad 87 smd rect (at 0.49784 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
|
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(net 28 /Hall6)
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)
|
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(pad 88 smd rect (at 0 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 29 /Hall7)
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)
|
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(pad 89 smd rect (at -0.49784 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 62 "/STM32F103 module/SPI1_SCK")
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)
|
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(pad 90 smd rect (at -0.99822 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 60 "/STM32F103 module/SPI1_MISO")
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)
|
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(pad 91 smd rect (at -1.4986 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 61 "/STM32F103 module/SPI1_MOSI")
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)
|
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(pad 92 smd rect (at -1.99898 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
|
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(net 30 /Hall8)
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)
|
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(pad 93 smd rect (at -2.49936 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 31 /Hall9)
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)
|
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(pad 94 smd rect (at -2.99974 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
|
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(net 46 "/STM32F103 module/BOOT")
|
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)
|
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(pad 95 smd rect (at -3.49758 -7.747) (size 0.30226 1.20142)
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(layers F.Cu F.Paste F.Mask)
|
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(net 52 "/STM32F103 module/I2C_SCL/CANRX")
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)
|
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(pad 96 smd rect (at -3.99796 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 53 "/STM32F103 module/I2C_SDA/CANTX")
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)
|
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(pad 97 smd rect (at -4.49834 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 97 "/Turret slits/SM_DIR")
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)
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(pad 98 smd rect (at -4.99872 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
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(net 14 "/Filters slit #1/SM_DIR")
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)
|
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(pad 99 smd rect (at -5.4991 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
|
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(net 99 GND)
|
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)
|
|
(pad 100 smd rect (at -5.99948 -7.747) (size 0.29972 1.20142)
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(layers F.Cu F.Paste F.Mask)
|
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(net 1 +3.3V)
|
|
)
|
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)
|
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|
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(module TO220-7-12 (layer F.Cu) (tedit 5462097E) (tstamp 53BBED33)
|
|
(at 188.5315 130.4925 270)
|
|
(descr "Regulateur TO220 serie LM78xx")
|
|
(tags "TR TO220")
|
|
(path /53AE6F08/53C09F3E)
|
|
(fp_text reference DA2 (at -4.7625 4.1275 360) (layer F.SilkS)
|
|
(effects (font (size 1.524 1.016) (thickness 0.2032)))
|
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)
|
|
(fp_text value TLE5205 (at 0 -6.35 270) (layer F.SilkS)
|
|
(effects (font (size 1.524 1.016) (thickness 0.2032)))
|
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)
|
|
(fp_line (start 3.175 5.08) (end -3.175 5.08) (layer F.SilkS) (width 0.381))
|
|
(fp_line (start -3.175 -5.08) (end 3.175 -5.08) (layer F.SilkS) (width 0.381))
|
|
(fp_line (start 3.175 -5.08) (end 3.81 -5.08) (layer F.SilkS) (width 0.381))
|
|
(fp_line (start 3.81 -5.08) (end 3.81 5.08) (layer F.SilkS) (width 0.381))
|
|
(fp_line (start 3.81 5.08) (end 3.175 5.08) (layer F.SilkS) (width 0.381))
|
|
(fp_line (start 3.175 -5.08) (end 3.175 5.08) (layer F.SilkS) (width 0.381))
|
|
(fp_line (start -3.175 5.08) (end -3.175 -5.08) (layer F.SilkS) (width 0.381))
|
|
(pad 7 thru_hole circle (at 1.27 3.81 270) (size 1.5 1.5) (drill 0.8)
|
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(layers *.Cu *.Mask F.SilkS)
|
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(net 83 "/Shutter MOSFET/OUT2")
|
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)
|
|
(pad 1 thru_hole rect (at 1.27 -3.81 270) (size 1.5 1.5) (drill 0.8)
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(layers *.Cu *.Mask F.SilkS)
|
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(net 82 "/Shutter MOSFET/OUT1")
|
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)
|
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(pad 5 thru_hole circle (at 1.27 1.27 270) (size 1.5 1.5) (drill 0.8)
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(layers *.Cu *.Mask F.SilkS)
|
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(net 81 "/Shutter MOSFET/IN2")
|
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)
|
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(pad 6 thru_hole circle (at -1.27 2.54 270) (size 1.5 1.5) (drill 0.8)
|
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(layers *.Cu *.Mask F.SilkS)
|
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(net 125 N-00000147)
|
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)
|
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(pad 2 thru_hole circle (at -1.27 -2.54 270) (size 1.5 1.5) (drill 0.8)
|
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(layers *.Cu *.Mask F.SilkS)
|
|
(net 79 "/Shutter MOSFET/EF")
|
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)
|
|
(pad 3 thru_hole circle (at 1.27 -1.27 270) (size 1.5 1.5) (drill 0.8)
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(layers *.Cu *.Mask F.SilkS)
|
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(net 80 "/Shutter MOSFET/IN1")
|
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)
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(module SOT23_6 (layer F.Cu) (tedit 54620A28) (tstamp 53BBED9E)
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(path /53973803/53976CAB/5395C045)
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(model smd/SOT23_6.wrl
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(layers F.Cu F.Paste F.Mask)
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(net 59 "/STM32F103 module/RST")
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(pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
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(layers F.Cu F.Paste F.Mask)
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(net 99 GND)
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(module SM0805 (layer F.Cu) (tedit 546203A0) (tstamp 53BF8B64)
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(model smd/chip_cms.wrl
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(pad 2 smd rect (at 0.9525 0 180) (size 0.889 1.397)
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(model smd/chip_cms.wrl
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(module SM0805 (layer F.Cu) (tedit 546209B9) (tstamp 53BBEE79)
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(at 124.6886 121.1326 90)
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(at 88.519 95.6945 180)
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(module SM0603 locked (layer F.Cu) (tedit 5463268C) (tstamp 5463258B)
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(module DB9-F (layer F.Cu) (tedit 546362FD) (tstamp 53BBF4BB)
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(at 60.5282 121.5 90)
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(descr "Connecteur DB9 femelle couche")
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(module DB9-M (layer F.Cu) (tedit 546363D8) (tstamp 5464F8AB)
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(at 60.5282 81 90)
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(descr "Connecteur DB9 male couche")
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(tags "CONN DB9")
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(module SM0805 (layer B.Cu) (tedit 42806E04) (tstamp 547B111F)
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(at 124.714 83.312 90)
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(path /547DB437)
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(module SIP-4-RO (layer F.Cu) (tedit 53BBF819) (tstamp 54746759)
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(module PIN_ARRAY_1 (layer F.Cu) (tedit 4E4E744E) (tstamp 54746CB5)
|
|
(at 97.79 79.248)
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(descr "1 pin")
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(tags "CONN DEV")
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(module PIN_ARRAY_1 (layer F.Cu) (tedit 4E4E744E) (tstamp 54746CC7)
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(at 237.49 118.491)
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(descr "1 pin")
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(module hole_3mm (layer F.Cu) (tedit 5474921E) (tstamp 54748751)
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(at 54 142)
|
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