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modified schematics

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This commit is contained in:
eddyem
2014-12-02 17:46:21 +03:00
parent 7455c600b0
commit 9b855489d5
33 changed files with 9128 additions and 4990 deletions
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207
with_opencm3/hardware_ini.c
View File

@@ -27,6 +27,7 @@
#include "main.h"
#include "hardware_ini.h"
#include "onewire.h"
volatile uint16_t ADC_value[8]; // ADC DMA value
@@ -142,6 +143,30 @@ void SysTick_init(){
*/
uint8_t adc_channel_array[16] = {9,8,15,14,7,6,5,4};
#define ADC_CHANNELS_NUMBER 8
/**
* Turn on ADC DMA for filling temperatures buffer
*/
void adc_dma_on(){
// first configure DMA1 Channel1 (ADC1)
rcc_periph_clock_enable(RCC_DMA1); // RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
dma_channel_reset(DMA1, DMA_CHANNEL1); //DMA_DeInit(DMA1_Channel1);
dma_set_peripheral_address(DMA1, DMA_CHANNEL1, (uint32_t) &(ADC_DR(ADC1))); // DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
dma_set_memory_address(DMA1, DMA_CHANNEL1, (uint32_t) ADC_value); // DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADC_value;
dma_set_number_of_data(DMA1, DMA_CHANNEL1, ADC_CHANNELS_NUMBER); // DMA_InitStructure.DMA_BufferSize = 1;
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
dma_disable_peripheral_increment_mode(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
dma_set_peripheral_size(DMA1, DMA_CHANNEL1, DMA_CCR_PSIZE_16BIT); // DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
dma_set_memory_size(DMA1, DMA_CHANNEL1, DMA_CCR_MSIZE_16BIT); // DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
dma_enable_circular_mode(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
dma_set_priority(DMA1, DMA_CHANNEL1, DMA_CCR_PL_HIGH); // DMA_InitStructure.DMA_Priority = DMA_Priority_High;
nvic_disable_irq(NVIC_DMA1_CHANNEL1_IRQ);
dma_disable_transfer_error_interrupt(DMA1, DMA_CHANNEL1);
dma_disable_transfer_complete_interrupt(DMA1, DMA_CHANNEL1);
dma_enable_channel(DMA1, DMA_CHANNEL1); // DMA_Cmd(DMA1_Channel1, ENABLE);
}
void ADC_init(){
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); // enable clocking
rcc_periph_clock_enable(RCC_ADC1);
@@ -157,20 +182,7 @@ void ADC_init(){
// Make sure the ADC doesn't run during config
adc_off(ADC1);
// first configure DMA1 Channel1 (ADC1)
rcc_periph_clock_enable(RCC_DMA1); // RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
dma_channel_reset(DMA1, DMA_CHANNEL1); //DMA_DeInit(DMA1_Channel1);
dma_set_peripheral_address(DMA1, DMA_CHANNEL1, (uint32_t) &(ADC_DR(ADC1))); // DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
dma_set_memory_address(DMA1, DMA_CHANNEL1, (uint32_t) ADC_value); // DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADC_value;
dma_set_number_of_data(DMA1, DMA_CHANNEL1, ADC_CHANNELS_NUMBER); // DMA_InitStructure.DMA_BufferSize = 1;
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
dma_disable_peripheral_increment_mode(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
dma_set_peripheral_size(DMA1, DMA_CHANNEL1, DMA_CCR_PSIZE_16BIT); // DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
dma_set_memory_size(DMA1, DMA_CHANNEL1, DMA_CCR_MSIZE_16BIT); // DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
dma_enable_circular_mode(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
dma_set_priority(DMA1, DMA_CHANNEL1, DMA_CCR_PL_HIGH); // DMA_InitStructure.DMA_Priority = DMA_Priority_High;
dma_enable_channel(DMA1, DMA_CHANNEL1); // DMA_Cmd(DMA1_Channel1, ENABLE);
adc_dma_on();
// Configure ADC as continuous scan mode with DMA
adc_set_dual_mode(ADC_CR1_DUALMOD_IND); // ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
@@ -196,10 +208,52 @@ void ADC_calibrate_and_start(){
adc_start_conversion_direct(ADC1);
}
uint16_t tim2_buff[8] = {10,20,30,40,50,60,70,80};
uint16_t tim2_inbuff[8];
uint16_t tim2_buff[TIM2_DMABUFF_SIZE];
uint16_t tim2_inbuff[TIM2_DMABUFF_SIZE];
int tum2buff_ctr = 0;
/**
* this function sends bits of ow_byte (LSB first) to 1-wire line
* @param ow_byte - byte to convert
* @param Nbits - number of bits to send
* @param ini - 1 to zero counter
*/
uint8_t OW_add_byte(uint8_t ow_byte, uint8_t Nbits, uint8_t ini){
uint8_t i, byte;
if(ini) tum2buff_ctr = 0;
if(Nbits == 0) return 0;
if(Nbits > 8) Nbits = 8;
for(i = 0; i < Nbits; i++){
if(ow_byte & 0x01){
byte = OW_1;
}else{
byte = OW_0;
}
tim2_buff[tum2buff_ctr++] = byte;
if(tum2buff_ctr == TIM2_DMABUFF_SIZE) return 0; // avoid buffer overflow
ow_byte = ow_byte >> 1;
}
return 1;
}
void init_dmatimer(){ // tim2_ch4 - PA3, no remap
/**
* Fill output buffer with data from 1-wire
* @param start_idx - index from which to start (bit number)
* @param N - data length (in **bytes**)
* @outbuf - where to place data
*/
void read_from_OWbuf(uint8_t start_idx, uint8_t N, uint8_t *outbuf){
uint8_t i, j, last = start_idx + N * 8, byte;
if(last >= TIM2_DMABUFF_SIZE) last = TIM2_DMABUFF_SIZE;
for(i = start_idx; i < last;){
byte = 0;
for(j = 0; j < 8; j++, byte <<= 1){
if(tim2_inbuff[i++] > OW_READ1) byte |= 1;
}
*outbuf++ = byte;
}
}
void init_ow_dmatimer(){ // tim2_ch4 - PA3, no remap
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO3);
rcc_periph_clock_enable(RCC_TIM2);
@@ -210,14 +264,19 @@ void init_dmatimer(){ // tim2_ch4 - PA3, no remap
// 72MHz div 72 = 1MHz
timer_set_prescaler(TIM2, 71); // prescaler is (div - 1)
timer_continuous_mode(TIM2); // automatically reload
timer_enable_preload(TIM2); // force changing period
timer_set_period(TIM2, 86); // period is 87us
timer_disable_preload(TIM2); // force changing period
timer_set_period(TIM2, OW_BIT); // bit length
timer_enable_update_event(TIM2);
timer_set_oc_polarity_high(TIM2, TIM_OC4);
timer_set_oc_mode(TIM2, TIM_OC4, TIM_OCM_PWM1); // edge-aligned mode
timer_enable_oc_preload(TIM2, TIM_OC4);
timer_disable_oc_preload(TIM2, TIM_OC4);
timer_set_oc_value(TIM2, TIM_OC4, OW_RESET);
timer_enable_oc_output(TIM2, TIM_OC4);
timer_enable_irq(TIM2, TIM_DIER_UDE | TIM_DIER_CC4DE | TIM_DIER_CC3DE);
timer_set_oc_polarity_low(TIM2, TIM_OC4);
timer_disable_counter(TIM2);
timer_disable_irq(TIM2, TIM_DIER_UIE);
nvic_disable_irq(NVIC_TIM2_IRQ);
gpio_set(GPIOA, GPIO3);
// TIM2_CH4 - DMA1, channel 7
rcc_periph_clock_enable(RCC_DMA1);
@@ -238,13 +297,18 @@ void init_dmatimer(){ // tim2_ch4 - PA3, no remap
timer_ic_set_input(TIM2, TIM_IC3, TIM_IC_IN_TI4);
timer_set_oc_polarity_high(TIM2, TIM_OC3);
timer_ic_enable(TIM2, TIM_IC3);
timer_enable_oc_output(TIM2, TIM_OC3);
//timer_enable_oc_output(TIM2, TIM_OC3);
//gpio_set(GPIOA, GPIO3);
ow_reset();
}
// configure DMA1 Channel1 (ADC1)
/**
* reconfigure DMA1_1 for 1-wire
*/
void ow_dma_on(){
dma_channel_reset(DMA1, DMA_CHANNEL1);
dma_set_peripheral_address(DMA1, DMA_CHANNEL1, (uint32_t) &(TIM_CCR3(TIM2)));
dma_set_memory_address(DMA1, DMA_CHANNEL1, (uint32_t) tim2_inbuff);
dma_set_number_of_data(DMA1, DMA_CHANNEL1, 8);
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL1);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL1);
dma_disable_peripheral_increment_mode(DMA1, DMA_CHANNEL1);
@@ -256,39 +320,104 @@ void init_dmatimer(){ // tim2_ch4 - PA3, no remap
}
void run_dmatimer(){
int i;
//int i;
ow_done = 0;
ow_dma_on();
DMA1_IFCR = DMA_ISR_TEIF7|DMA_ISR_HTIF7|DMA_ISR_TCIF7|DMA_ISR_GIF7 |
DMA_ISR_TEIF1|DMA_ISR_HTIF1|DMA_ISR_TCIF1|DMA_ISR_GIF1; // clear flags
dma_set_number_of_data(DMA1, DMA_CHANNEL7, 8);
timer_set_dma_on_compare_event(TIM2);
timer_enable_oc_output(TIM2, TIM_OC4);
TIM_SR(TIM2) = 0;
timer_set_period(TIM2, OW_BIT); // bit length
dma_set_number_of_data(DMA1, DMA_CHANNEL7, tum2buff_ctr);
//timer_set_dma_on_compare_event(TIM2);
timer_set_dma_on_update_event(TIM2);
timer_ic_enable(TIM2, TIM_IC3);
dma_enable_channel(DMA1, DMA_CHANNEL7);
timer_enable_counter(TIM2);
for(i = 0; i < 8; i++) tim2_inbuff[i] = 0;
dma_set_number_of_data(DMA1, DMA_CHANNEL1, 8);
//for(i = 0; i < TIM2_DMABUFF_SIZE; i++) tim2_inbuff[i] = 0;
dma_set_number_of_data(DMA1, DMA_CHANNEL1, tum2buff_ctr);
dma_enable_channel(DMA1, DMA_CHANNEL1);
timer_enable_irq(TIM2, TIM_DIER_UDE | TIM_DIER_CC4DE | TIM_DIER_CC3DE);
TIM2_CCER |= TIM_CCER_CC4P | TIM_CCER_CC4E;
TIM2_CR1 |= TIM_CR1_CEN; // timer_enable_counter(TIM2);
}
void ow_reset(){
ow_done = 0;
timer_disable_counter(TIM2);
DMA1_IFCR = DMA_ISR_TEIF7|DMA_ISR_HTIF7|DMA_ISR_TCIF7|DMA_ISR_GIF7 |
DMA_ISR_TEIF1|DMA_ISR_HTIF1|DMA_ISR_TCIF1|DMA_ISR_GIF1; // clear flags
TIM_SR(TIM2) = 0;
timer_set_period(TIM2, OW_RESET*2); // reset length
timer_set_oc_value(TIM2, TIM_OC4, OW_RESET);
timer_ic_set_input(TIM2, TIM_IC3, TIM_IC_IN_TI4);
timer_set_oc_polarity_high(TIM2, TIM_OC3);
timer_ic_enable(TIM2, TIM_IC3);
// timer_enable_irq(TIM2, TIM_DIER_CC3DE);
timer_set_dma_on_update_event(TIM2); // wait until end of signal!
timer_enable_irq(TIM2, TIM_DIER_UIE | TIM_DIER_CC3IE);
nvic_enable_irq(NVIC_TIM2_IRQ);
//timer_generate_event(TIM2, TIM_SR_UIF);
/*
tim2_inbuff[0] = 0;
dma_set_number_of_data(DMA1, DMA_CHANNEL1, 6);
dma_enable_channel(DMA1, DMA_CHANNEL1); // enable only reading - for interrupt
*/
// NOT USE THIS: wery long
//timer_set_oc_polarity_low(TIM2, TIM_OC4);
//timer_enable_oc_output(TIM2, TIM_OC4);
TIM2_CCER |= TIM_CCER_CC4P | TIM_CCER_CC4E;
TIM2_CR1 |= TIM_CR1_CEN; // timer_enable_counter(TIM2);
}
uint16_t rstat = 0, lastcc3;
void tim2_isr(){
if(timer_get_flag(TIM2, TIM_SR_UIF)){
timer_clear_flag(TIM2, TIM_SR_UIF);
TIM2_CCER &= ~TIM_CCER_CC4P; //timer_set_oc_polarity_high(TIM2, TIM_OC4);
TIM2_CR1 &= ~TIM_CR1_CEN; // timer_disable_counter(TIM2);
gpio_set(GPIOA, GPIO3);
timer_disable_irq(TIM2, TIM_DIER_UIE | TIM_DIER_CC3IE);
nvic_disable_irq(NVIC_TIM2_IRQ);
ow_done = 1;
rstat = lastcc3;
print_int(rstat, lastsendfun);
MSG("\n");
}
if(timer_get_flag(TIM2, TIM_SR_CC3IF)){
timer_clear_flag(TIM2, TIM_SR_CC3IF);
lastcc3 = TIM_CCR3(TIM2);
}
}
void dma1_channel7_isr(){
if(DMA1_ISR & DMA_ISR_TCIF7) {
DMA1_IFCR = DMA_IFCR_CTCIF7;
dma_disable_channel(DMA1, DMA_CHANNEL7);
timer_disable_irq(TIM2, TIM_DIER_CC4DE);
}else if(DMA1_ISR & DMA_ISR_TEIF7){
DMA1_IFCR = DMA_IFCR_CTEIF7;
MSG("out transfer error\n");
}
}
uint8_t ow_done = 1;
void dma1_channel1_isr(){
int i;
if(DMA1_ISR & DMA_ISR_TCIF1) {
DMA1_IFCR = DMA_IFCR_CTCIF1;
dma_disable_channel(DMA1, DMA_CHANNEL1);
timer_disable_counter(TIM2);
TIM2_CCER &= ~TIM_CCER_CC4P; //timer_set_oc_polarity_high(TIM2, TIM_OC4);
TIM2_CR1 &= ~TIM_CR1_CEN; // timer_disable_counter(TIM2);
timer_disable_irq(TIM2, TIM_DIER_CC3DE);
gpio_set(GPIOA, GPIO3);
for(i = 0; i < 8; i++){
dma_disable_channel(DMA1, DMA_CHANNEL1);
nvic_disable_irq(NVIC_DMA1_CHANNEL1_IRQ);
ow_done = 1;
for(i = 0; i < tum2buff_ctr; i++){
print_int(tim2_inbuff[i], lastsendfun);
MSG(" ");
}
@@ -298,3 +427,9 @@ void dma1_channel1_isr(){
MSG("in transfer error\n");
}
}
uint8_t OW_get_reset_status(){
if(rstat < OW_PRESENT) return 0; // no devices
return 1;
}

22
with_opencm3/hardware_ini.h
View File

@@ -23,11 +23,18 @@
#ifndef __HARDWARE_INI_H__
#define __HARDWARE_INI_H__
#define TIM2_DMABUFF_SIZE 128
// 1-wire zero-state lengths (in us minus 1)
#define OW_1 (9)
#define OW_0 (69)
#define OW_READ1 (14)
#define OW_BIT (79)
#define OW_RESET (499)
#define OW_PRESENT (599)
extern volatile uint16_t ADC_value[]; // ADC DMA value
#define TRD_NO 8 // number of TRD devices
#define TRD_NO (8) // number of TRD devices
// bits used to address external SPI ADC - PD10..12
#define ADC_ADDR_MASK (GPIO10|GPIO11|GPIO12)
#define ADC_SET_ADDR(X) ((X << 10) & ADC_ADDR_MASK)
@@ -88,7 +95,14 @@ void ADC_calibrate_and_start();
#define OW_RX_PORT GPIO_BANK_USART2_RX
#define OW_RX_PIN GPIO_USART2_RX
void init_dmatimer();
void init_ow_dmatimer();
void run_dmatimer();
extern uint8_t ow_done;
#define OW_READY() (ow_done)
void ow_dma_on();
void adc_dma_on();
uint8_t OW_add_byte(uint8_t ow_byte, uint8_t Nbits, uint8_t ini);
void read_from_OWbuf(uint8_t start_idx, uint8_t N, uint8_t *outbuf);
void ow_reset();
uint8_t OW_get_reset_status();
#endif // __HARDWARE_INI_H__

BIN
with_opencm3/ircontroller.bin
View File

Binary file not shown.

9
with_opencm3/ld/devices.data Normal file
View File

@@ -0,0 +1,9 @@
stm32f103?4* stm32f1 ROM=16K RAM=6K
stm32f103?6* stm32f1 ROM=32K RAM=10K
stm32f103?8* stm32f1 ROM=64K RAM=20K
stm32f103?b* stm32f1 ROM=128K RAM=20K
stm32f103?c* stm32f1 ROM=256K RAM=48K
stm32f103?d* stm32f1 ROM=384K RAM=64K
stm32f103?e* stm32f1 ROM=512K RAM=64K
stm32f103?f* stm32f1 ROM=768K RAM=96K
stm32f103?g* stm32f1 ROM=1024K RAM=96K

31
with_opencm3/ld/stm32f103x4.ld Normal file
View File

@@ -0,0 +1,31 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
/* Define memory regions. */
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 16K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K
}
/* Include the common ld script. */
INCLUDE libopencm3_stm32f1.ld

31
with_opencm3/ld/stm32f103x6.ld Normal file
View File

@@ -0,0 +1,31 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
/* Define memory regions. */
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 10K
}
/* Include the common ld script. */
INCLUDE libopencm3_stm32f1.ld

31
with_opencm3/ld/stm32f103x8.ld Normal file
View File

@@ -0,0 +1,31 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
/* Define memory regions. */
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
}
/* Include the common ld script. */
INCLUDE libopencm3_stm32f1.ld

4
with_opencm3/stm32-h103.ld → with_opencm3/ld/stm32f103xB.ld
View File

@@ -1,7 +1,7 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -17,7 +17,7 @@
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* Linker script for Olimex STM32-H103 (STM32F103RBT6, 128K flash, 20K RAM). */
/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
/* Define memory regions. */
MEMORY

31
with_opencm3/ld/stm32f103xC.ld Normal file
View File

@@ -0,0 +1,31 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
/* Define memory regions. */
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K
}
/* Include the common ld script. */
INCLUDE libopencm3_stm32f1.ld

31
with_opencm3/ld/stm32f103xD.ld Normal file
View File

@@ -0,0 +1,31 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
/* Define memory regions. */
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 384K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
}
/* Include the common ld script. */
INCLUDE libopencm3_stm32f1.ld

31
with_opencm3/ld/stm32f103xE.ld Normal file
View File

@@ -0,0 +1,31 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
/* Define memory regions. */
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
}
/* Include the common ld script. */
INCLUDE libopencm3_stm32f1.ld

31
with_opencm3/ld/stm32f103xF.ld Normal file
View File

@@ -0,0 +1,31 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
/* Define memory regions. */
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 768K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
}
/* Include the common ld script. */
INCLUDE libopencm3_stm32f1.ld

31
with_opencm3/ld/stm32f103xG.ld Normal file
View File

@@ -0,0 +1,31 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/* Linker script for STM32F100x4, 16K flash, 4K RAM. */
/* Define memory regions. */
MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
}
/* Include the common ld script. */
INCLUDE libopencm3_stm32f1.ld

13
with_opencm3/main.c
View File

@@ -157,7 +157,7 @@ int main(){
usbd_dev = USB_init();
// init ADC
// ADC_init();
ADC_init();
// SysTick is a system timer with 1mc period
SysTick_init();
@@ -168,15 +168,14 @@ int main(){
switch_SPI(SPI1); // init SPI1
SPI_init();
//OW_Init();
init_ow_dmatimer();
// wait a little and then turn on USB pullup
for (i = 0; i < 0x800000; i++)
__asm__("nop");
usb_connect(); // turn on USB
//ADC_calibrate_and_start();
init_dmatimer();
ADC_calibrate_and_start();
while(1){
usbd_poll(usbd_dev);
if(usbdatalen){ // there's something in USB buffer
@@ -190,9 +189,15 @@ init_dmatimer();
read_next_TRD();
}
}
OW_process(); // process 1-wire commands
if(OW_DATA_READY()){
OW_CLEAR_READY_FLAG();
MSG("Ready!\n");
}
process_stepper_motors(); // check flags of motors' timers
if(Timer - Old_timer > 999){ // one-second cycle
Old_timer += 1000;
//OW_fill_ID(0);
//gpio_toggle(GPIOC, GPIO12); // toggle LED
//gpio_toggle(GPIO_BANK_SPI2_MOSI, GPIO_SPI2_MOSI);
//gpio_toggle(GPIO_BANK_SPI2_SCK, GPIO_SPI2_SCK);

169
with_opencm3/onewire.c
View File

@@ -18,36 +18,121 @@
*/
#include "onewire.h"
#define OW_0 0x00
#define OW_1 0xff
#define OW_R 0xff
#define OW_RST 0xf0
OW_ID id_array[OW_MAX_NUM]; // 1-wire devices ID buffer (not more than eight)
uint8_t dev_amount = 0; // amount of 1-wire devices
uint8_t ID_buf[64] = {0}; // 1-wire devices ID buffer (8 bytes for every device)
uint8_t NUM_buf[8] = {0}; // numerical identificators for each sensor
// states of 1-wire processing queue
typedef enum{
OW_OFF_STATE, // not working
OW_RESET_STATE, // reset bus
OW_SEND_STATE, // send data
OW_READ_STATE, // wait for reading
} OW_States;
OW_States OW_State = OW_OFF_STATE; // 1-wire state, 0-not runned
uint8_t OW_wait_bytes = 0; // amount of bytes needed to read
uint8_t OW_start_idx = 0; // starting index to read from 1-wire buffer
uint8_t *read_buf = NULL; // buffer to read
uint8_t ow_data_ready = 0; // flag of reading OK
/**
* this function sends bits of ow_byte (LSB first) to 1-wire line
* @param ow_byte - byte to convert
* @param Nbits - number of bits to send
* fill buffer with zeros - read slots
* @param N - amount of bytes to read
*/
void OW_SendBits(uint8_t ow_byte, uint8_t Nbits){
uint8_t i, byte;
if(Nbits == 0) return;
if(Nbits > 8) Nbits = 8;
for(i = 0; i < Nbits; i++){
if(ow_byte & 0x01){
byte = OW_1;
}else{
byte = OW_0;
}
fill_uart_buff(OW_USART_X, byte); // send next "bit"
ow_byte = ow_byte >> 1;
uint8_t OW_Read(uint8_t N){
uint8_t i;
for(i = 0; i < N; i++)
if(!OW_add_byte(0, 8, 0))
return 0;
return 1;
}
uint8_t ow_was_reseting = 0;
void OW_process(){
switch(OW_State){
case OW_OFF_STATE:
return;
break;
case OW_RESET_STATE:
OW_State = OW_SEND_STATE;
ow_was_reseting = 1;
ow_reset();
MSG("reset\n");
break;
case OW_SEND_STATE:
if(!OW_READY()) return; // reset in work
if(ow_was_reseting){
if(!OW_get_reset_status()){
MSG("error: no devices found\n");
ow_was_reseting = 0;
OW_State = OW_OFF_STATE;
return;
}
}
ow_was_reseting = 0;
OW_State = OW_READ_STATE;
run_dmatimer(); // turn on data transfer
MSG("send\n");
break;
case OW_READ_STATE:
if(!OW_READY()) return; // data isn't ready
OW_State = OW_OFF_STATE;
adc_dma_on(); // return DMA1_1 to ADC at end of data transmitting
if(read_buf){
read_from_OWbuf(OW_start_idx, OW_wait_bytes, read_buf);
}
ow_data_ready = 1;
MSG("read\n");
break;
}
}
/**
* fill Nth array with identificators
*/
void OW_fill_ID(uint8_t N){
if(N >= OW_MAX_NUM){
MSG("number too big\n");
return;
}
OW_Send(1, (uint8_t*)"\xcc\x33", 2);
OW_Read(8); // wait for 8 bytes
read_buf = id_array[N].bytes;
OW_wait_bytes = 8;
OW_start_idx = 16;
}
/**
* Procedure of 1-wire communications
* variables:
* @param sendReset - send RESET before transmission
* @param command - bytes sent to the bus (if we want to read, send OW_READ_SLOT)
* @param cLen - command buffer length (how many bytes to send)
* @return 1 if succeed, 0 if failure
*/
uint8_t OW_Send(uint8_t sendReset, uint8_t *command, uint8_t cLen){
uint8_t f = 1;
ow_dma_on(); // reconfigure DMA1
ow_data_ready = 0;
// if reset needed - send RESET and check bus
if(sendReset)
OW_State = OW_RESET_STATE;
else
OW_State = OW_SEND_STATE;
while(cLen-- > 0){
if(!OW_add_byte(*command, 8, f)) return 0;
command++;
f = 0;
}
return 1;
}
#if 0
void OW_ClearBuff(){
UART_buff *curbuff = get_uart_buffer(OW_USART_X);
curbuff->end = 0;
@@ -74,19 +159,7 @@ newline(lastsendfun);
}
/*
* Configure peripherial ports (USART2) for 1-wire
*/
void OW_Init(){
struct usb_cdc_line_coding owlc = {
.dwDTERate = 115200,
.bCharFormat = USB_CDC_1_STOP_BITS,
.bParityType = USB_CDC_NO_PARITY,
.bDataBits = 8,
};
UART_init(OW_USART_X);
UART_setspeed(OW_USART_X, &owlc);
}
/*
* 1-wire reset
@@ -120,27 +193,7 @@ uint8_t OW_Reset(){
return 0;
}
/**
* Procedure of 1-wire communications
* variables:
* @param sendReset - send RESET before transmission
* @param command - bytes sent to the bus (if we want to read, send OW_READ_SLOT)
* @param cLen - command buffer length (how many bytes to send)
* @return 1 if succeed, 0 if failure
*/
uint8_t OW_Send(uint8_t sendReset, uint8_t *command, uint8_t cLen){
// if reset needed - send RESET and check bus
if(sendReset){
if(OW_Reset() == 0){
return 0;
}
}
while(cLen-- > 0){
OW_SendBits(*command, 8);
command++;
}
return 1;
}
/**
* Check USART IN buffer for ready & fill user buffer with data on success
@@ -257,3 +310,5 @@ void OW_getTemp(){
}
}
*/
#endif

21
with_opencm3/onewire.h
View File

@@ -33,8 +33,24 @@
#define OW_READ_SLOT (uint8_t*)"0xff"
void OW_Init();
typedef struct{
uint8_t bytes[8];
} OW_ID;
#define OW_MAX_NUM 8
extern uint8_t ow_data_ready;
#define OW_DATA_READY() (ow_data_ready)
#define OW_CLEAR_READY_FLAG() do{ow_data_ready = 0;}while(0)
void OW_process();
void OW_fill_ID(uint8_t N);
uint8_t OW_Send(uint8_t sendReset, uint8_t *command, uint8_t cLen);
#if 0
uint8_t OW_Get(uint8_t buflen, uint8_t *data, uint8_t readStart);
uint8_t OW_Scan(uint8_t *buf, uint8_t num);
@@ -49,6 +65,9 @@ uint8_t OW_Scan(uint8_t *buf, uint8_t num);
void OW_getTemp();
#endif
/*
* thermometer identificator is: 8bits CRC, 48bits serial, 8bits device code (10h)
* Critical temperatures is T_H and T_L

7
with_opencm3/user_proto.c
View File

@@ -64,7 +64,6 @@ void print_ad_vals(sendfun s){
void parce_incoming_buf(char *buf, int len, sendfun s){
uint8_t command;
uint8_t onewire_addr[8];
int i = 0, j, m;
lastsendfun = s;
if(Uval_ready == UVAL_START){ // we are in process of user's value reading
@@ -87,7 +86,7 @@ void parce_incoming_buf(char *buf, int len, sendfun s){
READINT();
}else switch (command){
case 'P':
run_dmatimer();
OW_fill_ID(0);
break;
case 'x': // set period of TIM1 (motors 1..3)
active_motor = 1;
@@ -103,14 +102,14 @@ void parce_incoming_buf(char *buf, int len, sendfun s){
for(m = 0; m < 5; m++)
stop_motor(m);
break;
case 'W': // scan for one 1-wire device
/* case 'W': // scan for one 1-wire device
if(1 == OW_Scan(onewire_addr, 1)){
P("found 1-wire: ", s);
print_hex(onewire_addr, 8, s);
}else
P("1-wire error",s );
P("\r\n", s);
break;
break;*/
case 'S': // single conversion
doubleconv = 0;
break;