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103
with_opencm3/STM32_PINS
Normal file
103
with_opencm3/STM32_PINS
Normal file
@ -0,0 +1,103 @@
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Functional map of MCU pins
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# name functionality
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001 PE2 DIR_3 direction of steppers' rotation
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002 PE3 DIR_4
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003 PE4 DIR_5
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004 PE5 POW3 Turn ON/OFF power switch POW_LOAD
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005 PE6 DG_FEEDBACK feedback from power switch POW_LOAD (+10..12V)
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006 VBAT -
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007 PC13 -
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008 PC14 -
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009 PC15 -
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010 VSS GND
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011 VDD +3.3V
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012 OSC_IN 8MHz in
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013 OSC_OUT 8MHz out
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014 NRST Reset
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015 PC0 SHTR Shutter on pulse
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016 PC1 SHTR_FB Error signal from shutter H-bridge
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017 PC2 POW0 Shutter polarity (open/close)
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018 PC3 -
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019 VSSA 0v analog
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020 VREF- ref (0v)
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021 VREF+ ref (+3.3v)
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022 VDDA +3.3V analog
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023 PA0 U10_ADC 10..12V voltage control
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024 PA1 U36_ADC 36V voltage control
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025 PA2 1WIRE_TX 1-wire interface
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026 PA3 1WIRE_RX
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027 VSS GND
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028 VDD +3.3V
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029 PA4 ADC7\
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030 PA5 ADC6 |
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031 PA6 ADC5 |
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032 PA7 ADC4 | ADC 12bit input channels (TRD)
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033 PC4 ADC3 |
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034 PC5 ADC2 |
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035 PB0 ADC1 |
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036 PB1 ADC0/
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037 BOOT1 BOOT 100k resistor to GND
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038 PE7 EN1 \
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039 PE8 EN2 |
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040 PE9 EN3 | enable Xth stepper motor
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041 PE10 EN4 |
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042 PE11 EN5 /
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043 PE12 POW2\
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044 PE13 POW1/ Power load (10..12V, pull-down)
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045 PE14 -
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046 PE15 -
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047 PB10 USART3_TX RS-232 (master)
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048 PB11 USART3_RX
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049 VSS GND
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050 VDD +3.3V
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051 PB12 -
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052 SPI2_SCK \
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053 SPI2_MISO | External SPI connection (at edge of the board)
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054 SPI2_MOSI /
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055 PD8 -
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056 PD9 -
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057 PD10 EXT0\
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058 PD11 EXT1 | ADG506 address selection
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059 PD12 EXT2 | or custom external ports
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060 PD13 EXT3/
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061 PD14 -
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062 PD15 TIM2 timer for motors 4&5
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063 PC6 TIM1 timer for stepper motors 1..3
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064 PC7 \ LS1 Linear stage 1 (long) DOWN end-switch
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065 PC8 / Linear stage 1 (long) UP end-switch
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066 PC9 \ LS2 Linear stage 2 (short) DOWN end-switch
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067 PA8 / Linear stage 2 (short) UP end-switch
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068 PA9 BOOT_TX \ UART1 (slave): boot + ext UART
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069 PA10 BOOT_RX /
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070 PA11 USB_DM USB data-
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071 PA12 USB_DP USB data+
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072 PA13 -
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073 NC -
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074 VSS GND
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075 VDD +3.3V
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076 PA14 -
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077 PA15 -
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078 PC10 USB_POWER +3V when USB connected
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079 PC11 USB_DISC software USB disconnection (low lewel for n-channel VT1, high level for pnp bipolar or p-channel MOSFET)
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080 PC12 -
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081 PD0 \
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082 PD1 | Tur1 Slits turret Hall sensors
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083 PD2 |
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084 PD3 /
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085 PD4 \
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086 PD5 | Tur2 Middle filters turret Hall sensors
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087 PD6 /
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088 PD7 Tur3_0 Upper filters turret Hall 0
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089 SPI1_SCK \
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090 SPI1_MISO | SPI connection (near USB connector)
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091 SPI1_MOSI/I2C_SMBAI/
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092 PB6 Tur3_1 \ Upper filters turret Hall 1,2
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093 PB7 Tur3_2 /
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094 BOOT BOOT Button to boot from bootloader
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095 I2C_SCL/CANRX \ External CAN connection (or I2S, etc)
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096 I2C_SDA/CANTX /
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097 PE0 DIR_1 direction of SM 1,2
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098 PE1 DIR_2
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099 VSS GND
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100 VDD +3.3V
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419
with_opencm3/hardware_ini.c.worked
Normal file
419
with_opencm3/hardware_ini.c.worked
Normal file
@ -0,0 +1,419 @@
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/*
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* hardware_ini.c - functions for HW initialisation
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*
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* Copyright 2014 Edward V. Emelianov <eddy@sao.ru, edward.emelianoff@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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/*
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* All hardware-dependent initialisation & definition should be placed here
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* and in hardware_ini.h
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*
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*/
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#include "main.h"
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#include "hardware_ini.h"
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#include "onewire.h"
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volatile uint16_t ADC_value[8]; // ADC DMA value
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/*
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* Configure SPI ports
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*/
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/*
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* SPI1 remapped:
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* SCK - PB3
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* MISO - PB4
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* MOSI - PB5
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*/
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void SPI1_init(){
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// enable AFIO & other clocking
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rcc_peripheral_enable_clock(&RCC_APB2ENR,
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RCC_APB2ENR_SPI1EN | RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPBEN);
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// remap SPI1 (change pins from PA5..7 to PB3..5); also turn off JTAG
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gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF, AFIO_MAPR_SPI1_REMAP);
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// SCK, MOSI - push-pull output
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gpio_set_mode(GPIO_BANK_SPI1_RE_SCK, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_RE_SCK);
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gpio_set_mode(GPIO_BANK_SPI1_RE_MOSI, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_RE_MOSI);
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// MISO - opendrain in
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gpio_set_mode(GPIO_BANK_SPI1_RE_MISO, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_SPI1_RE_MISO);
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spi_reset(SPI1);
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/* Set up SPI in Master mode with:
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* Clock baud rate: 1/128 of peripheral clock frequency (APB2, 72MHz)
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* Clock polarity: Idle High
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* Clock phase: Data valid on 2nd clock pulse
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* Data frame format: 8-bit
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* Frame format: MSB First
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*/
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spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_128, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
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SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
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nvic_enable_irq(NVIC_SPI1_IRQ); // enable SPI interrupt
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}
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/*
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* SPI2:
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* SCK - PB13
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* MISO - PB14
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* MOSI - PB15
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*/
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void SPI2_init(){
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// turn on clocking
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//rcc_periph_clock_enable(RCC_SPI2 | RCC_GPIOB);
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rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN);
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rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPBEN);
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// SCK, MOSI - push-pull output
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gpio_set_mode(GPIO_BANK_SPI2_SCK, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI2_SCK);
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gpio_set_mode(GPIO_BANK_SPI2_MOSI, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI2_MOSI);
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// MISO - opendrain in
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gpio_set_mode(GPIO_BANK_SPI2_MISO, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_SPI2_MISO);
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spi_reset(SPI2);
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/* Set up SPI in Master mode with:
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* Clock baud rate: 1/64 of peripheral clock frequency (APB1, 36MHz)
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* Clock polarity: Idle High
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* Clock phase: Data valid on 2nd clock pulse
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* Data frame format: 8-bit
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* Frame format: MSB First
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*/
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spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
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SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
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nvic_enable_irq(NVIC_SPI2_IRQ); // enable SPI interrupt
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}
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/**
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* GPIO initialisaion: clocking + pins setup
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*/
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void GPIO_init(){
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/* rcc_periph_clock_enable(RCC_AFIO);
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rcc_periph_clock_enable(RCC_SPI1);
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rcc_periph_clock_enable(RCC_GPIOC);*/
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rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN |
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RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN |
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RCC_APB2ENR_IOPEEN);
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// USB_DISC: push-pull
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gpio_set_mode(USB_DISC_PORT, GPIO_MODE_OUTPUT_2_MHZ,
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GPIO_CNF_OUTPUT_PUSHPULL, USB_DISC_PIN);
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// USB_POWER: open drain, externall pull down with R7 (22k)
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gpio_set_mode(USB_POWER_PORT, GPIO_MODE_INPUT,
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GPIO_CNF_INPUT_FLOAT, USB_POWER_PIN);
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// AD7794 addr + en
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gpio_set_mode(ADC_ADDR_PORT, GPIO_MODE_OUTPUT_2_MHZ,
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GPIO_CNF_OUTPUT_PUSHPULL, ADC_ADDR_MASK | ADC_EN_PIN); // ADDRESS: PD10..12; EN: PD13
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gpio_clear(ADC_ADDR_PORT, ADC_ADDR_MASK | ADC_EN_PIN); // clear address & turn switch off
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}
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/*
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* SysTick used for system timer with period of 1ms
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*/
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void SysTick_init(){
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systick_set_clocksource(STK_CSR_CLKSOURCE_AHB_DIV8); // Systyck: 72/8=9MHz
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systick_set_reload(8999); // 9000 pulses: 1kHz
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systick_interrupt_enable();
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systick_counter_enable();
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}
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/*
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* Due to inconvenient pins position on STM32F103VxT6 I had to make this strange location:
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* my channel # -> ADC1/2 channel #
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* 0 -> 9 PB1
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* 1 -> 8 PB0
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* 2 -> 15 PC5
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* 3 -> 14 PC4
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* 4 -> 7 PA7
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* 5 -> 6 PA6
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* 6 -> 5 PA5
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* 7 -> 4 PA4
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*/
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uint8_t adc_channel_array[16] = {9,8,15,14,7,6,5,4};
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#define ADC_CHANNELS_NUMBER 8
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/**
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* Turn on ADC DMA for filling temperatures buffer
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*/
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void adc_dma_on(){
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// first configure DMA1 Channel1 (ADC1)
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dma_channel_reset(DMA1, DMA_CHANNEL1); //DMA_DeInit(DMA1_Channel1);
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dma_set_peripheral_address(DMA1, DMA_CHANNEL1, (uint32_t) &(ADC_DR(ADC1))); // DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
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dma_set_memory_address(DMA1, DMA_CHANNEL1, (uint32_t) ADC_value); // DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&ADC_value;
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dma_set_number_of_data(DMA1, DMA_CHANNEL1, ADC_CHANNELS_NUMBER); // DMA_InitStructure.DMA_BufferSize = 1;
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dma_set_read_from_peripheral(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
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dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
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dma_disable_peripheral_increment_mode(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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dma_set_peripheral_size(DMA1, DMA_CHANNEL1, DMA_CCR_PSIZE_16BIT); // DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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dma_set_memory_size(DMA1, DMA_CHANNEL1, DMA_CCR_MSIZE_16BIT); // DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
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dma_enable_circular_mode(DMA1, DMA_CHANNEL1); // DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
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dma_set_priority(DMA1, DMA_CHANNEL1, DMA_CCR_PL_HIGH); // DMA_InitStructure.DMA_Priority = DMA_Priority_High;
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nvic_disable_irq(NVIC_DMA1_CHANNEL1_IRQ);
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dma_disable_transfer_error_interrupt(DMA1, DMA_CHANNEL1);
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dma_disable_transfer_complete_interrupt(DMA1, DMA_CHANNEL1);
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dma_enable_channel(DMA1, DMA_CHANNEL1); // DMA_Cmd(DMA1_Channel1, ENABLE);
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}
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void ADC_init(){
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rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); // enable clocking
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rcc_periph_clock_enable(RCC_ADC1);
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV4);
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rcc_periph_clock_enable(RCC_GPIOA | RCC_GPIOB | RCC_GPIOC); // clocking for ADC ports
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// channels 4-7: PA7-PA4
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gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO4|GPIO5|GPIO6|GPIO7);
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// channels 0,1: PB1, PB0
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gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO0|GPIO1);
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// channels 2,3: PC5, PC4
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gpio_set_mode(GPIOC, GPIO_MODE_INPUT, GPIO_CNF_INPUT_ANALOG, GPIO4|GPIO5);
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// Make sure the ADC doesn't run during config
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adc_off(ADC1);
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rcc_periph_clock_enable(RCC_DMA1);
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adc_dma_on();
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// Configure ADC as continuous scan mode with DMA
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adc_set_dual_mode(ADC_CR1_DUALMOD_IND); // ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
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adc_enable_scan_mode(ADC1); // ADC_InitStructure.ADC_ScanConvMode = ENABLE;
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adc_set_continuous_conversion_mode(ADC1); // ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
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adc_disable_external_trigger_regular(ADC1); // ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
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adc_set_right_aligned(ADC1); // ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
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adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_239DOT5CYC); // ADC_SampleTime_239Cycles5
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|
//adc_set_sample_time(ADC1, ADC_CHANNEL8, ADC_SMPR_SMP_239DOT5CYC); // ADC_RegularChannelConfig(ADC1, ADC_Channel_8, 1, ADC_SampleTime_239Cycles5);
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adc_enable_dma(ADC1); // ADC_DMACmd(ADC1, ENABLE);
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adc_power_on(ADC1); // ADC_Cmd(ADC1, ENABLE);
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|
}
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|
||||||
|
/**
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* Starts ADC calibration & after it runs ADC in continuous conversion mode
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||||||
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* First call ADC_init(), than wait a little and call this function
|
||||||
|
*/
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||||||
|
void ADC_calibrate_and_start(){
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adc_set_regular_sequence(ADC1, ADC_CHANNELS_NUMBER, adc_channel_array);
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|
adc_reset_calibration(ADC1);
|
||||||
|
adc_calibration(ADC1);
|
||||||
|
adc_start_conversion_regular(ADC1); // ADC_SoftwareStartConvCmd(ADC1, ENABLE);
|
||||||
|
adc_start_conversion_direct(ADC1);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
uint16_t tim2_buff[TIM2_DMABUFF_SIZE];
|
||||||
|
uint16_t tim2_inbuff[TIM2_DMABUFF_SIZE];
|
||||||
|
int tum2buff_ctr = 0;
|
||||||
|
uint8_t ow_done = 1;
|
||||||
|
/**
|
||||||
|
* this function sends bits of ow_byte (LSB first) to 1-wire line
|
||||||
|
* @param ow_byte - byte to convert
|
||||||
|
* @param Nbits - number of bits to send
|
||||||
|
* @param ini - 1 to zero counter
|
||||||
|
*/
|
||||||
|
uint8_t OW_add_byte(_U_ uint8_t ow_byte, _U_ uint8_t Nbits, _U_ uint8_t ini){
|
||||||
|
uint8_t i, byte;
|
||||||
|
if(ini) tum2buff_ctr = 0;
|
||||||
|
if(Nbits == 0) return 0;
|
||||||
|
if(Nbits > 8) Nbits = 8;
|
||||||
|
for(i = 0; i < Nbits; i++){
|
||||||
|
if(ow_byte & 0x01){
|
||||||
|
byte = OW_1;
|
||||||
|
}else{
|
||||||
|
byte = OW_0;
|
||||||
|
}
|
||||||
|
tim2_buff[tum2buff_ctr++] = byte;
|
||||||
|
if(tum2buff_ctr == TIM2_DMABUFF_SIZE) return 0; // avoid buffer overflow
|
||||||
|
ow_byte = ow_byte >> 1;
|
||||||
|
}
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Fill output buffer with data from 1-wire
|
||||||
|
* @param start_idx - index from which to start (bit number)
|
||||||
|
* @param N - data length (in **bytes**)
|
||||||
|
* @outbuf - where to place data
|
||||||
|
*/
|
||||||
|
void read_from_OWbuf(_U_ uint8_t start_idx, _U_ uint8_t N, _U_ uint8_t *outbuf){
|
||||||
|
uint8_t i, j, last = start_idx + N * 8, byte;
|
||||||
|
if(last >= TIM2_DMABUFF_SIZE) last = TIM2_DMABUFF_SIZE;
|
||||||
|
for(i = start_idx; i < last;){
|
||||||
|
byte = 0;
|
||||||
|
for(j = 0; j < 8; j++){
|
||||||
|
byte >>= 1;
|
||||||
|
if(tim2_inbuff[i++] < OW_READ1)
|
||||||
|
byte |= 0x80;
|
||||||
|
}
|
||||||
|
*outbuf++ = byte;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
// there's a mistake in opencm3, so redefine this if needed (TIM_CCMR2_CC3S_IN_TI1 -> TIM_CCMR2_CC3S_IN_TI4)
|
||||||
|
#ifndef TIM_CCMR2_CC3S_IN_TI4
|
||||||
|
#define TIM_CCMR2_CC3S_IN_TI4 (2)
|
||||||
|
#endif
|
||||||
|
void init_ow_dmatimer(){ // tim2_ch4 - PA3, no remap
|
||||||
|
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
|
||||||
|
GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN, GPIO3);
|
||||||
|
rcc_periph_clock_enable(RCC_TIM2);
|
||||||
|
rcc_periph_clock_enable(RCC_DMA1);
|
||||||
|
timer_reset(TIM2);
|
||||||
|
// timers have frequency of 1MHz -- 1us for one step
|
||||||
|
// 36MHz of APB1
|
||||||
|
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
|
||||||
|
// 72MHz div 72 = 1MHz
|
||||||
|
TIM2_PSC = 71; // prescaler is (div - 1)
|
||||||
|
TIM2_CR1 &= ~(TIM_CR1_OPM | TIM_CR1_UDIS); // continuous mode & enable update events
|
||||||
|
TIM2_CR1 |= TIM_CR1_ARPE; // changing period immediately
|
||||||
|
TIM2_ARR = OW_BIT; // default period of timer
|
||||||
|
// PWM_OUT: TIM2_CH4; capture: TIM2_CH3
|
||||||
|
// PWM edge-aligned mode & enable preload for CCR4, CC3 takes input from TI4
|
||||||
|
TIM2_CCMR2 = TIM_CCMR2_OC4M_PWM1 | TIM_CCMR2_OC4PE | TIM_CCMR2_CC3S_IN_TI4;
|
||||||
|
TIM2_CCR4 = 0; // set output value to 1 by clearing CCR4
|
||||||
|
TIM2_EGR = TIM_EGR_UG; // update values of ARR & CCR4
|
||||||
|
// set low polarity for CC4, high for CC4 & enable CC4 out and CC3 in
|
||||||
|
TIM2_CCER = TIM_CCER_CC4P | TIM_CCER_CC4E | TIM_CCER_CC3E;
|
||||||
|
}
|
||||||
|
|
||||||
|
void run_dmatimer(){
|
||||||
|
ow_done = 0;
|
||||||
|
DMA1_IFCR = DMA_ISR_TEIF7|DMA_ISR_HTIF7|DMA_ISR_TCIF7|DMA_ISR_GIF7 |
|
||||||
|
DMA_ISR_TEIF1|DMA_ISR_HTIF1|DMA_ISR_TCIF1|DMA_ISR_GIF1; // clear flags
|
||||||
|
|
||||||
|
init_ow_dmatimer();
|
||||||
|
|
||||||
|
// TIM2_CH4 - DMA1, channel 7
|
||||||
|
dma_channel_reset(DMA1, DMA_CHANNEL7);
|
||||||
|
dma_set_peripheral_address(DMA1, DMA_CHANNEL7, (uint32_t) &(TIM_CCR4(TIM2)));
|
||||||
|
dma_set_read_from_memory(DMA1, DMA_CHANNEL7);
|
||||||
|
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL7);
|
||||||
|
dma_disable_peripheral_increment_mode(DMA1, DMA_CHANNEL7);
|
||||||
|
dma_set_peripheral_size(DMA1, DMA_CHANNEL7, DMA_CCR_PSIZE_16BIT);
|
||||||
|
dma_set_memory_size(DMA1, DMA_CHANNEL7, DMA_CCR_MSIZE_16BIT);
|
||||||
|
dma_enable_transfer_error_interrupt(DMA1, DMA_CHANNEL7);
|
||||||
|
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL7);
|
||||||
|
dma_set_memory_address(DMA1, DMA_CHANNEL7, (uint32_t)tim2_buff);
|
||||||
|
// TIM2_CH4 - DMA1, channel 7
|
||||||
|
dma_channel_reset(DMA1, DMA_CHANNEL1);
|
||||||
|
dma_set_peripheral_address(DMA1, DMA_CHANNEL1, (uint32_t) &(TIM_CCR3(TIM2)));
|
||||||
|
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL1);
|
||||||
|
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL1);
|
||||||
|
dma_disable_peripheral_increment_mode(DMA1, DMA_CHANNEL1);
|
||||||
|
dma_set_peripheral_size(DMA1, DMA_CHANNEL1, DMA_CCR_PSIZE_16BIT);
|
||||||
|
dma_set_memory_size(DMA1, DMA_CHANNEL1, DMA_CCR_MSIZE_16BIT);
|
||||||
|
dma_enable_transfer_error_interrupt(DMA1, DMA_CHANNEL1);
|
||||||
|
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL1);
|
||||||
|
nvic_enable_irq(NVIC_DMA1_CHANNEL1_IRQ);
|
||||||
|
nvic_enable_irq(NVIC_DMA1_CHANNEL7_IRQ); // enable dma1_channel7_isr
|
||||||
|
|
||||||
|
TIM2_SR = 0; // clear all flags
|
||||||
|
TIM2_CR1 &= ~TIM_CR1_OPM; // continuous mode
|
||||||
|
timer_set_period(TIM2, OW_BIT); // bit length
|
||||||
|
timer_generate_event(TIM2, TIM_EGR_UG); // update values
|
||||||
|
dma_set_memory_address(DMA1, DMA_CHANNEL7, (uint32_t)tim2_buff);
|
||||||
|
dma_set_number_of_data(DMA1, DMA_CHANNEL7, tum2buff_ctr);
|
||||||
|
|
||||||
|
//for(i = 0; i < TIM2_DMABUFF_SIZE; i++) tim2_inbuff[i] = 0;
|
||||||
|
dma_set_memory_address(DMA1, DMA_CHANNEL1, (uint32_t) tim2_inbuff);
|
||||||
|
dma_set_number_of_data(DMA1, DMA_CHANNEL1, tum2buff_ctr);
|
||||||
|
|
||||||
|
dma_enable_channel(DMA1, DMA_CHANNEL7);
|
||||||
|
dma_enable_channel(DMA1, DMA_CHANNEL1);
|
||||||
|
|
||||||
|
timer_set_dma_on_compare_event(TIM2);
|
||||||
|
TIM2_CCER |= TIM_CCER_CC3E; // enable input capture
|
||||||
|
TIM2_DIER = TIM_DIER_CC4DE | TIM_DIER_CC3DE; // enable DMA events
|
||||||
|
// set low polarity, enable cc out & enable input capture
|
||||||
|
TIM2_CCER |= TIM_CCER_CC4P | TIM_CCER_CC4E | TIM_CCER_CC3E;
|
||||||
|
TIM2_CR1 |= TIM_CR1_CEN; // run timer
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
uint16_t rstat = 0, lastcc3;
|
||||||
|
void ow_reset(){
|
||||||
|
ow_done = 0;
|
||||||
|
rstat = 0;
|
||||||
|
TIM2_SR = 0; // clear all flags
|
||||||
|
TIM2_DIER = 0; // disable timer interrupts
|
||||||
|
TIM2_ARR = OW_RESET_TIME; // set period to 1ms
|
||||||
|
TIM2_CCR4 = OW_RESET; // zero pulse length
|
||||||
|
TIM2_EGR = TIM_EGR_UG; // update values of ARR & CCR4
|
||||||
|
TIM2_CR1 |= TIM_CR1_OPM | TIM_CR1_CEN; // we need only single pulse & run timer
|
||||||
|
TIM2_SR = 0; // clear update flag generated after timer's running
|
||||||
|
TIM2_DIER = TIM_DIER_UIE | TIM_DIER_CC3IE; // generate interrupts on update event & cc
|
||||||
|
nvic_enable_irq(NVIC_TIM2_IRQ);
|
||||||
|
}
|
||||||
|
|
||||||
|
void tim2_isr(){
|
||||||
|
if(TIM2_SR & TIM_SR_UIF){ // update interrupt
|
||||||
|
TIM2_SR &= ~TIM_SR_UIF; // clear flag
|
||||||
|
TIM2_DIER = 0; // disable all timer interrupts
|
||||||
|
TIM2_CCR4 = 0; // set output value to 1
|
||||||
|
TIM2_EGR |= TIM_EGR_UG; // generate update event to change value in CCR4
|
||||||
|
TIM2_CR1 &= ~TIM_CR1_CEN; // timer_disable_counter(TIM2);
|
||||||
|
nvic_disable_irq(NVIC_TIM2_IRQ);
|
||||||
|
ow_done = 1;
|
||||||
|
rstat = lastcc3;
|
||||||
|
print_int(rstat, lastsendfun);
|
||||||
|
MSG("\n");
|
||||||
|
}
|
||||||
|
if(TIM2_SR & TIM_SR_CC3IF){ // we need this interrupt to store CCR3 value
|
||||||
|
TIM2_SR = 0; // clear flag (we've manage TIM_SR_UIF before, so can simply do =0)
|
||||||
|
lastcc3 = TIM2_CCR3;
|
||||||
|
//TIM2_DIER &= ~TIM_DIER_CC3IE; // disable CCR3 interrupts
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void dma1_channel7_isr(){
|
||||||
|
if(DMA1_ISR & DMA_ISR_TCIF7) {
|
||||||
|
DMA1_IFCR = DMA_IFCR_CTCIF7;
|
||||||
|
dma_disable_channel(DMA1, DMA_CHANNEL7);
|
||||||
|
timer_disable_irq(TIM2, TIM_DIER_CC4DE);
|
||||||
|
}else if(DMA1_ISR & DMA_ISR_TEIF7){
|
||||||
|
DMA1_IFCR = DMA_IFCR_CTEIF7;
|
||||||
|
MSG("out transfer error\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void dma1_channel1_isr(){
|
||||||
|
int i;
|
||||||
|
if(DMA1_ISR & DMA_ISR_TCIF1) {
|
||||||
|
DMA1_IFCR = DMA_IFCR_CTCIF1;
|
||||||
|
// TIM2_CCER &= ~TIM_CCER_CC4P; //timer_set_oc_polarity_high(TIM2, TIM_OC4);
|
||||||
|
TIM2_CR1 &= ~TIM_CR1_CEN; // timer_disable_counter(TIM2);
|
||||||
|
timer_disable_irq(TIM2, TIM_DIER_CC3DE);
|
||||||
|
// gpio_set(GPIOA, GPIO3);
|
||||||
|
dma_disable_channel(DMA1, DMA_CHANNEL1);
|
||||||
|
nvic_disable_irq(NVIC_DMA1_CHANNEL1_IRQ);
|
||||||
|
ow_done = 1;
|
||||||
|
for(i = 0; i < tum2buff_ctr; i++){
|
||||||
|
print_int(tim2_inbuff[i], lastsendfun);
|
||||||
|
MSG(" ");
|
||||||
|
}
|
||||||
|
MSG("\n");
|
||||||
|
}else if(DMA1_ISR & DMA_ISR_TEIF1){
|
||||||
|
DMA1_IFCR = DMA_IFCR_CTEIF1;
|
||||||
|
MSG("in transfer error\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8_t OW_get_reset_status(){
|
||||||
|
print_int(rstat, lastsendfun);
|
||||||
|
MSG("\n");
|
||||||
|
if(rstat < OW_PRESENT) return 0; // no devices
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
Loading…
x
Reference in New Issue
Block a user